projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /*++\r |
| 2 | \r | |
| 3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
| 4 | \r\r | |
| 9dc8036d MK |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 6 | \r | |
| 3cbfba02 DW |
7 | \r\r |
| 8 | \r | |
| 9 | Module Name:\r | |
| 10 | \r | |
| 11 | CK505ClockPlatformInfo.h\r | |
| 12 | \r | |
| 13 | Abstract:\r | |
| 14 | \r | |
| 15 | Protocol to communicate product clock routing information.\r | |
| 16 | \r | |
| 17 | GUID Info:\r | |
| 18 | {3C485EA4-449A-46ce-BB08-2A336EA96B4E}\r | |
| 19 | 0x3c485ea4, 0x449a, 0x46ce, 0xbb, 0x8, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e);\r | |
| 20 | \r | |
| 21 | **/\r | |
| 22 | \r | |
| 23 | #ifndef _CLOCK_PLATFORM_INFO_H_\r | |
| 24 | #define _CLOCK_PLATFORM_INFO_H_\r | |
| 25 | \r | |
| 26 | \r | |
| 27 | #define EFI_CK505_CLOCK_PLATFORM_INFO_GUID \\r | |
| 28 | {0x3c485ea4, 0x449a, 0x46ce, 0xbb, 0x8, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e}\r | |
| 29 | \r | |
| 30 | //\r | |
| 31 | // Structure to hold register modifications\r | |
| 32 | //\r | |
| 33 | typedef enum {\r | |
| 34 | None = 0x00000000,\r | |
| 35 | nICS9LP505_1 = 0x00000001,\r | |
| 36 | nICS9LP505_2 = 0x00000002,\r | |
| 37 | nIDTCV163 = 0x00000004,\r | |
| 38 | nIDTCV174 = 0x00000008,\r | |
| 39 | nSLG505YC56 = 0x00000010,\r | |
| 40 | nSLG505YC64 = 0x00000020,\r | |
| 41 | nCY28505 = 0x00000040,\r | |
| 42 | nCY28505_2 = 0x00000080,\r | |
| 43 | nCY28505LF = 0x00000100,\r | |
| 44 | nPI6C505_OLD = 0x00000200,\r | |
| 45 | nPI6C505_RevD = 0x00000400,\r | |
| 46 | nGENERIC_505 = 0x00000800,\r | |
| 47 | nSLG505YC264 = 0x00001000,\r | |
| 48 | nIDTCV183 = 0x00002000,\r | |
| 49 | nSLG505YC256 = 0x00004000,\r | |
| 50 | nIDTCV184 = 0x00008000,\r | |
| 51 | nIDTCV190 = 0x00010000,\r | |
| 52 | All = 0xFFFFFFFF\r | |
| 53 | } EFI_CLOCKS_SUPPORTED;\r | |
| 54 | \r | |
| 55 | typedef enum {\r | |
| 56 | Disabled,\r | |
| 57 | Enabled,\r | |
| 58 | EnabledWithoutSwitch,\r | |
| 59 | EnabledWithSwitch\r | |
| 60 | } EFI_SIGNAL_STATE;\r | |
| 61 | \r | |
| 62 | typedef enum {\r | |
| 63 | SrcClk11,\r | |
| 64 | SrcClk10,\r | |
| 65 | SrcClk9,\r | |
| 66 | SrcClk8,\r | |
| 67 | SrcClk7,\r | |
| 68 | SrcClk6,\r | |
| 69 | SrcClk5,\r | |
| 70 | SrcClk4,\r | |
| 71 | SrcClk3,\r | |
| 72 | SrcClk2,\r | |
| 73 | SrcClk1,\r | |
| 74 | SrcClk0,\r | |
| 75 | CpuClk1,\r | |
| 76 | CpuClk0,\r | |
| 77 | Ref0,\r | |
| 78 | Dot96,\r | |
| 79 | Usb48,\r | |
| 80 | PciClkF5,\r | |
| 81 | PciClk4,\r | |
| 82 | PciClk3,\r | |
| 83 | PciClk2,\r | |
| 84 | PciClk1,\r | |
| 85 | PciClk0,\r | |
| 86 | SaveClockConfiguration,\r | |
| 87 | MePresent,\r | |
| 88 | Cr_A,\r | |
| 89 | Cr_B,\r | |
| 90 | Cr_C,\r | |
| 91 | Cr_D,\r | |
| 92 | Cr_E,\r | |
| 93 | Cr_F,\r | |
| 94 | Cr_G,\r | |
| 95 | Cr_H,\r | |
| 96 | Clk_None // Dummy entry for dynamic detection\r | |
| 97 | } EFI_CLOCK_SIGNAL_NAME;\r | |
| 98 | \r | |
| 99 | typedef struct {\r | |
| 100 | EFI_CLOCK_SIGNAL_NAME Signal;\r | |
| 101 | EFI_SIGNAL_STATE State;\r | |
| 102 | EFI_CLOCKS_SUPPORTED Supported;\r | |
| 103 | } EFI_STATIC_SIGNALS;\r | |
| 104 | \r | |
| 105 | typedef struct {\r | |
| 106 | BOOLEAN BehindBridge;\r | |
| 107 | UINT16 BridgeBus;\r | |
| 108 | UINT16 BridgeDev;\r | |
| 109 | UINT16 BridgeFunction;\r | |
| 110 | UINT16 TargetDevice;\r | |
| 111 | EFI_CLOCK_SIGNAL_NAME Signal;\r | |
| 112 | } EFI_DYNAMIC_SIGNALS;\r | |
| 113 | \r | |
| 114 | \r | |
| 115 | typedef struct {\r | |
| 116 | EFI_STATIC_SIGNALS *StaticClockTable;\r | |
| 117 | UINTN StaticClockTableCount;\r | |
| 118 | EFI_STATIC_SIGNALS *SxClockTable;\r | |
| 119 | UINTN SxClockTableCount;\r | |
| 120 | EFI_STATIC_SIGNALS *DynamicDisabledClocksTable;\r | |
| 121 | UINTN DynamicDisabledClocksTableCount;\r | |
| 122 | } EFI_CLOCK_PLATFORM_INFO;\r | |
| 123 | \r | |
| 124 | extern EFI_GUID gEfiCk505ClockPlatformInfoGuid;\r | |
| 125 | \r | |
| 126 | #endif\r |