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1 | /*++ |
2 | ||
9ea2d901 | 3 | Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR> |
3cbfba02 DW |
4 | |
5 | ||
6 | This program and the accompanying materials are licensed and made available under | |
7 | ||
8 | the terms and conditions of the BSD License that accompanies this distribution. | |
9 | ||
10 | The full text of the license may be found at | |
11 | ||
12 | http://opensource.org/licenses/bsd-license.php. | |
13 | ||
14 | ||
15 | ||
16 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
17 | ||
18 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
19 | ||
20 | ||
21 | ||
22 | ||
23 | ||
24 | Module Name: | |
25 | ||
26 | GlobalNvsArea.h | |
27 | ||
28 | Abstract: | |
29 | ||
30 | Definition of the global NVS area protocol. This protocol | |
31 | publishes the address and format of a global ACPI NVS buffer used as a communications | |
32 | buffer between SMM code and ASL code. | |
33 | The format is derived from the ACPI reference code, version 0.95. | |
34 | ||
35 | Note: Data structures defined in this protocol are not naturally aligned. | |
36 | ||
37 | **/ | |
38 | ||
39 | ||
40 | #ifndef _GLOBAL_NVS_AREA_H_ | |
41 | #define _GLOBAL_NVS_AREA_H_ | |
42 | ||
43 | // | |
44 | // Includes | |
45 | // | |
46 | #define GLOBAL_NVS_DEVICE_ENABLE 1 | |
47 | #define GLOBAL_NVS_DEVICE_DISABLE 0 | |
48 | ||
49 | // | |
50 | // Forward reference for pure ANSI compatibility | |
51 | // | |
52 | ||
53 | //EFI_FORWARD_DECLARATION (EFI_GLOBAL_NVS_AREA_PROTOCOL); | |
54 | ||
55 | // | |
56 | // Global NVS Area Protocol GUID | |
57 | // | |
58 | #define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \ | |
59 | { 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc } | |
60 | ||
61 | // | |
62 | // Revision id - Added TPM related fields | |
63 | // | |
64 | #define GLOBAL_NVS_AREA_RIVISION_1 1 | |
65 | ||
66 | // | |
67 | // Extern the GUID for protocol users. | |
68 | // | |
69 | extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid; | |
70 | ||
71 | // | |
72 | // Global NVS Area definition | |
73 | // | |
74 | #pragma pack (1) | |
75 | typedef struct { | |
76 | // | |
77 | // Miscellaneous Dynamic Values, the definitions below need to be matched | |
78 | // GNVS definitions in Platform.ASL | |
79 | // | |
80 | UINT16 OperatingSystem; // 00 | |
81 | UINT8 SmiFunction; // 02 SMI function call via IO Trap | |
82 | UINT8 SmiParameter0; // 03 | |
83 | UINT8 SmiParameter1; // 04 | |
84 | UINT8 SciFunction; // 05 SCI function call via _L00 | |
85 | UINT8 SciParameter0; // 06 | |
86 | UINT8 SciParameter1; // 07 | |
87 | UINT8 GlobalLock; // 08 Global lock function call | |
88 | UINT8 LockParameter0; // 09 | |
89 | UINT8 LockParameter1; // 10 | |
90 | UINT32 Port80DebugValue; // 11 | |
91 | UINT8 LidState; // 15 Open = 1 | |
92 | UINT8 PowerState; // 16 AC = 1 | |
93 | UINT8 DebugState; // 17 | |
94 | ||
95 | ||
96 | // | |
97 | // Thermal Policy Values | |
98 | // | |
99 | UINT8 EnableThermalOffset; // 18 ThermalOffset for KSC | |
100 | UINT8 Reserved1; // 19 | |
101 | UINT8 Reserved2; // 20 | |
102 | UINT8 PassiveThermalTripPoint; // 21 | |
103 | UINT8 PassiveTc1Value; // 22 | |
104 | UINT8 PassiveTc2Value; // 23 | |
105 | UINT8 PassiveTspValue; // 24 | |
106 | UINT8 CriticalThermalTripPoint; // 25 | |
0ad3c505 | 107 | UINT8 EnableDigitalThermalSensor; // 26 |
3cbfba02 DW |
108 | UINT8 BspDigitalThermalSensorTemperature; // 27 Temperature of BSP |
109 | UINT8 ApDigitalThermalSensorTemperature; // 28 Temperature of AP | |
110 | UINT8 DigitalThermalSensorSmiFunction; // 29 SMI function call via DTS IO Trap | |
111 | ||
112 | // | |
113 | // Battery Support Values | |
114 | // | |
115 | UINT8 NumberOfBatteries; // 30 | |
116 | UINT8 BatteryCapacity0; // 31 Battery 0 Stored Capacity | |
117 | UINT8 BatteryCapacity1; // 32 Battery 1 Stored Capacity | |
118 | UINT8 BatteryCapacity2; // 33 Battery 2 Stored Capacity | |
119 | UINT8 BatteryStatus0; // 34 Battery 0 Stored Status | |
120 | UINT8 BatteryStatus1; // 35 Battery 1 Stored Status | |
121 | UINT8 BatteryStatus2; // 36 Battery 2 Stored Status | |
122 | ||
123 | // NOTE: Do NOT Change the Offset of Revision Field | |
124 | UINT8 Revision; // 37 Revision of the structure EFI_GLOBAL_NVS_AREA | |
125 | UINT8 Reserved3[2]; // 38:39 | |
126 | ||
127 | // | |
128 | // Processor Configuration Values | |
129 | // | |
130 | UINT8 ApicEnable; // 40 APIC Enabled by SBIOS (APIC Enabled = 1) | |
131 | UINT8 LogicalProcessorCount; // 41 Processor Count Enabled (MP Enabled != 0) | |
132 | UINT8 CurentPdcState0; // 42 PDC settings, Processor 0 | |
133 | UINT8 CurentPdcState1; // 43 PDC settings, Processor 1 | |
134 | UINT8 MaximumPpcState; // 44 Maximum PPC state | |
135 | UINT32 PpmFlags; // 45:48 PPM configuration flags, same as CFGD | |
136 | UINT8 Reserved4[1]; // 49 | |
137 | ||
138 | // | |
139 | // SIO Configuration Values | |
140 | // | |
141 | UINT8 DockedSioPresent; // 50 Dock SIO Present | |
142 | UINT8 DockComA; // 51 COM A Port | |
143 | UINT8 DockComB; // 52 COM B Port | |
144 | UINT8 LptP; // 53 LPT Port | |
145 | UINT8 DockFdc; // 54 FDC Port | |
146 | UINT8 OnboardCom; // 55 Onboard COM Port | |
147 | UINT8 OnboardComCir; // 56 Onboard COM CIR Port | |
148 | ||
149 | UINT8 WPCN381U; // 57 | |
150 | UINT8 NPCE791x; // 58 | |
151 | UINT8 Reserved5[1]; // 59 | |
152 | ||
153 | // | |
154 | // Internal Graphics Device Values | |
155 | // | |
156 | UINT8 IgdState; // 60 IGD State (Primary Display = 1) | |
157 | UINT8 DisplayToggleList; // 61 Display Toggle List Selection | |
158 | UINT8 CurrentDeviceList; // 62 Current Attached Device List | |
159 | UINT8 PreviousDeviceList; // 63 Previous Attached Device List | |
160 | UINT16 CurrentDisplayState; // 64 Current Display State | |
161 | UINT16 NextDisplayState; // 66 Next Display State | |
162 | UINT16 SetDisplayState; // 68 Set Display State | |
163 | UINT8 NumberOfValidDeviceId; // 70 Number of Valid Device IDs | |
164 | UINT32 DeviceId1; // 71 Device ID 1 | |
165 | UINT32 DeviceId2; // 75 Device ID 2 | |
166 | UINT32 DeviceId3; // 79 Device ID 3 | |
167 | UINT32 DeviceId4; // 83 Device ID 4 | |
168 | UINT32 DeviceId5; // 87 Device ID 5 | |
169 | ||
170 | UINT32 AKsv0; // 91:94 First four bytes of AKSV (manufacturing mode) | |
171 | UINT8 AKsv1; // 95 Fifth byte of AKSV (manufacturing mode | |
172 | ||
173 | UINT8 Reserved6[7]; // 96:102 | |
174 | ||
175 | // | |
176 | // Backlight Control Values | |
177 | // | |
178 | UINT8 BacklightControlSupport; // 103 Backlight Control Support | |
179 | UINT8 BrightnessPercentage; // 104 Brightness Level Percentage | |
180 | ||
181 | // | |
182 | // Ambient Light Sensor Values | |
183 | // | |
184 | UINT8 AlsEnable; // 105 Ambient Light Sensor Enable | |
185 | UINT8 AlsAdjustmentFactor; // 106 Ambient Light Adjusment Factor | |
186 | UINT8 LuxLowValue; // 107 LUX Low Value | |
187 | UINT8 LuxHighValue; // 108 LUX High Value | |
188 | ||
189 | UINT8 Reserved7[1]; // 109 | |
190 | ||
191 | // | |
192 | // Extended Mobile Access Values | |
193 | // | |
194 | UINT8 EmaEnable; // 110 EMA Enable | |
195 | UINT16 EmaPointer; // 111 EMA Pointer | |
196 | UINT16 EmaLength; // 113 EMA Length | |
197 | ||
198 | UINT8 Reserved8[1]; // 115 | |
199 | ||
200 | // | |
201 | // Mobile East Fork Values | |
202 | // | |
203 | UINT8 MefEnable; // 116 Mobile East Fork Enable | |
204 | ||
205 | // | |
206 | // PCIe Dock Status | |
207 | // | |
208 | UINT8 PcieDockStatus; // 117 PCIe Dock Status | |
209 | ||
210 | UINT8 Reserved9[2]; // 118:119 | |
211 | ||
212 | // | |
213 | // TPM Registers | |
214 | // | |
215 | UINT8 TpmPresent; // 120 TPM Present | |
216 | UINT8 TpmEnable; // 121 TPM Enable | |
217 | ||
218 | UINT8 MorData; // 122 Memory Overwrite Request Data | |
219 | UINT8 TcgParamter; // 123 Used for save the Mor and/or physical presence paramter | |
220 | UINT32 PPResponse; // 124 Physical Presence request operation response | |
221 | UINT8 PPRequest; // 128 Physical Presence request operation | |
222 | UINT8 LastPPRequest; // 129 Last Physical Presence request operation | |
223 | ||
224 | // | |
225 | // SATA Values | |
226 | // | |
227 | UINT8 GtfTaskFileBufferPort0[7]; // 130 GTF Task File Buffer for Port 0 | |
228 | UINT8 GtfTaskFileBufferPort2[7]; // 137 GTF Task File Buffer for Port 2 | |
229 | UINT8 IdeMode; // 144 IDE Mode (Compatible\Enhanced) | |
230 | UINT8 GtfTaskFileBufferPort1[7]; // 145:151 GTF Task File Buffer for Port 1 | |
231 | ||
232 | UINT8 Reserved111[10]; // 152:161 | |
233 | UINT64 BootTimeLogAddress; // 162:169 Boot Time Log Table Address | |
234 | ||
235 | UINT32 IgdOpRegionAddress; // 170 IGD OpRegion Starting Address | |
236 | UINT8 IgdBootType; // 174 IGD Boot Type CMOS option | |
237 | UINT8 IgdPanelType; // 175 IGD Panel Type CMOs option | |
238 | UINT8 IgdTvFormat; // 176 IGD TV Format CMOS option | |
239 | UINT8 IgdTvMinor; // 177 IGD TV Minor Format CMOS option | |
240 | UINT8 IgdPanelScaling; // 178 IGD Panel Scaling | |
241 | UINT8 IgdBlcConfig; // 179 IGD BLC Configuration | |
242 | UINT8 IgdBiaConfig; // 180 IGD BIA Configuration | |
243 | UINT8 IgdSscConfig; // 181 IGD SSC Configuration | |
244 | UINT8 Igd409; // 182 IGD 0409 Modified Settings Flag | |
245 | UINT8 Igd509; // 183 IGD 0509 Modified Settings Flag | |
246 | UINT8 Igd609; // 184 IGD 0609 Modified Settings Flag | |
247 | UINT8 Igd709; // 185 IGD 0709 Modified Settings Flag | |
248 | UINT8 IgdPowerConservation; // 186 IGD Power Conservation Feature Flag | |
249 | UINT8 IgdDvmtMemSize; // 187 IGD DVMT Memory Size | |
250 | UINT8 IgdFunc1Enable; // 188 IGD Function 1 Enable | |
251 | UINT8 IgdHpllVco; // 189 HPLL VCO | |
252 | UINT32 NextStateDid1; // 190 Next state DID1 for _DGS | |
253 | UINT32 NextStateDid2; // 194 Next state DID2 for _DGS | |
254 | UINT32 NextStateDid3; // 198 Next state DID3 for _DGS | |
255 | UINT32 NextStateDid4; // 202 Next state DID4 for _DGS | |
256 | UINT32 NextStateDid5; // 206 Next state DID5 for _DGS | |
257 | UINT32 NextStateDid6; // 210 Next state DID6 for _DGS | |
258 | UINT32 NextStateDid7; // 214 Next state DID7 for _DGS | |
259 | UINT32 NextStateDid8; // 218 Next state DID8 for _DGS | |
260 | UINT8 IgdSciSmiMode; // 222 GMCH SMI/SCI mode (0=SCI) | |
261 | UINT8 IgdPAVP; // 223 IGD PAVP data | |
262 | UINT8 IgdSelfRefresh; // 224 IGD Self Refresh | |
263 | UINT8 PcieOSCControl; // 225 PCIE OSC Control | |
264 | UINT8 NativePCIESupport; // 226 Native PCI Express Support | |
265 | ||
266 | // | |
267 | // USB Sideband Deferring Support | |
268 | // | |
269 | UINT8 HostAlertVector; // 227 GPE vector used for HOST_ALERT | |
270 | UINT8 HostAlertPio; // 228 PIO of USB device used for HOST_ALERT | |
271 | ||
272 | UINT8 Reserved112[27]; // 229 | |
273 | UINT32 NvIgOpRegionAddress; // 256 NVIG support | |
274 | UINT32 NvHmOpRegionAddress; // 260 NVHM support | |
275 | UINT32 ApXmOpRegionAddress; // 264 AMDA support | |
276 | UINT32 DeviceId6; // 268 Device ID 6 | |
277 | UINT32 DeviceId7; // 272 Device ID 7 | |
278 | UINT32 DeviceId8; // 276 Device ID 8 | |
279 | UINT32 EndpointBaseAddress; // 280 PEG Endpoint PCIe Base Address | |
280 | UINT32 CapStrPresence; // 284 PEG Endpoint Capability Structure Presence | |
281 | UINT32 EndpointPcieCapBaseAddress; // 288 PEG Endpoint PCIe Capability Structure Base Address | |
282 | UINT32 EndpointVcCapBaseAddress; // 292 PEG Endpoint Virtual Channel Capability Structure Base Address | |
283 | UINT32 XPcieCfgBaseAddress; // 296 Any Device's PCIe Config Space Base Address | |
284 | UINT32 OccupiedBuses1; // 300 Occupied Buses from 0 to 31 | |
285 | UINT32 OccupiedBuses2; // 304 Occupied Buses from 32 to 63 | |
286 | UINT32 OccupiedBuses3; // 308 Occupied Buses from 64 to 95 | |
287 | UINT32 OccupiedBuses4; // 312 Occupied Buses from 96 to 127 | |
288 | UINT32 OccupiedBuses5; // 316 Occupied Buses from 128 to 159 | |
289 | UINT32 OccupiedBuses6; // 320 Occupied Buses from 160 to 191 | |
290 | UINT32 OccupiedBuses7; // 324 Occupied Buses from 192 to 223 | |
291 | UINT32 OccupiedBuses8; // 328 Occupied Buses from 224 to 255 | |
292 | UINT8 UartSelection; // 332 UART Interface Selection 0: Internal; 1: SIO | |
293 | UINT8 PcuUart1Enable; // 333 PCU UART 1 Enabled | |
294 | UINT8 PcuUart2Enable; // 334 PCU UART 2 Enabled | |
295 | ||
296 | UINT32 LPEBar0; // 335~338 LPE Bar0 | |
297 | UINT32 LPEBar1; // 339~342 LPE Bar1 | |
298 | ||
299 | UINT32 LPEBar2; // 343~346 LPE Bar2 | |
300 | UINT8 AcSetup; // 347 For Ac Powered Config option - IST applet | |
301 | UINT8 BatterySetup; // 348 For Battery Powered Config option - IST applet | |
302 | UINT8 PlatformFlavor; // 349 0:unknown 1: Mobile; 2: desktop | |
303 | UINT8 Reserved113[1]; // 350 | |
304 | ||
305 | UINT8 IsctReserve; // 351 ISCT / AOAC Configuration | |
306 | UINT8 XhciMode; // 352 xHCI mode | |
307 | UINT8 PmicEnable; // 353 PMIC enable | |
308 | ||
309 | UINT8 LpeEnable; // 354 LPE enable | |
310 | UINT32 ISPAddr; // 355 ISP Base address | |
311 | UINT8 ISPDevSel; // 359 ISP device enabled selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3 | |
312 | ||
313 | // | |
314 | // Lpss controllers | |
315 | // | |
316 | UINT32 PCIBottomAddress; //360 ((4+8+6)*4+2)*4=296 | |
317 | UINT32 PCITopAddress; //364 | |
318 | ||
319 | UINT32 LDMA1Addr; // 368 | |
320 | UINT32 LDMA1Len; // 372 | |
321 | UINT32 LDMA11Addr; // 376 | |
322 | UINT32 LDMA11Len; // 380 | |
323 | UINT32 PWM1Addr; // 384 PWM1 | |
324 | UINT32 PWM1Len; // 388 | |
325 | UINT32 PWM11Addr; // 392 | |
326 | UINT32 PWM11Len; // 396 | |
327 | UINT32 PWM2Addr; // 400 PWM2 | |
328 | UINT32 PWM2Len; // 404 | |
329 | UINT32 PWM21Addr; // 408 | |
330 | UINT32 PWM21Len; // 412 | |
331 | UINT32 UART1Addr; // 416 UART1 | |
332 | UINT32 UART1Len; // 420 | |
333 | UINT32 UART11Addr; // 424 UART1 | |
334 | UINT32 UART11Len; // 428 | |
335 | UINT32 UART2Addr; // 432 UART2 | |
336 | UINT32 UART2Len; // 436 | |
337 | UINT32 UART21Addr; // 440 UART2 | |
338 | UINT32 UART21Len; // 444 | |
339 | UINT32 SPIAddr; // 448 SPI | |
340 | UINT32 SPILen; // 452 | |
341 | UINT32 SPI1Addr; // 456 | |
342 | UINT32 SPI1Len; // 460 | |
343 | ||
344 | UINT32 LDMA2Addr; // 464 | |
345 | UINT32 LDMA2Len; // 468 | |
346 | UINT32 LDMA21Addr; // 472 | |
347 | UINT32 LDMA21Len; // 476 | |
348 | UINT32 I2C1Addr; // 480 I2C1 | |
349 | UINT32 I2C1Len; // 484 | |
350 | UINT32 I2C11Addr; // 488 I2C1 | |
351 | UINT32 I2C11Len; // 492 | |
352 | UINT32 I2C2Addr; // 496 I2C2 | |
353 | UINT32 I2C2Len; // 500 | |
354 | UINT32 I2C21Addr; // 504 I2C2 | |
355 | UINT32 I2C21Len; // 508 | |
356 | UINT32 I2C3Addr; // 512 I2C3 | |
357 | UINT32 I2C3Len; // 516 | |
358 | UINT32 I2C31Addr; // 520 I2C3 | |
359 | UINT32 I2C31Len; // 524 | |
360 | UINT32 I2C4Addr; // 528 I2C4 | |
361 | UINT32 I2C4Len; // 532 | |
362 | UINT32 I2C41Addr; // 536 I2C4 | |
363 | UINT32 I2C41Len; // 540 | |
364 | UINT32 I2C5Addr; // 544 I2C5 | |
365 | UINT32 I2C5Len; // 548 | |
366 | UINT32 I2C51Addr; // 552 I2C5 | |
367 | UINT32 I2C51Len; // 556 | |
368 | UINT32 I2C6Addr; // 560 I2C6 | |
369 | UINT32 I2C6Len; // 564 | |
370 | UINT32 I2C61Addr; // 566 I2C6 | |
371 | UINT32 I2C61Len; // 570 | |
372 | UINT32 I2C7Addr; // 574 I2C7 | |
373 | UINT32 I2C7Len; // 578 | |
374 | UINT32 I2C71Addr; // 582 I2C7 | |
375 | UINT32 I2C71Len; // 586 | |
376 | ||
377 | // | |
378 | // Scc controllers | |
379 | // | |
380 | UINT32 eMMCAddr; // 590 EMMC | |
381 | UINT32 eMMCLen; // 594 | |
382 | UINT32 eMMC1Addr; // 598 | |
383 | UINT32 eMMC1Len; // 602 | |
384 | UINT32 SDIOAddr; // 606 SDIO | |
385 | UINT32 SDIOLen; // 610 | |
386 | UINT32 SDIO1Addr; // 614 | |
387 | UINT32 SDIO1Len; // 618 | |
388 | UINT32 SDCardAddr; // 622 SDCard | |
389 | UINT32 SDCardLen; // 626 | |
390 | UINT32 SDCard1Addr; // 630 | |
391 | UINT32 SDCard1Len; // 636 | |
392 | UINT32 MipiHsiAddr; // 640 MIPI-HSI | |
393 | UINT32 MipiHsiLen; // 644 | |
394 | UINT32 MipiHsi1Addr; // 648 | |
395 | UINT32 MipiHsi1Len; // 652 | |
396 | ||
397 | UINT8 SdCardRemovable; // 656 reserve offset upto 658 | |
398 | UINT8 HideLPSSDevices; // 657 Hide unsupported LPSS devices when in ACPI mode | |
399 | UINT8 ReservedO; // 658 OS Selection | |
400 | UINT8 Reserved00; // 659 | |
401 | UINT8 Reserved01; // 660 | |
402 | UINT8 Reserved02; // 661 | |
403 | UINT8 Reserved03; // 662 | |
404 | UINT8 Reserved04; // 663 | |
405 | UINT8 Reserved05; // 664 | |
406 | UINT8 Reserved06; // 665 | |
407 | UINT8 Reserved07; // 666 | |
408 | UINT8 Reserved08; // 667 | |
409 | UINT8 Reserved09; // 668 | |
410 | UINT8 Reserved0A; // 669 | |
411 | UINT32 Reserved0B; // 670 | |
412 | UINT32 Reserved0C; // 674 | |
413 | UINT32 Reserved0D; // 678 | |
414 | UINT32 Reserved0E; // 682 | |
415 | UINT32 Reserved0F; // 686 | |
416 | UINT32 Reserved10; // 690 | |
417 | UINT32 Reserved11; // 694 | |
418 | UINT32 Reserved12; // 698 | |
419 | UINT32 Reserved13; // 702 | |
420 | UINT32 Reserved14; // 706 | |
421 | UINT32 Reserved15; // 710 | |
422 | UINT32 Reserved16; // 714 | |
423 | UINT8 Reserved17; | |
424 | UINT32 Reserved18; | |
425 | UINT32 Reserved19; | |
426 | UINT32 Reserved1A; | |
427 | UINT32 Reserved1B; | |
428 | UINT32 Reserved1C; | |
429 | UINT8 Reserved1D; | |
430 | UINT32 Reserved1E; | |
431 | UINT32 Reserved1F; | |
432 | UINT32 Reserved20; | |
433 | UINT32 Reserved21; | |
434 | UINT32 Reserved22; | |
435 | UINT8 Reserved23; | |
436 | UINT8 BatteryChargingSolution; // 761 0-non ULPMC 1-ULPMC | |
437 | ||
438 | // | |
439 | //101 bytes | |
440 | // | |
441 | UINT8 NFCnSelect; // 762 NFCx Select 1: NFC1 2:NFC2 | |
442 | UINT8 LpssSccMode; // 763 EMMC device 0-ACPI mode, 1-PCI mode | |
443 | ||
444 | UINT32 TPMAddress; // 764 | |
445 | UINT32 TPMLength; // 768 | |
446 | ||
447 | UINT8 I2CTouchAddress; // 772 I2C touch address, 0x4B:RVP 0x4A:FFRD | |
448 | UINT8 IdleReserve; // 773 0 - disabled 1 - enabled | |
449 | UINT8 SDIOMode; // 774 3 - Default 2 - DDR50 | |
450 | UINT8 emmcVersion; // 775 0 - 4.41 1 - 4.5 | |
451 | UINT32 BmBound; // 776 BM Bound | |
452 | UINT8 FsaStatus; // 780 0 - Fsa is off, 1- Fsa is on | |
453 | ||
454 | // | |
455 | // Board Id | |
456 | // This field is for the ASL code to know whether this board is Baylake or Bayley Bay etc | |
457 | // | |
458 | UINT8 BoardID; // 781 | |
459 | UINT8 FabID; // 782 | |
460 | UINT8 OtgMode; // 783 0- OTG disable 1- OTG PCI mode | |
461 | UINT8 Stepping; // 784 Stepping | |
462 | UINT8 WittEnable; // 785 WITT eanble 0 - disable 1 - enable | |
463 | ||
464 | UINT8 SocStepping; // 786 Soc Stepping infomation | |
465 | UINT8 AmbientTripPointChange; // 787 DPTF: Controls whether _ATI changes other participant's trip point(enabled/disabled) | |
466 | UINT8 UtsEnable; // 788 Uart Test eanble 0 - disable 1 - enable | |
467 | UINT8 DptfReserve; // 789 | |
468 | ||
469 | UINT8 SarEnable; // 790 | |
470 | UINT8 PssDeveice; // 791 PSS Deveice: 0 - None, 1 - Monzax 2K, 2 - Monzax 8K | |
471 | UINT8 EDPV; // 792 Check for eDP display device | |
472 | UINT32 DIDX; // 793 Device ID for eDP device | |
473 | UINT8 MicrosoftIoT; // (794)JP1 pins are for Microsoft IoT project. | |
52a99493 | 474 | UINT8 RtcBattery; // (795) The Flag of RTC Battery Present. |
3cbfba02 DW |
475 | } EFI_GLOBAL_NVS_AREA; |
476 | #pragma pack () | |
477 | ||
478 | // | |
479 | // Global NVS Area Protocol | |
480 | // | |
481 | typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL { | |
482 | EFI_GLOBAL_NVS_AREA *Area; | |
483 | } EFI_GLOBAL_NVS_AREA_PROTOCOL; | |
484 | ||
485 | #endif |