projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /*++\r |
| 2 | \r | |
| 3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
| 4 | \r\r | |
| 9dc8036d MK |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 6 | \r | |
| 3cbfba02 DW |
7 | \r\r |
| 8 | \r | |
| 9 | \r | |
| 10 | Module Name:\r | |
| 11 | \r | |
| 12 | LpcWpc83667Policy.h\r | |
| 13 | \r | |
| 14 | Abstract:\r | |
| 15 | \r | |
| 16 | Protocol used for WPC83627 Policy definition.\r | |
| 17 | -------------------------------------------------------------------------------\r | |
| 18 | Rev Date<MM/DD/YYYY> Name Description\r | |
| 19 | -------------------------------------------------------------------------------\r | |
| 20 | R01 < 4/22/2011> LB Update driver for Sio83627UGH support.\r | |
| 21 | -------------------------------------------------------------------------------\r | |
| 22 | **/\r | |
| 23 | \r | |
| 24 | #ifndef _WPC83627_POLICY_PROTOCOL_H_\r | |
| 25 | #define _WPC83627_POLICY_PROTOCOL_H_\r | |
| 26 | \r | |
| 27 | EFI_FORWARD_DECLARATION (EFI_WPC83627_POLICY_PROTOCOL);\r | |
| 28 | \r | |
| 29 | #define EFI_WPC83627_POLICY_PROTOCOL_GUID \\r | |
| 30 | { \\r | |
| 31 | 0xd3ecc567, 0x9fd5, 0x44c1, 0x86, 0xcf, 0x5d, 0xa7, 0xa2, 0x4f, 0x4b, 0x5d \\r | |
| 32 | }\r | |
| 33 | \r | |
| 34 | #define EFI_WPC83627_COM1_ENABLE 0x01\r | |
| 35 | #define EFI_WPC83627_COM2_ENABLE 0x01\r | |
| 36 | \r | |
| 37 | #define EFI_WPC83627_COM3_ENABLE 0x01\r | |
| 38 | #define EFI_WPC83627_COM4_ENABLE 0x01\r | |
| 39 | \r | |
| 40 | #define EFI_WPC83627_LPT1_ENABLE 0x01\r | |
| 41 | #define EFI_WPC83627_LPT1_ENABLE 0x01\r | |
| 42 | #define EFI_WPC83627_FDD_ENABLE 0x01\r | |
| 43 | #define EFI_WPC83627_FDD_WRITE_ENABLE 0x01\r | |
| 44 | #define EFI_WPC83627_PS2_KBC_ENABLE 0x01\r | |
| 45 | #define EFI_WPC83627_ECIR_ENABLE 0x01\r | |
| 46 | \r | |
| 47 | #define EFI_WPC83627_COM1_DISABLE 0x00\r | |
| 48 | #define EFI_WPC83627_COM2_DISABLE 0x00\r | |
| 49 | \r | |
| 50 | #define EFI_WPC83627_COM3_DISABLE 0x00\r | |
| 51 | #define EFI_WPC83627_COM4_DISABLE 0x00\r | |
| 52 | \r | |
| 53 | #define EFI_WPC83627_LPT1_DISABLE 0x00\r | |
| 54 | #define EFI_WPC83627_FDD_DISABLE 0x00\r | |
| 55 | #define EFI_WPC83627_FDD_WRITE_PROTECT 0x00\r | |
| 56 | #define EFI_WPC83627_PS2_KBC_DISABLE 0x00\r | |
| 57 | #define EFI_WPC83627_ECIR_DISABLE 0x00\r | |
| 58 | #define EFI_WPC83627_RESERVED_DEFAULT 0x00\r | |
| 59 | \r | |
| 60 | typedef struct {\r | |
| 61 | UINT16 Com1 :1; // 0 = Disable, 1 = Enable\r | |
| 62 | UINT16 Lpt1 :1; // 0 = Disable, 1 = Enable\r | |
| 63 | UINT16 Floppy :1; // 0 = Disable, 1 = Enable\r | |
| 64 | UINT16 FloppyWriteProtect :1; // 0 = Write Protect, 1 = Write Enable\r | |
| 65 | UINT16 Port80 :1; // 0 = Disable, 1 = Enable\r | |
| 66 | UINT16 CIR :1; // CIR enable or disable\r | |
| 67 | UINT16 Ps2Keyboard :1; // 0 = Disable, 1 = Enable\r | |
| 68 | UINT16 Ps2Mouse :1; // 0 = Disable, 1 = Enable\r | |
| 69 | UINT16 Com2 :1; // 0 = Disable, 1 = Enable\r | |
| 70 | \r | |
| 71 | UINT16 Com3 :1; // 0 = Disable, 1 = Enable\r | |
| 72 | UINT16 Com4 :1; // 0 = Disable, 1 = Enable\r | |
| 73 | \r | |
| 74 | UINT16 Dac :1; // 0 = Disable, 1 = Enable\r | |
| 75 | UINT16 Rsvd :6;\r | |
| 76 | } EFI_WPC83627_DEVICE_ENABLES;\r | |
| 77 | \r | |
| 78 | typedef enum {\r | |
| 79 | LptModeOutput,\r | |
| 80 | LptModeBiDirectional,\r | |
| 81 | LptModeEpp,\r | |
| 82 | LptModeEcp\r | |
| 83 | } EFI_LPT_MODE;\r | |
| 84 | \r | |
| 85 | typedef struct _EFI_WPC83627_POLICY_PROTOCOL {\r | |
| 86 | EFI_WPC83627_DEVICE_ENABLES DeviceEnables;\r | |
| 87 | EFI_LPT_MODE LptMode;\r | |
| 88 | } EFI_WPC83627_POLICY_PROTOCOL;\r | |
| 89 | \r | |
| 90 | extern EFI_GUID gEfiLpcWpc83627PolicyProtocolGuid;\r | |
| 91 | \r | |
| 92 | #endif\r |