projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | ;\r |
| 2 | ; This file contains an 'Intel Sample Driver' and is\r | |
| 3 | ; licensed for Intel CPUs and chipsets under the terms of your\r | |
| 4 | ; license agreement with Intel or your vendor. This file may\r | |
| 5 | ; be modified by the user, subject to additional terms of the\r | |
| 6 | ; license agreement\r | |
| 7 | ;\r | |
| 8 | ;\r | |
| 9 | ; Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r | |
| 10 | ; \r\r | |
| 9dc8036d MK |
11 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 12 | \r | |
| 3cbfba02 DW |
13 | ; \r\r |
| 14 | ;\r | |
| 15 | \r | |
| 16 | ;Module Name:\r | |
| 17 | ;\r | |
| 18 | ; CpuIA32.c\r | |
| 19 | ;\r | |
| 20 | ;Abstract:\r | |
| 21 | ;\r | |
| 22 | ;--*/\r | |
| 23 | \r | |
| 24 | ;#include "CpuIA32.h"\r | |
| 25 | \r | |
| 26 | ;---------------------------------------------------------------------------\r | |
| 27 | .586p\r | |
| 28 | .model flat,C\r | |
| 29 | .code\r | |
| 30 | \r | |
| 31 | ;---------------------------------------------------------------------------\r | |
| 32 | ;VOID\r | |
| 33 | ;EfiHalt (\r | |
| 34 | ; VOID\r | |
| 35 | ;)\r | |
| 36 | EfiHalt PROC C PUBLIC\r | |
| 37 | hlt\r | |
| 38 | ret\r | |
| 39 | EfiHalt ENDP\r | |
| 40 | \r | |
| 41 | ;VOID\r | |
| 42 | ;EfiWbinvd (\r | |
| 43 | ; VOID\r | |
| 44 | ;)\r | |
| 45 | EfiWbinvd PROC C PUBLIC\r | |
| 46 | wbinvd\r | |
| 47 | ret\r | |
| 48 | EfiWbinvd ENDP\r | |
| 49 | \r | |
| 50 | ;VOID\r | |
| 51 | ;EfiInvd (\r | |
| 52 | ; VOID\r | |
| 53 | ;)\r | |
| 54 | EfiInvd PROC C PUBLIC\r | |
| 55 | invd\r | |
| 56 | ret\r | |
| 57 | EfiInvd ENDP\r | |
| 58 | \r | |
| 59 | ;VOID\r | |
| 60 | ;EfiCpuid (IN UINT32 RegisterInEax,\r | |
| 61 | ; OUT EFI_CPUID_REGISTER *Reg OPTIONAL)\r | |
| 62 | EfiCpuid PROC C PUBLIC\r | |
| 63 | push ebp\r | |
| 64 | mov ebp, esp\r | |
| 65 | push ebx\r | |
| 66 | push esi\r | |
| 67 | push edi\r | |
| 68 | pushad\r | |
| 69 | \r | |
| 70 | mov eax, dword ptr[ebp + 8] ;egisterInEax\r | |
| 71 | cpuid\r | |
| 72 | cmp dword ptr[ebp + 0Ch], 0 ; Reg\r | |
| 73 | je @F\r | |
| 74 | mov edi,dword ptr [ebp+0Ch] ; Reg\r | |
| 75 | \r | |
| 76 | mov dword ptr [edi],eax ; Reg->RegEax\r | |
| 77 | mov dword ptr [edi+4],ebx ; Reg->RegEbx\r | |
| 78 | mov dword ptr [edi+8],ecx ; Reg->RegEcx\r | |
| 79 | mov dword ptr [edi+0Ch],edx ; Reg->RegEdx\r | |
| 80 | \r | |
| 81 | @@:\r | |
| 82 | popad\r | |
| 83 | pop edi\r | |
| 84 | pop esi\r | |
| 85 | pop ebx\r | |
| 86 | pop ebp\r | |
| 87 | \r | |
| 88 | ret\r | |
| 89 | EfiCpuid ENDP\r | |
| 90 | \r | |
| 91 | \r | |
| 92 | ;UINT64\r | |
| 93 | ;EfiReadMsr (\r | |
| 94 | ; IN UINT32 Index\r | |
| 95 | ; );\r | |
| 96 | EfiReadMsr PROC C PUBLIC\r | |
| 97 | mov ecx, dword ptr [esp + 4]; Index\r | |
| 98 | rdmsr\r | |
| 99 | ret\r | |
| 100 | EfiReadMsr ENDP\r | |
| 101 | \r | |
| 102 | ;VOID\r | |
| 103 | ;EfiWriteMsr (\r | |
| 104 | ; IN UINT32 Index,\r | |
| 105 | ; IN UINT64 Value\r | |
| 106 | ; );\r | |
| 107 | EfiWriteMsr PROC C PUBLIC\r | |
| 108 | mov ecx, dword ptr [esp+4]; Index\r | |
| 109 | mov eax, dword ptr [esp+8]; DWORD PTR Value[0]\r | |
| 110 | mov edx, dword ptr [esp+0Ch]; DWORD PTR Value[4]\r | |
| 111 | wrmsr\r | |
| 112 | ret\r | |
| 113 | EfiWriteMsr ENDP\r | |
| 114 | \r | |
| 115 | ;UINT64\r | |
| 116 | ;EfiReadTsc (\r | |
| 117 | ; VOID\r | |
| 118 | ; )\r | |
| 119 | EfiReadTsc PROC C PUBLIC\r | |
| 120 | rdtsc\r | |
| 121 | ret\r | |
| 122 | EfiReadTsc ENDP\r | |
| 123 | \r | |
| 124 | ;VOID\r | |
| 125 | ;EfiDisableCache (\r | |
| 126 | ; VOID\r | |
| 127 | ;)\r | |
| 128 | EfiDisableCache PROC C PUBLIC\r | |
| 129 | mov eax, cr0\r | |
| 130 | bswap eax\r | |
| 131 | and al, 60h\r | |
| 132 | cmp al, 60h\r | |
| 133 | je @F\r | |
| 134 | mov eax, cr0\r | |
| 135 | or eax, 060000000h\r | |
| 136 | mov cr0, eax\r | |
| 137 | wbinvd\r | |
| 138 | @@:\r | |
| 139 | ret\r | |
| 140 | EfiDisableCache ENDP\r | |
| 141 | \r | |
| 142 | ;VOID\r | |
| 143 | ;EfiEnableCache (\r | |
| 144 | ; VOID\r | |
| 145 | ; )\r | |
| 146 | EfiEnableCache PROC C PUBLIC\r | |
| 147 | wbinvd\r | |
| 148 | mov eax, cr0\r | |
| 149 | and eax, 09fffffffh\r | |
| 150 | mov cr0, eax\r | |
| 151 | ret\r | |
| 152 | EfiEnableCache ENDP\r | |
| 153 | \r | |
| 154 | ;UINT32\r | |
| 155 | ;EfiGetEflags (\r | |
| 156 | ; VOID\r | |
| 157 | ; )\r | |
| 158 | EfiGetEflags PROC C PUBLIC\r | |
| 159 | pushfd\r | |
| 160 | pop eax\r | |
| 161 | ret\r | |
| 162 | EfiGetEflags ENDP\r | |
| 163 | \r | |
| 164 | ;VOID\r | |
| 165 | ;EfiDisableInterrupts (\r | |
| 166 | ; VOID\r | |
| 167 | ; )\r | |
| 168 | EfiDisableInterrupts PROC C PUBLIC\r | |
| 169 | cli\r | |
| 170 | ret\r | |
| 171 | EfiDisableInterrupts ENDP\r | |
| 172 | \r | |
| 173 | ;VOID\r | |
| 174 | ;EfiEnableInterrupts (\r | |
| 175 | ; VOID\r | |
| 176 | ; )\r | |
| 177 | EfiEnableInterrupts PROC C PUBLIC\r | |
| 178 | sti\r | |
| 179 | ret\r | |
| 180 | EfiEnableInterrupts ENDP\r | |
| 181 | \r | |
| 182 | ;VOID\r | |
| 183 | ;EfiCpuidExt (\r | |
| 184 | ; IN UINT32 RegisterInEax,\r | |
| 185 | ; IN UINT32 CacheLevel,\r | |
| 186 | ; OUT EFI_CPUID_REGISTER *Regs\r | |
| 187 | ; )\r | |
| 188 | EfiCpuidExt PROC C PUBLIC USES ebx edi esi\r | |
| 189 | pushad\r | |
| 190 | \r | |
| 191 | mov eax, dword ptr [esp + 30h] ; RegisterInEax\r | |
| 192 | mov ecx, dword ptr [esp + 34h] ; CacheLevel\r | |
| 193 | cpuid\r | |
| 194 | mov edi, dword ptr [esp + 38h] ; DWORD PTR Regs\r | |
| 195 | \r | |
| 196 | mov dword ptr [edi], eax ; Reg->RegEax\r | |
| 197 | mov dword ptr [edi + 4], ebx ; Reg->RegEbx\r | |
| 198 | mov dword ptr [edi + 8], ecx ; Reg->RegEcx\r | |
| 199 | mov dword ptr [edi + 0Ch], edx ; Reg->RegEdx\r | |
| 200 | \r | |
| 201 | popad\r | |
| 202 | ret\r | |
| 203 | EfiCpuidExt ENDP\r | |
| 204 | \r | |
| 205 | END\r | |
| 206 | \r |