[mirror_edk2.git] / Vlv2TbltDevicePkg / Library / EfiRegTableLib / EfiRegTableLib.c

/*++\r
\r
Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
                                                                                   \r\r
  This program and the accompanying materials are licensed and made available under\r\r
  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
  The full text of the license may be found at                                     \r\r
  http://opensource.org/licenses/bsd-license.php.                                  \r\r
                                                                                   \r\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
                                                                                   \r\r
\r
\r
Module Name:\r
\r
  EfiRegTableLib.c\r
\r
Abstract:\r
\r
  Lib function for table driven register initialization.\r
\r
Revision History\r
\r
--*/\r
\r
#include <Library/EfiRegTableLib.h>\r
#include <Library/S3BootScriptLib.h>\r
\r
//\r
// Local Functions\r
//\r
\r
/**\r
  Local worker function to process PCI_WRITE table entries.  Performs write and\r
  may also call BootScriptSave protocol if indicated in the Entry flags\r
\r
  @param Entry            A pointer to the PCI_WRITE entry to process\r
\r
  @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
                          when processing the entry.\r
\r
  @retval Nothing.\r
\r
**/\r
STATIC\r
VOID\r
PciWrite (\r
  EFI_REG_TABLE_PCI_WRITE             *Entry,\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  Status = PciRootBridgeIo->Pci.Write (\r
                                  PciRootBridgeIo,\r
                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
                                  (UINT64) Entry->PciAddress,\r
                                  1,\r
                                  &Entry->Data\r
                                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
    Status = S3BootScriptSavePciCfgWrite (\r
              (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
              (UINT64) Entry->PciAddress,\r
              1,\r
              &Entry->Data\r
              );\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
}\r
\r
/**\r
  Local worker function to process PCI_READ_MODIFY_WRITE table entries.\r
  Performs RMW write and may also call BootScriptSave protocol if indicated in\r
  the Entry flags.\r
\r
  @param Entry            A pointer to the PCI_READ_MODIFY_WRITE entry to process.\r
\r
  @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
                          when processing the entry.\r
\r
  @retval Nothing.\r
\r
**/\r
STATIC\r
VOID\r
PciReadModifyWrite (\r
  EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *Entry,\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo\r
  )\r
{\r
  EFI_STATUS  Status;\r
  UINT32      TempData;\r
\r
  Status = PciRootBridgeIo->Pci.Read (\r
                                  PciRootBridgeIo,\r
                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
                                  (UINT64) Entry->PciAddress,\r
                                  1,\r
                                  &TempData\r
                                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Entry->OrMask &= Entry->AndMask;\r
  TempData &= ~Entry->AndMask;\r
  TempData |= Entry->OrMask;\r
\r
  Status = PciRootBridgeIo->Pci.Write (\r
                                  PciRootBridgeIo,\r
                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
                                  (UINT64) Entry->PciAddress,\r
                                  1,\r
                                  &TempData\r
                                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
    Status = S3BootScriptSavePciCfgReadWrite (\r
              (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
              (UINT64) Entry->PciAddress,\r
              &Entry->OrMask,\r
              &Entry->AndMask\r
              );\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
}\r
\r
/**\r
  Local worker function to process MEM_READ_MODIFY_WRITE table entries.\r
  Performs RMW write and may also call BootScriptSave protocol if indicated in\r
  the Entry flags.\r
\r
  @param Entry            A pointer to the MEM_READ_MODIFY_WRITE entry to process.\r
\r
  @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
                          when processing the entry.\r
\r
  @retval Nothing.\r
\r
**/\r
STATIC\r
VOID\r
MemReadModifyWrite (\r
  EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *Entry,\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo\r
  )\r
{\r
  EFI_STATUS  Status;\r
  UINT32      TempData;\r
\r
  Status = PciRootBridgeIo->Mem.Read (\r
                                  PciRootBridgeIo,\r
                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
                                  (UINT64) Entry->MemAddress,\r
                                  1,\r
                                  &TempData\r
                                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Entry->OrMask &= Entry->AndMask;\r
  TempData &= ~Entry->AndMask;\r
  TempData |= Entry->OrMask;\r
\r
  Status = PciRootBridgeIo->Mem.Write (\r
                                  PciRootBridgeIo,\r
                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
                                  (UINT64) Entry->MemAddress,\r
                                  1,\r
                                  &TempData\r
                                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
    Status = S3BootScriptSaveMemReadWrite (\r
              (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
              Entry->MemAddress,\r
              &Entry->OrMask,\r
              &Entry->AndMask\r
              );\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
}\r
\r
//\r
// Exported functions\r
//\r
\r
/**\r
  Processes register table assuming which may contain PCI, IO, MEM, and STALL\r
  entries.\r
\r
  No parameter checking is done so the caller must be careful about omitting\r
  values for PciRootBridgeIo or CpuIo parameters.  If the regtable does\r
  not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply\r
  NULL).  If the regtable does not contain any IO or Mem entries, it is safe to\r
  omit the CpuIo (supply NULL).\r
\r
  The RegTableEntry parameter is not checked, but is required.\r
\r
  gBS is assumed to have been defined and is used when processing stalls.\r
\r
  The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
  entry is encountered.\r
\r
  @param RegTableEntry    A pointer to the register table to process\r
\r
  @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
                          when processing PCI table entries\r
\r
  @param CpuIo            A pointer to the instance of CpuIo that is used when processing IO and\r
                          MEM table entries\r
\r
  @retval Nothing.\r
\r
**/\r
VOID\r
ProcessRegTablePci (\r
  EFI_REG_TABLE                       *RegTableEntry,\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo,\r
  EFI_CPU_IO_PROTOCOL                 *CpuIo\r
  )\r
{\r
  while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {\r
    switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {\r
    case OP_PCI_WRITE:\r
      PciWrite ((EFI_REG_TABLE_PCI_WRITE *) RegTableEntry, PciRootBridgeIo);\r
      break;\r
\r
    case OP_PCI_READ_MODIFY_WRITE:\r
      PciReadModifyWrite ((EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);\r
      break;\r
\r
    case OP_MEM_READ_MODIFY_WRITE:\r
      MemReadModifyWrite ((EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);\r
      break;\r
\r
    default:\r
      DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));\r
      ASSERT (0);\r
      break;\r
    }\r
\r
    RegTableEntry++;\r
  }\r
}\r
\r
/**\r
  Processes register table assuming which may contain IO, MEM, and STALL\r
  entries, but must NOT contain any PCI entries.  Any PCI entries cause an\r
  ASSERT in a DEBUG build and are skipped in a free build.\r
\r
  No parameter checking is done.  Both RegTableEntry and CpuIo parameters are\r
  required.\r
\r
  gBS is assumed to have been defined and is used when processing stalls.\r
\r
  The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
  entry is encountered.\r
\r
  @param  RegTableEntry   A pointer to the register table to process\r
\r
  @param  CpuIo           A pointer to the instance of CpuIo that is used when processing IO and\r
                          MEM table entries\r
\r
  @retval Nothing.\r
\r
**/\r
VOID\r
ProcessRegTableCpu (\r
  EFI_REG_TABLE                       *RegTableEntry,\r
  EFI_CPU_IO_PROTOCOL                 *CpuIo\r
  )\r
{\r
  while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {\r
    switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {\r
    default:\r
      DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));\r
      ASSERT (0);\r
      break;\r
    }\r
\r
    RegTableEntry++;\r
  }\r
}\r
Commit	Line	Data
3cbfba02 DW	1	/*++\r
	2	\r
	3	Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
	4	\r\r
	5	This program and the accompanying materials are licensed and made available under\r\r
	6	the terms and conditions of the BSD License that accompanies this distribution. \r\r
	7	The full text of the license may be found at \r\r
	8	http://opensource.org/licenses/bsd-license.php. \r\r
	9	\r\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r
	12	\r\r
	13	\r
	14	\r
	15	Module Name:\r
	16	\r
	17	EfiRegTableLib.c\r
	18	\r
	19	Abstract:\r
	20	\r
	21	Lib function for table driven register initialization.\r
	22	\r
	23	Revision History\r
	24	\r
	25	--*/\r
	26	\r
	27	#include <Library/EfiRegTableLib.h>\r
	28	#include <Library/S3BootScriptLib.h>\r
	29	\r
	30	//\r
	31	// Local Functions\r
	32	//\r
	33	\r
	34	/**\r
	35	Local worker function to process PCI_WRITE table entries. Performs write and\r
	36	may also call BootScriptSave protocol if indicated in the Entry flags\r
	37	\r
	38	@param Entry A pointer to the PCI_WRITE entry to process\r
	39	\r
	40	@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used\r
	41	when processing the entry.\r
	42	\r
	43	@retval Nothing.\r
	44	\r
	45	**/\r
	46	STATIC\r
	47	VOID\r
	48	PciWrite (\r
	49	EFI_REG_TABLE_PCI_WRITE *Entry,\r
	50	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo\r
	51	)\r
	52	{\r
	53	EFI_STATUS Status;\r
	54	\r
	55	Status = PciRootBridgeIo->Pci.Write (\r
	56	PciRootBridgeIo,\r
	57	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
	58	(UINT64) Entry->PciAddress,\r
	59	1,\r
	60	&Entry->Data\r
	61	);\r
	62	ASSERT_EFI_ERROR (Status);\r
	63	\r
	64	if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
65	Status = S3BootScriptSavePciCfgWrite (\r
66	(EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
67	(UINT64) Entry->PciAddress,\r
68	1,\r
69	&Entry->Data\r
70	);\r
71	ASSERT_EFI_ERROR (Status);\r
72	}\r
73	}\r
74	\r
75	/**\r
76	Local worker function to process PCI_READ_MODIFY_WRITE table entries.\r
77	Performs RMW write and may also call BootScriptSave protocol if indicated in\r
78	the Entry flags.\r
79	\r
80	@param Entry A pointer to the PCI_READ_MODIFY_WRITE entry to process.\r
81	\r
82	@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used\r
83	when processing the entry.\r
84	\r
85	@retval Nothing.\r
86	\r
87	**/\r
88	STATIC\r
89	VOID\r
90	PciReadModifyWrite (\r
91	EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *Entry,\r
92	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo\r
93	)\r
94	{\r
95	EFI_STATUS Status;\r
96	UINT32 TempData;\r
97	\r
98	Status = PciRootBridgeIo->Pci.Read (\r
99	PciRootBridgeIo,\r
100	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
101	(UINT64) Entry->PciAddress,\r
102	1,\r
103	&TempData\r
104	);\r
105	ASSERT_EFI_ERROR (Status);\r
106	\r
107	Entry->OrMask &= Entry->AndMask;\r
108	TempData &= ~Entry->AndMask;\r
109	TempData \|= Entry->OrMask;\r
110	\r
111	Status = PciRootBridgeIo->Pci.Write (\r
112	PciRootBridgeIo,\r
113	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
114	(UINT64) Entry->PciAddress,\r
115	1,\r
116	&TempData\r
117	);\r
118	ASSERT_EFI_ERROR (Status);\r
119	\r
120	if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
121	Status = S3BootScriptSavePciCfgReadWrite (\r
122	(EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
123	(UINT64) Entry->PciAddress,\r
124	&Entry->OrMask,\r
125	&Entry->AndMask\r
126	);\r
127	ASSERT_EFI_ERROR (Status);\r
128	}\r
129	}\r
130	\r
131	/**\r
132	Local worker function to process MEM_READ_MODIFY_WRITE table entries.\r
133	Performs RMW write and may also call BootScriptSave protocol if indicated in\r
134	the Entry flags.\r
135	\r
136	@param Entry A pointer to the MEM_READ_MODIFY_WRITE entry to process.\r
137	\r
138	@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used\r
139	when processing the entry.\r
140	\r
141	@retval Nothing.\r
142	\r
143	**/\r
144	STATIC\r
145	VOID\r
146	MemReadModifyWrite (\r
147	EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *Entry,\r
148	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo\r
149	)\r
150	{\r
151	EFI_STATUS Status;\r
152	UINT32 TempData;\r
153	\r
154	Status = PciRootBridgeIo->Mem.Read (\r
155	PciRootBridgeIo,\r
156	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
157	(UINT64) Entry->MemAddress,\r
158	1,\r
159	&TempData\r
160	);\r
161	ASSERT_EFI_ERROR (Status);\r
162	\r
163	Entry->OrMask &= Entry->AndMask;\r
164	TempData &= ~Entry->AndMask;\r
165	TempData \|= Entry->OrMask;\r
166	\r
167	Status = PciRootBridgeIo->Mem.Write (\r
168	PciRootBridgeIo,\r
169	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
170	(UINT64) Entry->MemAddress,\r
171	1,\r
172	&TempData\r
173	);\r
174	ASSERT_EFI_ERROR (Status);\r
175	\r
176	if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
177	Status = S3BootScriptSaveMemReadWrite (\r
178	(EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
179	Entry->MemAddress,\r
180	&Entry->OrMask,\r
181	&Entry->AndMask\r
182	);\r
183	ASSERT_EFI_ERROR (Status);\r
184	}\r
185	}\r
186	\r
187	//\r
188	// Exported functions\r
189	//\r
190	\r
191	/**\r
192	Processes register table assuming which may contain PCI, IO, MEM, and STALL\r
193	entries.\r
194	\r
195	No parameter checking is done so the caller must be careful about omitting\r
196	values for PciRootBridgeIo or CpuIo parameters. If the regtable does\r
197	not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply\r
198	NULL). If the regtable does not contain any IO or Mem entries, it is safe to\r
199	omit the CpuIo (supply NULL).\r
200	\r
201	The RegTableEntry parameter is not checked, but is required.\r
202	\r
203	gBS is assumed to have been defined and is used when processing stalls.\r
204	\r
205	The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
206	entry is encountered.\r
207	\r
208	@param RegTableEntry A pointer to the register table to process\r
209	\r
210	@param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used\r
211	when processing PCI table entries\r
212	\r
213	@param CpuIo A pointer to the instance of CpuIo that is used when processing IO and\r
214	MEM table entries\r
215	\r
216	@retval Nothing.\r
217	\r
218	**/\r
219	VOID\r
220	ProcessRegTablePci (\r
221	EFI_REG_TABLE *RegTableEntry,\r
222	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
223	EFI_CPU_IO_PROTOCOL *CpuIo\r
224	)\r
225	{\r
226	while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {\r
227	switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {\r
228	case OP_PCI_WRITE:\r
229	PciWrite ((EFI_REG_TABLE_PCI_WRITE *) RegTableEntry, PciRootBridgeIo);\r
230	break;\r
231	\r
232	case OP_PCI_READ_MODIFY_WRITE:\r
233	PciReadModifyWrite ((EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);\r
234	break;\r
235	\r
236	case OP_MEM_READ_MODIFY_WRITE:\r
237	MemReadModifyWrite ((EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);\r
238	break;\r
239	\r
240	default:\r
241	DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));\r
242	ASSERT (0);\r
243	break;\r
244	}\r
245	\r
246	RegTableEntry++;\r
247	}\r
248	}\r
249	\r
250	/**\r
251	Processes register table assuming which may contain IO, MEM, and STALL\r
252	entries, but must NOT contain any PCI entries. Any PCI entries cause an\r
253	ASSERT in a DEBUG build and are skipped in a free build.\r
254	\r
255	No parameter checking is done. Both RegTableEntry and CpuIo parameters are\r
256	required.\r
257	\r
258	gBS is assumed to have been defined and is used when processing stalls.\r
259	\r
260	The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
261	entry is encountered.\r
262	\r
263	@param RegTableEntry A pointer to the register table to process\r
264	\r
265	@param CpuIo A pointer to the instance of CpuIo that is used when processing IO and\r
266	MEM table entries\r
267	\r
268	@retval Nothing.\r
269	\r
270	**/\r
271	VOID\r
272	ProcessRegTableCpu (\r
273	EFI_REG_TABLE *RegTableEntry,\r
274	EFI_CPU_IO_PROTOCOL *CpuIo\r
275	)\r
276	{\r
277	while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {\r
278	switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {\r
279	default:\r
280	DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));\r
281	ASSERT (0);\r
282	break;\r
283	}\r
284	\r
285	RegTableEntry++;\r
286	}\r
287	}\r