Vlv2TbltDevicePkg: Remove SMM binary modules from FDF

[mirror_edk2.git] / Vlv2TbltDevicePkg / Library / SerialPortLib / SioInit.c

/** @file\r
\r
  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
                                                                                   \r\r
  This program and the accompanying materials are licensed and made available under\r\r
  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
  The full text of the license may be found at                                     \r\r
  http://opensource.org/licenses/bsd-license.php.                                  \r\r
                                                                                   \r\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
                                                                                   \r\r
\r
Module Name:\r
\r
    SioInit.c\r
\r
Abstract:\r
\r
    Functions for LpcSio initialization\r
\r
--*/\r
\r
#include "PlatformSerialPortLib.h"\r
#include "SioInit.h"\r
\r
typedef struct {\r
  UINT8 Register;\r
  UINT8 Value;\r
} EFI_SIO_TABLE;\r
\r
EFI_SIO_TABLE mSioTableWpcn381u[] = {\r
    {0x29, 0x0A0},\r
    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0},                                       // Select UART0 device\r
    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)},       // Set Base Address MSB\r
    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB\r
    {WPCN381U_IRQ1_REGISTER, 0x014},                                                      // Set to IRQ4\r
    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1},                                       // Select UART1 device\r
    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)},       // Set Base Address MSB\r
    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB\r
    {WPCN381U_IRQ1_REGISTER, 0x013},                                                      // Set to IRQ3\r
    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO},                                        // Select GPIO device\r
    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)},               // Set Base Address MSB\r
    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)},           // Set Base Address LSB\r
    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
    {0x21, 0x001},                                                                        // Global Device Enable\r
    {0x26, 0x000}\r
};\r
\r
EFI_SIO_TABLE mSioTableWdcp376[] = {\r
    {0x29, 0x0A0},\r
    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0},                                       // Select UART0 device\r
    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)},       // Set Base Address MSB\r
    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB\r
    {WPCN381U_IRQ1_REGISTER, 0x014},                                                      // Set to IRQ4\r
    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1},                                       // Select UART1 device\r
    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)},       // Set Base Address MSB\r
    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB\r
    {WPCN381U_IRQ1_REGISTER, 0x013},                                                      // Set to IRQ3\r
    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO},                                        // Select GPIO device\r
    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)},               // Set Base Address MSB\r
    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)},           // Set Base Address LSB\r
    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
    {0x21, 0x001},                                                                        // Global Device Enable\r
    {0x26, 0x000},\r
    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K},                                        // Select PS2 Keyboard\r
    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)},                // Set Base Address MSB\r
    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)},            // Set Base Address LSB\r
    {WPCN381U_BASE2_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)},                // Set Base Address MSB\r
    {WPCN381U_BASE2_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)},            // Set Base Address LSB\r
    {WPCN381U_IRQ1_REGISTER, 0x011},                                                      // Set to IRQ1\r
    {0xF0, (SIO_KBC_CLOCK << 6)},                                                         // Select KBC Clock Source\r
    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M},                                        // Select PS2 Mouse\r
    {WPCN381U_IRQ1_REGISTER, 0x01c},                                                      // Set to IRQ12\r
    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}                                 // Enable it with Activation bit\r
};\r
\r
/**\r
  Initialization for SIO.\r
\r
  @param FfsHeader     FV this PEIM was loaded from.\r
  @param PeiServices   General purpose services available to every PEIM.\r
\r
  None\r
\r
**/\r
VOID\r
InitializeSio (\r
  VOID\r
  )\r
{\r
  UINT16          Index;\r
  UINT16          IndexPort;\r
  UINT16          DataPort;\r
\r
  //\r
  // Super I/O initialization for Winbond WPCN381U\r
  //\r
  IndexPort  = WPCN381U_CONFIG_INDEX;\r
  DataPort   = WPCN381U_CONFIG_DATA;\r
\r
  //\r
  // Check for Winbond WPCN381U\r
  //\r
  IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER);   // Winbond WPCN381U Device ID register is 0x20\r
\r
  if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) {   // Winbond WPCN381U Device ID is 0xF4\r
    //\r
    // Configure WPCN381U SIO\r
    //\r
    for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {\r
      IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);\r
      IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);\r
    }\r
  }\r
\r
  if (IoRead8 (DataPort) == WDCP376_CHIP_ID) {   // Winbond WDCP376 Device ID is 0xF1\r
    //\r
    // Configure WDCP376 SIO\r
    //\r
    for (Index = 0; Index < sizeof (mSioTableWdcp376) / sizeof (EFI_SIO_TABLE); Index++) {\r
      IoWrite8 (IndexPort, mSioTableWdcp376[Index].Register);\r
      IoWrite8 (DataPort, mSioTableWdcp376[Index].Value);\r
    }\r
  }\r
  return;\r
}\r