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1/** @file\r
2\r
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
4 \r\r
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5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
6\r
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7 \r\r
8\r
9Module Name:\r
10\r
11 SioInit.c\r
12\r
13Abstract:\r
14\r
15 Functions for LpcSio initialization\r
16\r
17--*/\r
18\r
19#include "PlatformSerialPortLib.h"\r
20#include "SioInit.h"\r
21\r
22typedef struct {\r
23 UINT8 Register;\r
24 UINT8 Value;\r
25} EFI_SIO_TABLE;\r
26\r
27EFI_SIO_TABLE mSioTableWpcn381u[] = {\r
28 {0x29, 0x0A0},\r
29 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device\r
30 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB\r
31 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB\r
32 {WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4\r
33 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r
34 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device\r
35 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB\r
36 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB\r
37 {WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3\r
38 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r
39 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device\r
40 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB\r
41 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB\r
42 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r
43 {0x21, 0x001}, // Global Device Enable\r
44 {0x26, 0x000}\r
45};\r
46\r
47EFI_SIO_TABLE mSioTableWdcp376[] = {\r
48 {0x29, 0x0A0},\r
49 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device\r
50 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB\r
51 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB\r
52 {WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4\r
53 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r
54 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device\r
55 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB\r
56 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB\r
57 {WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3\r
58 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r
59 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device\r
60 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB\r
61 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB\r
62 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r
63 {0x21, 0x001}, // Global Device Enable\r
64 {0x26, 0x000},\r
65 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K}, // Select PS2 Keyboard\r
66 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)}, // Set Base Address MSB\r
67 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)}, // Set Base Address LSB\r
68 {WPCN381U_BASE2_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)}, // Set Base Address MSB\r
69 {WPCN381U_BASE2_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)}, // Set Base Address LSB\r
70 {WPCN381U_IRQ1_REGISTER, 0x011}, // Set to IRQ1\r
71 {0xF0, (SIO_KBC_CLOCK << 6)}, // Select KBC Clock Source\r
72 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r
73 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M}, // Select PS2 Mouse\r
74 {WPCN381U_IRQ1_REGISTER, 0x01c}, // Set to IRQ12\r
75 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE} // Enable it with Activation bit\r
76};\r
77\r
78/**\r
79 Initialization for SIO.\r
80\r
81 @param FfsHeader FV this PEIM was loaded from.\r
82 @param PeiServices General purpose services available to every PEIM.\r
83\r
84 None\r
85\r
86**/\r
87VOID\r
88InitializeSio (\r
89 VOID\r
90 )\r
91{\r
92 UINT16 Index;\r
93 UINT16 IndexPort;\r
94 UINT16 DataPort;\r
95\r
96 //\r
97 // Super I/O initialization for Winbond WPCN381U\r
98 //\r
99 IndexPort = WPCN381U_CONFIG_INDEX;\r
100 DataPort = WPCN381U_CONFIG_DATA;\r
101\r
102 //\r
103 // Check for Winbond WPCN381U\r
104 //\r
105 IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER); // Winbond WPCN381U Device ID register is 0x20\r
106\r
107 if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) { // Winbond WPCN381U Device ID is 0xF4\r
108 //\r
109 // Configure WPCN381U SIO\r
110 //\r
111 for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {\r
112 IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);\r
113 IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);\r
114 }\r
115 }\r
116\r
117 if (IoRead8 (DataPort) == WDCP376_CHIP_ID) { // Winbond WDCP376 Device ID is 0xF1\r
118 //\r
119 // Configure WDCP376 SIO\r
120 //\r
121 for (Index = 0; Index < sizeof (mSioTableWdcp376) / sizeof (EFI_SIO_TABLE); Index++) {\r
122 IoWrite8 (IndexPort, mSioTableWdcp376[Index].Register);\r
123 IoWrite8 (DataPort, mSioTableWdcp376[Index].Value);\r
124 }\r
125 }\r
126 return;\r
127}\r