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1 | /** @file\r |
2 | Header file of Serial port hardware definition.\r | |
3 | \r | |
4 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
5 | \r\r | |
6 | This program and the accompanying materials are licensed and made available under\r\r | |
7 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
8 | The full text of the license may be found at \r\r | |
9 | http://opensource.org/licenses/bsd-license.php. \r\r | |
10 | \r\r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
13 | \r\r | |
14 | This software and associated documentation\r | |
15 | (if any) is furnished under a license and may only be used or\r | |
16 | copied in accordance with the terms of the license. Except as\r | |
17 | permitted by such license, no part of this software or\r | |
18 | documentation may be reproduced, stored in a retrieval system, or\r | |
19 | transmitted in any form or by any means without the express written\r | |
20 | consent of Intel Corporation.\r | |
21 | \r | |
22 | Module Name: PlatformSerialPortLib.h\r | |
23 | \r | |
24 | **/\r | |
25 | \r | |
26 | #ifndef _SIO_INIT_H_\r | |
27 | #define _SIO_INIT_H_\r | |
28 | \r | |
29 | #define WPCN381U_CONFIG_INDEX 0x2E\r | |
30 | #define WPCN381U_CONFIG_DATA 0x2F\r | |
31 | #define WPCN381U_CONFIG_INDEX1 0x164E\r | |
32 | #define WPCN381U_CONFIG_DATA1 0x164F\r | |
33 | #define WPCN381U_CHIP_ID 0xF4\r | |
34 | #define WDCP376_CHIP_ID 0xF1\r | |
35 | \r | |
36 | //\r | |
37 | // SIO Logical Devices Numbers\r | |
38 | //\r | |
39 | #define WPCN381U_LDN_UART0 0x03 // LDN for Serial Port Controller\r | |
40 | #define WPCN381U_LDN_UART1 0x02 // LDN for Parallel Port Controller\r | |
41 | #define WPCN381U_LDN_PS2K 0x06 // LDN for PS2 Keyboard Controller\r | |
42 | #define WPCN381U_LDN_PS2M 0x05 // LDN for PS2 Mouse Controller\r | |
43 | #define WPCN381U_KB_BASE1_ADDRESS 0x60 // Base Address of KB controller\r | |
44 | #define WPCN381U_KB_BASE2_ADDRESS 0x64 // Base Address of KB controller\r | |
45 | #define SIO_KBC_CLOCK 0x01 // 0/1/2 - 8/12/16 MHz KBC Clock Source\r | |
46 | #define WPCN381U_LDN_GPIO 0x07 // LDN for GPIO\r | |
47 | \r | |
48 | //\r | |
49 | // SIO Registers Layout\r | |
50 | //\r | |
51 | #define WPCN381U_LD_SEL_REGISTER 0x07 // Logical Device Select Register Address\r | |
52 | #define WPCN381U_DEV_ID_REGISTER 0x20 // Device Identification Register Address\r | |
53 | #define WPCN381U_ACTIVATE_REGISTER 0x30 // Device Identification Register Address\r | |
54 | #define WPCN381U_BASE1_HI_REGISTER 0x60 // Device BaseAddres Register #1 MSB Address\r | |
55 | #define WPCN381U_BASE1_LO_REGISTER 0x61 // Device BaseAddres Register #1 LSB Address\r | |
56 | #define WPCN381U_BASE2_HI_REGISTER 0x62 // Device BaseAddres Register #1 MSB Address\r | |
57 | #define WPCN381U_BASE2_LO_REGISTER 0x63 // Device Ba1eAddres Register #1 LSB Address\r | |
58 | #define WPCN381U_IRQ1_REGISTER 0x70 // Device IRQ Register #1 Address\r | |
59 | #define WPCN381U_IRQ2_REGISTER 0x71 // Device IRQ Register #2 Address\r | |
60 | \r | |
61 | //\r | |
62 | // SIO Activation Values\r | |
63 | //\r | |
64 | #define WPCN381U_ACTIVATE_VALUE 0x01 // Value to activate Device\r | |
65 | #define WPCN381U_DEACTIVATE_VALUE 0x00 // Value to deactivate Device\r | |
66 | \r | |
67 | //\r | |
68 | // SIO GPIO\r | |
69 | //\r | |
70 | #define WPCN381U_GPIO_BASE_ADDRESS 0x0A20 // SIO GPIO Base Address\r | |
71 | \r | |
72 | //\r | |
73 | // SIO Serial Port Settings\r | |
74 | //\r | |
75 | #define WPCN381U_SERIAL_PORT0_BASE_ADDRESS 0x03F8 // Base Address of Serial Port 0 (COMA / UART0)\r | |
76 | #define WPCN381U_SERIAL_PORT1_BASE_ADDRESS 0x02F8 // Base Address of Serial Port 1 (COMB / UART1)\r | |
77 | \r | |
78 | #endif\r |