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1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | Module Name:\r | |
15 | \r | |
16 | \r | |
17 | PeiPostCode.c\r | |
18 | \r | |
19 | Abstract:\r | |
20 | \r | |
21 | Worker functions for PostCode\r | |
22 | \r | |
23 | --*/\r | |
24 | \r | |
25 | #include "EfiStatusCode.h"\r | |
26 | \r | |
27 | #pragma pack(1)\r | |
28 | typedef struct {\r | |
29 | EFI_STATUS_CODE_VALUE StatusValue;\r | |
30 | UINT8 Port80Value;\r | |
31 | } EFI_STATUS_CODE_TO_PORT_80;\r | |
32 | #pragma pack()\r | |
33 | \r | |
34 | //\r | |
35 | // see Edk\Foundation\Library\EfiCommonLib\PostCode.c for DXE/BDS POST codes.\r | |
36 | //\r | |
37 | EFI_STATUS_CODE_TO_PORT_80 mPeiPort80Table[] = {\r | |
38 | //\r | |
39 | // Platform init\r | |
40 | //\r | |
41 | {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_INIT, 0x11},\r | |
42 | {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP1, 0x12},\r | |
43 | {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP2, 0x13},\r | |
44 | {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP3, 0x14},\r | |
45 | {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP4, 0x15},\r | |
46 | \r | |
47 | //\r | |
48 | // SMBUS\r | |
49 | //\r | |
50 | {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_INIT, 0x16},\r | |
51 | {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_EXEC_ENTRY, 0x17},\r | |
52 | {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_EXEC_EXIT, 0x18},\r | |
53 | \r | |
54 | //\r | |
55 | // Clock\r | |
56 | //\r | |
57 | {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_ENTRY, 0x19},\r | |
58 | {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_EXIT, 0x1A},\r | |
59 | \r | |
60 | //\r | |
61 | // Over clocking support\r | |
62 | //\r | |
63 | {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_OVERCLOCK_PEI_INIT_ENTRY, 0x1B},\r | |
64 | {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_OVERCLOCK_PEI_INIT_EXIT, 0x1C},\r | |
65 | \r | |
66 | //\r | |
67 | // MRC\r | |
68 | //\r | |
69 | {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_INIT_BEGIN, 0x21},\r | |
70 | {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_SPD_READ, 0x23},\r | |
71 | {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PRESENCE_DETECT, 0x24},\r | |
72 | {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_TIMING, 0x25},\r | |
73 | {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_OPTIMIZING, 0x26},\r | |
74 | {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_CONFIGURING, 0x27},\r | |
75 | {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_TEST, 0x28},\r | |
76 | {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_COMPLETE, 0x29},\r | |
77 | \r | |
78 | //\r | |
79 | // Platform Init after MRC\r | |
80 | //\r | |
81 | {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PROG_MTRR, 0x2A},\r | |
82 | {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PROG_MTRR_END, 0x2B},\r | |
83 | \r | |
84 | {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_BEGIN, 0x31},\r | |
85 | {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_AUTO, 0x32},\r | |
86 | {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_LOAD, 0x33},\r | |
87 | {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_START, 0x34},\r | |
88 | {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_EC_NO_RECOVERY_CAPSULE, 0x35},\r | |
89 | \r | |
90 | {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_INIT, 0x41},\r | |
91 | {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_STEP1, 0x42},\r | |
92 | {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_END, 0x43},\r | |
93 | {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_PEI_INIT, 0x44},\r | |
94 | {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_PEI_STEP1, 0x45},\r | |
95 | {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_PEI_END, 0x46}\r | |
96 | };\r | |
97 | \r | |
98 | BOOLEAN\r | |
99 | PeiCodeTypeToPostCode (\r | |
100 | IN EFI_STATUS_CODE_TYPE CodeType,\r | |
101 | IN EFI_STATUS_CODE_VALUE Value,\r | |
102 | OUT UINT8 *PostCode\r | |
103 | )\r | |
104 | {\r | |
105 | UINTN Index;\r | |
106 | \r | |
107 | if (CodeType == EFI_PROGRESS_CODE) {\r | |
108 | if ((Value == (EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT_BEGIN)) ||\r | |
109 | (Value == (EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT_END)) ||\r | |
110 | (Value == (EFI_SOFTWARE_DXE_CORE | EFI_SW_PC_INIT_BEGIN)) ||\r | |
111 | (Value == (EFI_SOFTWARE_DXE_CORE | EFI_SW_PC_INIT_END))) {\r | |
112 | return FALSE;\r | |
113 | }\r | |
114 | } else {\r | |
115 | return FALSE;\r | |
116 | }\r | |
117 | \r | |
118 | for (Index = 0; Index < sizeof(mPeiPort80Table)/sizeof(EFI_STATUS_CODE_TO_PORT_80); Index++) {\r | |
119 | if (mPeiPort80Table[Index].StatusValue == Value) {\r | |
120 | *PostCode = mPeiPort80Table[Index].Port80Value;\r | |
121 | return TRUE;\r | |
122 | }\r | |
123 | }\r | |
124 | \r | |
125 | return FALSE;\r | |
126 | }\r |