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1/** @file\r
2\r
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
4 \r\r
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5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
6\r
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7 \r\r
8\r
9Module Name:\r
10\r
11\r
12 ClockControl.c\r
13\r
14Abstract:\r
15\r
16 Sets platform/SKU specific clock routing information.\r
17\r
18\r
19\r
20--*/\r
21\r
22#include "PlatformDxe.h"\r
23#include <Protocol/CK505ClockPlatformInfo.h>\r
24\r
25//\r
26// Default clock routing informtion (All On)\r
27//\r
28EFI_CLOCK_PLATFORM_INFO mDefClockPolicy = {NULL, 0, NULL, 0, NULL, 0};\r
29\r
30//\r
31// Clock Settings\r
32//\r
33// Static clock table.\r
34// This should be used to define any clock settings that are static\r
35// (Always On or Always Off). Dynamic clocks should be set to enabled\r
36// in this table.\r
37//\r
38EFI_STATIC_SIGNALS mAtxStaticClocks[] = {\r
39 {SrcClk8, Enabled, All},\r
40 {SrcClk7, Enabled, All},\r
41 {SrcClk6, Enabled, All},\r
42 {SrcClk5, Enabled, All},\r
43 {SrcClk4, Enabled, All},\r
44 {SrcClk3, Enabled, All},\r
45 {SrcClk2, Enabled, All},\r
46 {SrcClk1, Enabled, All},\r
47 {SrcClk0, Enabled, All},\r
48 {Ref0, Enabled, All},\r
49 {Dot96, Enabled, All},\r
50 {Usb48, Enabled, All},\r
51 {PciClkF5, Enabled, All},\r
52 {PciClk0, Enabled, All},\r
53 {PciClk2, Enabled, All},\r
54 {PciClk3, Enabled, All},\r
55 {PciClk4, Disabled, All},\r
56 {Cr_B, EnabledWithSwitch, All},\r
57};\r
58\r
59//\r
60// ClockSxInfo Table\r
61// This is a list of clocks that need to be set to a known state when the\r
62// system enters S4 or S5.\r
63//\r
64EFI_STATIC_SIGNALS mAtxSxClocks[] = {\r
65 {SaveClockConfiguration, Disabled, All}\r
66};\r
67\r
68//\r
69// ATX settings structure\r
70//\r
71EFI_CLOCK_PLATFORM_INFO mAtxClockSettings = {\r
72 mAtxStaticClocks,\r
73 sizeof(mAtxStaticClocks) / sizeof(mAtxStaticClocks[0]),\r
74 mAtxSxClocks,\r
75 sizeof(mAtxSxClocks) / sizeof(mAtxSxClocks[0])\r
76};\r
77\r
78#if defined( RVP_SUPPORT ) && RVP_SUPPORT\r
79//\r
80// RVP Clock Settings\r
81//\r
82// Static clock table.\r
83// This should be used to define any clock settings that are static\r
84// (Always On or Always Off). Dynamic clocks should be set to enabled\r
85// in this table.\r
86//\r
87//UPSD_TBD Check with Jan if any porting required.\r
88//\r
89EFI_STATIC_SIGNALS mRvpStaticClocks[] = {\r
90 {SrcClk11, Enabled, All}, // Not used/not present but leave coding enabled\r
91 {SrcClk10, Enabled, All}, // Not used/not present but leave coding enabled\r
92 {SrcClk9, Enabled, All}, // Not used/not present but leave coding enabled\r
93 {SrcClk8, Enabled, All}, // ICHSATAII\r
94 {SrcClk7, Enabled, All}, // DPL_REFSSCLKIN\r
95 {SrcClk6, Enabled, All}, // 100M_MCH\r
96 {SrcClk5, Enabled, All}, // Mini-PCIe //TODO PNV: Need to check ICH GPIO38:\r
97 // 0: turn on; 1: turn off\r
98 {SrcClk4, Enabled, All}, // ICHSATA\r
99 {SrcClk3, Enabled, All}, // 100M_ICH\r
100 {SrcClk2, Enabled, All}, // 100M_LAN\r
101 {SrcClk1, Enabled, All}, // 25M_LAN\r
102 {SrcClk0, Enabled, All}, // 96M_DREF\r
103 {Ref0, Enabled, All},\r
104 {Dot96, Enabled, All},\r
105 {Usb48, Enabled, All},\r
106 {PciClkF5, Enabled, All}, // 33M_ICH\r
107 {PciClk0, Enabled, All}, // 33M_RISER\r
108 {PciClk1, Enabled, All}, // 33M_RISER\r
109 {PciClk2, Enabled, All}, // VDD_Clock\r
110 {PciClk3, Enabled, All}, // 33M_S1\r
111 {PciClk4, Enabled, All}, // 33M_PA\r
112};\r
113\r
114//\r
115// Dynamic clock table\r
116// This is used to determine if a clock should be left on or turned off based\r
117// on the presence of a device. The bridge information is used so the bus\r
118// number for the device to be detected can be found.\r
119//\r
120\r
121//\r
122// ClockSxInfo Table\r
123// This is a list of clocks that need to be set to a known state when the\r
124// system enters S4 or S5.\r
125//\r
126EFI_STATIC_SIGNALS mRvpSxClocks[] = {\r
127 {SaveClockConfiguration, Disabled, All}\r
128};\r
129\r
130//\r
131// RVP settings structure\r
132//\r
133EFI_CLOCK_PLATFORM_INFO mRvpClockSettings = {\r
134 mRvpStaticClocks,\r
135 sizeof(mRvpStaticClocks) / sizeof(mRvpStaticClocks[0]),\r
136 0, // No clocks will be turned off mRvpDynamicClocks,\r
137 0, // No clocks will be turned off sizeof(mRvpDynamicClocks) / sizeof(mRvpDynamicClocks[0]),\r
138 mRvpSxClocks,\r
139 sizeof(mRvpSxClocks) / sizeof(mRvpSxClocks[0])\r
140};\r
141#endif\r
142\r
143VOID\r
144InitializeClockRouting(\r
145 )\r
146{\r
147 EFI_STATUS Status;\r
148 UINTN BoardIdVarSize;\r
149 EFI_BOARD_FEATURES BoardIdVar;\r
150 EFI_CLOCK_PLATFORM_INFO *ClockPolicy;\r
151 EFI_HANDLE Handle;\r
152\r
153 ClockPolicy = &mDefClockPolicy;\r
154\r
155 //\r
156 // Do modifications based on board type\r
157 //\r
158 BoardIdVarSize = sizeof (EFI_BOARD_FEATURES);\r
159 Status = gRT->GetVariable (\r
160 BOARD_FEATURES_NAME,\r
161 &gEfiBoardFeaturesGuid,\r
162 NULL,\r
163 &BoardIdVarSize,\r
164 &BoardIdVar\r
165 );\r
166 if (!EFI_ERROR (Status)) {\r
167\r
168#if defined( RVP_SUPPORT ) && RVP_SUPPORT\r
169 if (BoardIdVar & B_BOARD_FEATURES_RVP) {\r
170 ClockPolicy = &mRvpClockSettings;\r
171 }\r
172#else\r
173\r
174 //\r
175 // Isolate board type information\r
176 //\r
177 BoardIdVar = BoardIdVar & (B_BOARD_FEATURES_FORM_FACTOR_ATX |\r
178 B_BOARD_FEATURES_FORM_FACTOR_BTX |\r
179 B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX |\r
180 B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX);\r
181\r
182 if (BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_ATX ||\r
183 BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX) {\r
184 ClockPolicy = &mAtxClockSettings;\r
185 }\r
186\r
187#endif\r
188\r
189 }\r
190\r
191 Handle = NULL;\r
192 Status = gBS->InstallProtocolInterface (\r
193 &Handle,\r
194 &gEfiCk505ClockPlatformInfoGuid,\r
195 EFI_NATIVE_INTERFACE,\r
196 ClockPolicy\r
197 );\r
198 ASSERT_EFI_ERROR(Status);\r
199\r
200}\r
201\r
202\r