[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformDxe / PciBus.h

/*++\r
\r
  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
                                                                                   \r\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
                                                                                   \r\r
\r
**/\r
\r
\r
#ifndef _EFI_PCI_BUS_H_\r
#define _EFI_PCI_BUS_H_\r
\r
#include <PiDxe.h>\r
\r
#include <Protocol/LoadedImage.h>\r
#include <Protocol/PciHostBridgeResourceAllocation.h>\r
#include <Protocol/PciIo.h>\r
#include <Protocol/LoadFile2.h>\r
#include <Protocol/PciRootBridgeIo.h>\r
#include <Protocol/PciHotPlugRequest.h>\r
#include <Protocol/DevicePath.h>\r
#include <Protocol/PciPlatform.h>\r
#include <Protocol/PciHotPlugInit.h>\r
#include <Protocol/Decompress.h>\r
#include <Protocol/BusSpecificDriverOverride.h>\r
#include <Protocol/IncompatiblePciDeviceSupport.h>\r
#include <Protocol/PciOverride.h>\r
#include <Protocol/PciEnumerationComplete.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/BaseLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DevicePathLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PeCoffLib.h>\r
\r
#include <IndustryStandard/Pci.h>\r
#include <IndustryStandard/PeImage.h>\r
#include <IndustryStandard/Acpi.h>\r
\r
typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;\r
typedef struct _PCI_BAR                    PCI_BAR;\r
\r
#define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)\r
#define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)\r
\r
#define     EFI_PCI_IOV_POLICY_ARI           0x0001\r
#define     EFI_PCI_IOV_POLICY_SRIOV         0x0002\r
#define     EFI_PCI_IOV_POLICY_MRIOV         0x0004\r
\r
typedef enum {\r
  PciBarTypeUnknown = 0,\r
  PciBarTypeIo16,\r
  PciBarTypeIo32,\r
  PciBarTypeMem32,\r
  PciBarTypePMem32,\r
  PciBarTypeMem64,\r
  PciBarTypePMem64,\r
  PciBarTypeIo,\r
  PciBarTypeMem,\r
  PciBarTypeMaxType\r
} PCI_BAR_TYPE;\r
\r
\r
#define VGABASE1  0x3B0\r
#define VGALIMIT1 0x3BB\r
\r
#define VGABASE2  0x3C0\r
#define VGALIMIT2 0x3DF\r
\r
#define ISABASE   0x100\r
#define ISALIMIT  0x3FF\r
\r
//\r
// PCI BAR parameters\r
//\r
struct _PCI_BAR {\r
  UINT64        BaseAddress;\r
  UINT64        Length;\r
  UINT64        Alignment;\r
  PCI_BAR_TYPE  BarType;\r
  BOOLEAN       Prefetchable;\r
  UINT8         MemType;\r
  UINT16        Offset;\r
};\r
\r
//\r
// defined in PCI Card Specification, 8.0\r
//\r
#define PCI_CARD_MEMORY_BASE_0                0x1C\r
#define PCI_CARD_MEMORY_LIMIT_0               0x20\r
#define PCI_CARD_MEMORY_BASE_1                0x24\r
#define PCI_CARD_MEMORY_LIMIT_1               0x28\r
#define PCI_CARD_IO_BASE_0_LOWER              0x2C\r
#define PCI_CARD_IO_BASE_0_UPPER              0x2E\r
#define PCI_CARD_IO_LIMIT_0_LOWER             0x30\r
#define PCI_CARD_IO_LIMIT_0_UPPER             0x32\r
#define PCI_CARD_IO_BASE_1_LOWER              0x34\r
#define PCI_CARD_IO_BASE_1_UPPER              0x36\r
#define PCI_CARD_IO_LIMIT_1_LOWER             0x38\r
#define PCI_CARD_IO_LIMIT_1_UPPER             0x3A\r
#define PCI_CARD_BRIDGE_CONTROL               0x3E\r
\r
#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
\r
#define PPB_BAR_0                             0\r
#define PPB_BAR_1                             1\r
#define PPB_IO_RANGE                          2\r
#define PPB_MEM32_RANGE                       3\r
#define PPB_PMEM32_RANGE                      4\r
#define PPB_PMEM64_RANGE                      5\r
#define PPB_MEM64_RANGE                       0xFF\r
\r
#define P2C_BAR_0                             0\r
#define P2C_MEM_1                             1\r
#define P2C_MEM_2                             2\r
#define P2C_IO_1                              3\r
#define P2C_IO_2                              4\r
\r
#define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001\r
#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002\r
#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004\r
#define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008\r
#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020\r
#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040\r
\r
#define PCI_MAX_HOST_BRIDGE_NUM               0x0010\r
\r
//\r
// Define option for attribute\r
//\r
#define EFI_SET_SUPPORTS    0\r
#define EFI_SET_ATTRIBUTES  1\r
\r
#define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')\r
\r
struct _PCI_IO_DEVICE {\r
  UINT32                                    Signature;\r
  EFI_HANDLE                                Handle;\r
  EFI_PCI_IO_PROTOCOL                       PciIo;\r
  LIST_ENTRY                                Link;\r
\r
  EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
  EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;\r
  EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;\r
\r
  //\r
  // PCI configuration space header type\r
  //\r
  PCI_TYPE00                                Pci;\r
\r
  //\r
  // Bus number, Device number, Function number\r
  //\r
  UINT8                                     BusNumber;\r
  UINT8                                     DeviceNumber;\r
  UINT8                                     FunctionNumber;\r
\r
  //\r
  // BAR for this PCI Device\r
  //\r
  PCI_BAR                                   PciBar[PCI_MAX_BAR];\r
\r
  //\r
  // The bridge device this pci device is subject to\r
  //\r
  PCI_IO_DEVICE                             *Parent;\r
\r
  //\r
  // A linked list for children Pci Device if it is bridge device\r
  //\r
  LIST_ENTRY                                ChildList;\r
\r
  //\r
  // TRUE if the PCI bus driver creates the handle for this PCI device\r
  //\r
  BOOLEAN                                   Registered;\r
\r
  //\r
  // TRUE if the PCI bus driver successfully allocates the resource required by\r
  // this PCI device\r
  //\r
  BOOLEAN                                   Allocated;\r
\r
  //\r
  // The attribute this PCI device currently set\r
  //\r
  UINT64                                    Attributes;\r
\r
  //\r
  // The attributes this PCI device actually supports\r
  //\r
  UINT64                                    Supports;\r
\r
  //\r
  // The resource decode the bridge supports\r
  //\r
  UINT32                                    Decodes;\r
\r
  //\r
  // TRUE if the ROM image is from the PCI Option ROM BAR\r
  //\r
  BOOLEAN                                   EmbeddedRom;\r
\r
  //\r
  // The OptionRom Size\r
  //\r
  UINT64                                    RomSize;\r
\r
  //\r
  // The OptionRom Size\r
  //\r
  UINT64                                    RomBase;\r
\r
  //\r
  // TRUE if all OpROM (in device or in platform specific position) have been processed\r
  //\r
  BOOLEAN                                   AllOpRomProcessed;\r
\r
  //\r
  // TRUE if there is any EFI driver in the OptionRom\r
  //\r
  BOOLEAN                                   BusOverride;\r
\r
  //\r
  // A list tracking reserved resource on a bridge device\r
  //\r
  LIST_ENTRY                                ReservedResourceList;\r
\r
  //\r
  // A list tracking image handle of platform specific overriding driver\r
  //\r
  LIST_ENTRY                                OptionRomDriverList;\r
\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;\r
  EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;\r
\r
  BOOLEAN                                   IsPciExp;\r
\r
  //\r
  // For SR-IOV\r
  //\r
  UINT8                                     PciExpressCapabilityOffset;\r
  UINT32                                    AriCapabilityOffset;\r
  UINT32                                    SrIovCapabilityOffset;\r
  UINT32                                    MrIovCapabilityOffset;\r
  PCI_BAR                                   VfPciBar[PCI_MAX_BAR];\r
  UINT32                                    SystemPageSize;\r
  UINT16                                    InitialVFs;\r
  UINT16                                    ReservedBusNum;\r
\r
  //\r
  // Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r
  // but some chipsets support non-standard I/O window alignments less than 4K.\r
  // This field is used to support this case.\r
  //\r
  UINT16                                    BridgeIoAlignment;\r
};\r
\r
#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_LINK(a) \\r
  CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
\r
\r
\r
//\r
// Global Variables\r
//\r
extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r
extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;\r
extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;\r
extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;\r
extern BOOLEAN                                      gFullEnumeration;\r
extern UINTN                                        gPciHostBridgeNumber;\r
extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
extern UINT64                                       gAllOne;\r
extern UINT64                                       gAllZero;\r
extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;\r
extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;\r
extern BOOLEAN                                      mReserveIsaAliases;\r
extern BOOLEAN                                      mReserveVgaAliases;\r
\r
/**\r
  Macro that checks whether device is a GFX device.\r
\r
  @param  _p      Specified device.\r
\r
  @retval TRUE    Device is a GFX device.\r
  @retval FALSE   Device is not a GFX device.\r
\r
**/\r
#define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
\r
/**\r
  Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
  than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
\r
  @param  This                Protocol instance pointer.\r
  @param  Controller          Handle of device to test.\r
  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
                              device to start.\r
\r
  @retval EFI_SUCCESS         This driver supports this device.\r
  @retval EFI_ALREADY_STARTED This driver is already running on this device.\r
  @retval other               This driver does not support this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingSupported (\r
  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
  IN EFI_HANDLE                     Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
  );\r
\r
/**\r
  Start this driver on ControllerHandle and enumerate Pci bus and start\r
  all device under PCI bus.\r
\r
  @param  This                 Protocol instance pointer.\r
  @param  Controller           Handle of device to bind driver to.\r
  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
                               device to start.\r
\r
  @retval EFI_SUCCESS          This driver is added to ControllerHandle.\r
  @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.\r
  @retval other                This driver does not support this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingStart (\r
  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
  IN EFI_HANDLE                     Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
  );\r
\r
/**\r
  Stop this driver on ControllerHandle. Support stopping any child handles\r
  created by this driver.\r
\r
  @param  This              Protocol instance pointer.\r
  @param  Controller        Handle of device to stop driver on.\r
  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
                            children is zero stop the entire bus driver.\r
  @param  ChildHandleBuffer List of Child Handles to Stop.\r
\r
  @retval EFI_SUCCESS       This driver is removed ControllerHandle.\r
  @retval other             This driver was not removed from this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingStop (\r
  IN  EFI_DRIVER_BINDING_PROTOCOL   *This,\r
  IN  EFI_HANDLE                    Controller,\r
  IN  UINTN                         NumberOfChildren,\r
  IN  EFI_HANDLE                    *ChildHandleBuffer\r
  );\r
\r
#endif\r
Commit	Line	Data
3cbfba02 DW	1	/*++\r
	2	\r
	3	Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
	4	\r\r
9dc8036d MK	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
9dc8036d MK	6	\r
3cbfba02 DW	7	\r\r
	8	\r
	9	**/\r
	10	\r
	11	\r
	12	#ifndef _EFI_PCI_BUS_H_\r
	13	#define _EFI_PCI_BUS_H_\r
	14	\r
	15	#include <PiDxe.h>\r
	16	\r
	17	#include <Protocol/LoadedImage.h>\r
	18	#include <Protocol/PciHostBridgeResourceAllocation.h>\r
	19	#include <Protocol/PciIo.h>\r
	20	#include <Protocol/LoadFile2.h>\r
	21	#include <Protocol/PciRootBridgeIo.h>\r
	22	#include <Protocol/PciHotPlugRequest.h>\r
	23	#include <Protocol/DevicePath.h>\r
	24	#include <Protocol/PciPlatform.h>\r
	25	#include <Protocol/PciHotPlugInit.h>\r
	26	#include <Protocol/Decompress.h>\r
	27	#include <Protocol/BusSpecificDriverOverride.h>\r
	28	#include <Protocol/IncompatiblePciDeviceSupport.h>\r
	29	#include <Protocol/PciOverride.h>\r
	30	#include <Protocol/PciEnumerationComplete.h>\r
	31	\r
	32	#include <Library/DebugLib.h>\r
	33	#include <Library/UefiDriverEntryPoint.h>\r
	34	#include <Library/BaseLib.h>\r
	35	#include <Library/UefiLib.h>\r
	36	#include <Library/BaseMemoryLib.h>\r
	37	#include <Library/ReportStatusCodeLib.h>\r
	38	#include <Library/MemoryAllocationLib.h>\r
	39	#include <Library/UefiBootServicesTableLib.h>\r
	40	#include <Library/DevicePathLib.h>\r
	41	#include <Library/PcdLib.h>\r
	42	#include <Library/PeCoffLib.h>\r
	43	\r
	44	#include <IndustryStandard/Pci.h>\r
	45	#include <IndustryStandard/PeImage.h>\r
	46	#include <IndustryStandard/Acpi.h>\r
	47	\r
	48	typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;\r
	49	typedef struct _PCI_BAR PCI_BAR;\r
	50	\r
	51	#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)\r
	52	#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)\r
	53	\r
	54	#define EFI_PCI_IOV_POLICY_ARI 0x0001\r
	55	#define EFI_PCI_IOV_POLICY_SRIOV 0x0002\r
	56	#define EFI_PCI_IOV_POLICY_MRIOV 0x0004\r
	57	\r
	58	typedef enum {\r
	59	PciBarTypeUnknown = 0,\r
	60	PciBarTypeIo16,\r
	61	PciBarTypeIo32,\r
	62	PciBarTypeMem32,\r
	63	PciBarTypePMem32,\r
	64	PciBarTypeMem64,\r
	65	PciBarTypePMem64,\r
	66	PciBarTypeIo,\r
	67	PciBarTypeMem,\r
	68	PciBarTypeMaxType\r
	69	} PCI_BAR_TYPE;\r
	70	\r
71	\r
72	#define VGABASE1 0x3B0\r
73	#define VGALIMIT1 0x3BB\r
74	\r
75	#define VGABASE2 0x3C0\r
76	#define VGALIMIT2 0x3DF\r
77	\r
78	#define ISABASE 0x100\r
79	#define ISALIMIT 0x3FF\r
80	\r
81	//\r
82	// PCI BAR parameters\r
83	//\r
84	struct _PCI_BAR {\r
85	UINT64 BaseAddress;\r
86	UINT64 Length;\r
87	UINT64 Alignment;\r
88	PCI_BAR_TYPE BarType;\r
89	BOOLEAN Prefetchable;\r
90	UINT8 MemType;\r
91	UINT16 Offset;\r
92	};\r
93	\r
94	//\r
95	// defined in PCI Card Specification, 8.0\r
96	//\r
97	#define PCI_CARD_MEMORY_BASE_0 0x1C\r
98	#define PCI_CARD_MEMORY_LIMIT_0 0x20\r
99	#define PCI_CARD_MEMORY_BASE_1 0x24\r
100	#define PCI_CARD_MEMORY_LIMIT_1 0x28\r
101	#define PCI_CARD_IO_BASE_0_LOWER 0x2C\r
102	#define PCI_CARD_IO_BASE_0_UPPER 0x2E\r
103	#define PCI_CARD_IO_LIMIT_0_LOWER 0x30\r
104	#define PCI_CARD_IO_LIMIT_0_UPPER 0x32\r
105	#define PCI_CARD_IO_BASE_1_LOWER 0x34\r
106	#define PCI_CARD_IO_BASE_1_UPPER 0x36\r
107	#define PCI_CARD_IO_LIMIT_1_LOWER 0x38\r
108	#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A\r
109	#define PCI_CARD_BRIDGE_CONTROL 0x3E\r
110	\r
111	#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
112	#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
113	\r
114	#define PPB_BAR_0 0\r
115	#define PPB_BAR_1 1\r
116	#define PPB_IO_RANGE 2\r
117	#define PPB_MEM32_RANGE 3\r
118	#define PPB_PMEM32_RANGE 4\r
119	#define PPB_PMEM64_RANGE 5\r
120	#define PPB_MEM64_RANGE 0xFF\r
121	\r
122	#define P2C_BAR_0 0\r
123	#define P2C_MEM_1 1\r
124	#define P2C_MEM_2 2\r
125	#define P2C_IO_1 3\r
126	#define P2C_IO_2 4\r
127	\r
128	#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
129	#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
130	#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
131	#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
132	#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
133	#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
134	#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
135	\r
136	#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
137	\r
138	//\r
139	// Define option for attribute\r
140	//\r
141	#define EFI_SET_SUPPORTS 0\r
142	#define EFI_SET_ATTRIBUTES 1\r
143	\r
144	#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')\r
145	\r
146	struct _PCI_IO_DEVICE {\r
147	UINT32 Signature;\r
148	EFI_HANDLE Handle;\r
149	EFI_PCI_IO_PROTOCOL PciIo;\r
150	LIST_ENTRY Link;\r
151	\r
152	EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
153	EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
154	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
155	EFI_LOAD_FILE2_PROTOCOL LoadFile2;\r
156	\r
157	//\r
158	// PCI configuration space header type\r
159	//\r
160	PCI_TYPE00 Pci;\r
161	\r
162	//\r
163	// Bus number, Device number, Function number\r
164	//\r
165	UINT8 BusNumber;\r
166	UINT8 DeviceNumber;\r
167	UINT8 FunctionNumber;\r
168	\r
169	//\r
170	// BAR for this PCI Device\r
171	//\r
172	PCI_BAR PciBar[PCI_MAX_BAR];\r
173	\r
174	//\r
175	// The bridge device this pci device is subject to\r
176	//\r
177	PCI_IO_DEVICE *Parent;\r
178	\r
179	//\r
180	// A linked list for children Pci Device if it is bridge device\r
181	//\r
182	LIST_ENTRY ChildList;\r
183	\r
184	//\r
2e182e30	185	// TRUE if the PCI bus driver creates the handle for this PCI device\r
3cbfba02 DW	186	//\r
	187	BOOLEAN Registered;\r
	188	\r
	189	//\r
	190	// TRUE if the PCI bus driver successfully allocates the resource required by\r
	191	// this PCI device\r
	192	//\r
	193	BOOLEAN Allocated;\r
	194	\r
	195	//\r
	196	// The attribute this PCI device currently set\r
	197	//\r
	198	UINT64 Attributes;\r
	199	\r
	200	//\r
	201	// The attributes this PCI device actually supports\r
	202	//\r
	203	UINT64 Supports;\r
	204	\r
	205	//\r
	206	// The resource decode the bridge supports\r
	207	//\r
	208	UINT32 Decodes;\r
	209	\r
	210	//\r
	211	// TRUE if the ROM image is from the PCI Option ROM BAR\r
	212	//\r
	213	BOOLEAN EmbeddedRom;\r
	214	\r
	215	//\r
	216	// The OptionRom Size\r
	217	//\r
	218	UINT64 RomSize;\r
	219	\r
	220	//\r
	221	// The OptionRom Size\r
	222	//\r
	223	UINT64 RomBase;\r
	224	\r
	225	//\r
	226	// TRUE if all OpROM (in device or in platform specific position) have been processed\r
	227	//\r
	228	BOOLEAN AllOpRomProcessed;\r
	229	\r
	230	//\r
	231	// TRUE if there is any EFI driver in the OptionRom\r
	232	//\r
	233	BOOLEAN BusOverride;\r
	234	\r
	235	//\r
	236	// A list tracking reserved resource on a bridge device\r
	237	//\r
	238	LIST_ENTRY ReservedResourceList;\r
	239	\r
	240	//\r
	241	// A list tracking image handle of platform specific overriding driver\r
	242	//\r
	243	LIST_ENTRY OptionRomDriverList;\r
	244	\r
	245	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
	246	EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
	247	\r
	248	BOOLEAN IsPciExp;\r
	249	\r
250	//\r
251	// For SR-IOV\r
252	//\r
253	UINT8 PciExpressCapabilityOffset;\r
254	UINT32 AriCapabilityOffset;\r
255	UINT32 SrIovCapabilityOffset;\r
256	UINT32 MrIovCapabilityOffset;\r
257	PCI_BAR VfPciBar[PCI_MAX_BAR];\r
258	UINT32 SystemPageSize;\r
259	UINT16 InitialVFs;\r
260	UINT16 ReservedBusNum;\r
261	\r
262	//\r
263	// Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r
2e182e30	264	// but some chipsets support non-standard I/O window alignments less than 4K.\r
3cbfba02 DW	265	// This field is used to support this case.\r
	266	//\r
	267	UINT16 BridgeIoAlignment;\r
	268	};\r
	269	\r
	270	#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
	271	CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
	272	\r
	273	#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
	274	CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
	275	\r
	276	#define PCI_IO_DEVICE_FROM_LINK(a) \\r
	277	CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
	278	\r
	279	#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
	280	CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
	281	\r
	282	\r
	283	\r
	284	//\r
	285	// Global Variables\r
	286	//\r
	287	extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r
	288	extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
	289	extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
	290	extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r
	291	extern BOOLEAN gFullEnumeration;\r
	292	extern UINTN gPciHostBridgeNumber;\r
	293	extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
	294	extern UINT64 gAllOne;\r
	295	extern UINT64 gAllZero;\r
	296	extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
	297	extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;\r
	298	extern BOOLEAN mReserveIsaAliases;\r
	299	extern BOOLEAN mReserveVgaAliases;\r
	300	\r
	301	/**\r
	302	Macro that checks whether device is a GFX device.\r
	303	\r
	304	@param _p Specified device.\r
	305	\r
2e182e30 GL	306	@retval TRUE Device is a GFX device.\r
2e182e30 GL	307	@retval FALSE Device is not a GFX device.\r
3cbfba02 DW	308	\r
	309	**/\r
	310	#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
	311	\r
	312	/**\r
	313	Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
	314	than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
	315	\r
	316	@param This Protocol instance pointer.\r
	317	@param Controller Handle of device to test.\r
2e182e30	318	@param RemainingDevicePath Optional parameter use to pick a specific child\r
3cbfba02 DW	319	device to start.\r
	320	\r
	321	@retval EFI_SUCCESS This driver supports this device.\r
	322	@retval EFI_ALREADY_STARTED This driver is already running on this device.\r
	323	@retval other This driver does not support this device.\r
	324	\r
	325	**/\r
	326	EFI_STATUS\r
	327	EFIAPI\r
	328	PciBusDriverBindingSupported (\r
	329	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	330	IN EFI_HANDLE Controller,\r
	331	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
	332	);\r
	333	\r
	334	/**\r
	335	Start this driver on ControllerHandle and enumerate Pci bus and start\r
	336	all device under PCI bus.\r
	337	\r
	338	@param This Protocol instance pointer.\r
	339	@param Controller Handle of device to bind driver to.\r
2e182e30	340	@param RemainingDevicePath Optional parameter use to pick a specific child\r
3cbfba02 DW	341	device to start.\r
	342	\r
	343	@retval EFI_SUCCESS This driver is added to ControllerHandle.\r
	344	@retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.\r
	345	@retval other This driver does not support this device.\r
	346	\r
	347	**/\r
	348	EFI_STATUS\r
	349	EFIAPI\r
	350	PciBusDriverBindingStart (\r
	351	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	352	IN EFI_HANDLE Controller,\r
	353	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
	354	);\r
	355	\r
	356	/**\r
2e182e30	357	Stop this driver on ControllerHandle. Support stopping any child handles\r
3cbfba02 DW	358	created by this driver.\r
	359	\r
	360	@param This Protocol instance pointer.\r
	361	@param Controller Handle of device to stop driver on.\r
	362	@param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of\r
	363	children is zero stop the entire bus driver.\r
	364	@param ChildHandleBuffer List of Child Handles to Stop.\r
	365	\r
	366	@retval EFI_SUCCESS This driver is removed ControllerHandle.\r
	367	@retval other This driver was not removed from this device.\r
	368	\r
	369	**/\r
	370	EFI_STATUS\r
	371	EFIAPI\r
	372	PciBusDriverBindingStop (\r
	373	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	374	IN EFI_HANDLE Controller,\r
	375	IN UINTN NumberOfChildren,\r
	376	IN EFI_HANDLE *ChildHandleBuffer\r
	377	);\r
	378	\r
	379	#endif\r