]>
Commit | Line | Data |
---|---|---|
3cbfba02 DW |
1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | Module Name:\r | |
15 | \r | |
16 | SlotConfig.c\r | |
17 | \r | |
18 | Abstract:\r | |
19 | \r | |
20 | Sets platform/SKU specific expansion slot information.\r | |
21 | \r | |
22 | \r | |
23 | \r | |
24 | \r | |
25 | --*/\r | |
26 | \r | |
27 | #include "PlatformDxe.h"\r | |
28 | #include <Protocol/SmbiosSlotPopulation.h>\r | |
29 | #include <IndustryStandard/Pci22.h>\r | |
30 | \r | |
31 | \r | |
32 | //\r | |
33 | // Default bus number for the bridge\r | |
34 | //\r | |
35 | #define DEF_BUS_CONFIG 0x0101\r | |
36 | #define DEF_BUS 0x01\r | |
37 | \r | |
38 | //\r | |
39 | // Data structures for slot information\r | |
40 | //\r | |
41 | typedef struct {\r | |
42 | UINT16 SmbiosSlotId;\r | |
43 | UINT8 Bus;\r | |
44 | UINT8 Dev;\r | |
45 | UINT8 Function;\r | |
46 | UINT8 TargetDevice;\r | |
47 | } EFI_PCI_SLOT_BRIDGE_INFO;\r | |
48 | \r | |
49 | //\r | |
50 | // Product specific bridge to slot routing information\r | |
51 | //\r | |
52 | EFI_PCI_SLOT_BRIDGE_INFO mSlotBridgeTable[] = {\r | |
53 | {\r | |
54 | 0x01, //PCIe x1 ICH (Bridge B0:D28:F1)\r | |
55 | DEFAULT_PCI_BUS_NUMBER_PCH,\r | |
56 | PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,\r | |
57 | PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2,\r | |
58 | 0\r | |
59 | }\r | |
60 | };\r | |
61 | \r | |
62 | UINTN mSlotBridgeTableSize =\r | |
63 | sizeof(mSlotBridgeTable) / sizeof(EFI_PCI_SLOT_BRIDGE_INFO);\r | |
64 | \r | |
65 | //\r | |
66 | // Slot entry table for IBX RVP\r | |
67 | //\r | |
68 | EFI_SMBIOS_SLOT_ENTRY mSlotEntries[] = {\r | |
69 | {0x06, FALSE, TRUE}, // PCIe x16 Slot 1 (NOT USED)\r | |
70 | {0x04, FALSE, TRUE}, // PCIe x16 Slot 2 (NOT USED)\r | |
71 | {0x03, FALSE, TRUE}, // PCIe x4 Slot (NOT USED)\r | |
72 | {0x02, FALSE, FALSE}, // Mini PCIe x1 Slot\r | |
73 | {0x15, FALSE, TRUE}, // PCIe x1 Slot 2 (NOT USED)\r | |
74 | {0x16, FALSE, TRUE}, // PCIe x1 Slot 3 (NOT USED)\r | |
75 | {0x07, FALSE, FALSE}, // PCI Slot 1\r | |
76 | {0x18, FALSE, TRUE}, // PCI Slot 2 (NOT USED)\r | |
77 | {0x17, FALSE, TRUE}, // PCI Slot 3 (NOT USED)\r | |
78 | };\r | |
79 | \r | |
80 | EFI_SMBIOS_SLOT_POPULATION_INFO mSlotInformation = {\r | |
81 | sizeof(mSlotEntries) / sizeof(EFI_SMBIOS_SLOT_ENTRY),\r | |
82 | mSlotEntries\r | |
83 | };\r | |
84 | \r | |
85 | \r |