projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /*++\r |
| 2 | \r | |
| 3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
| 4 | \r\r | |
| 9dc8036d MK |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 6 | \r | |
| 3cbfba02 DW |
7 | \r\r |
| 8 | \r | |
| 9 | Module Name:\r | |
| 10 | \r | |
| 11 | SlotConfig.c\r | |
| 12 | \r | |
| 13 | Abstract:\r | |
| 14 | \r | |
| 15 | Sets platform/SKU specific expansion slot information.\r | |
| 16 | \r | |
| 17 | \r | |
| 18 | \r | |
| 19 | \r | |
| 20 | --*/\r | |
| 21 | \r | |
| 22 | #include "PlatformDxe.h"\r | |
| 23 | #include <Protocol/SmbiosSlotPopulation.h>\r | |
| 24 | #include <IndustryStandard/Pci22.h>\r | |
| 25 | \r | |
| 26 | \r | |
| 27 | //\r | |
| 28 | // Default bus number for the bridge\r | |
| 29 | //\r | |
| 30 | #define DEF_BUS_CONFIG 0x0101\r | |
| 31 | #define DEF_BUS 0x01\r | |
| 32 | \r | |
| 33 | //\r | |
| 34 | // Data structures for slot information\r | |
| 35 | //\r | |
| 36 | typedef struct {\r | |
| 37 | UINT16 SmbiosSlotId;\r | |
| 38 | UINT8 Bus;\r | |
| 39 | UINT8 Dev;\r | |
| 40 | UINT8 Function;\r | |
| 41 | UINT8 TargetDevice;\r | |
| 42 | } EFI_PCI_SLOT_BRIDGE_INFO;\r | |
| 43 | \r | |
| 44 | //\r | |
| 45 | // Product specific bridge to slot routing information\r | |
| 46 | //\r | |
| 47 | EFI_PCI_SLOT_BRIDGE_INFO mSlotBridgeTable[] = {\r | |
| 48 | {\r | |
| 49 | 0x01, //PCIe x1 ICH (Bridge B0:D28:F1)\r | |
| 50 | DEFAULT_PCI_BUS_NUMBER_PCH,\r | |
| 51 | PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,\r | |
| 52 | PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2,\r | |
| 53 | 0\r | |
| 54 | }\r | |
| 55 | };\r | |
| 56 | \r | |
| 57 | UINTN mSlotBridgeTableSize =\r | |
| 58 | sizeof(mSlotBridgeTable) / sizeof(EFI_PCI_SLOT_BRIDGE_INFO);\r | |
| 59 | \r | |
| 60 | //\r | |
| 61 | // Slot entry table for IBX RVP\r | |
| 62 | //\r | |
| 63 | EFI_SMBIOS_SLOT_ENTRY mSlotEntries[] = {\r | |
| 64 | {0x06, FALSE, TRUE}, // PCIe x16 Slot 1 (NOT USED)\r | |
| 65 | {0x04, FALSE, TRUE}, // PCIe x16 Slot 2 (NOT USED)\r | |
| 66 | {0x03, FALSE, TRUE}, // PCIe x4 Slot (NOT USED)\r | |
| 67 | {0x02, FALSE, FALSE}, // Mini PCIe x1 Slot\r | |
| 68 | {0x15, FALSE, TRUE}, // PCIe x1 Slot 2 (NOT USED)\r | |
| 69 | {0x16, FALSE, TRUE}, // PCIe x1 Slot 3 (NOT USED)\r | |
| 70 | {0x07, FALSE, FALSE}, // PCI Slot 1\r | |
| 71 | {0x18, FALSE, TRUE}, // PCI Slot 2 (NOT USED)\r | |
| 72 | {0x17, FALSE, TRUE}, // PCI Slot 3 (NOT USED)\r | |
| 73 | };\r | |
| 74 | \r | |
| 75 | EFI_SMBIOS_SLOT_POPULATION_INFO mSlotInformation = {\r | |
| 76 | sizeof(mSlotEntries) / sizeof(EFI_SMBIOS_SLOT_ENTRY),\r | |
| 77 | mSlotEntries\r | |
| 78 | };\r | |
| 79 | \r | |
| 80 | \r |