[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformInitPei / MemoryCallback.c

/** @file\r
\r
  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
                                                                                   \r\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
                                                                                   \r\r
\r
Module Name:\r
\r
  MemoryCallback.c\r
\r
Abstract:\r
\r
  EFI 2.0 PEIM to provide the platform support functionality on the Bridgeport.\r
\r
--*/\r
\r
#include "PlatformEarlyInit.h"\r
\r
\r
VOID\r
UpdateDefaultSetupValue (\r
  IN  EFI_PLATFORM_INFO_HOB       *PlatformInfo\r
  )\r
{\r
return;\r
}\r
\r
/**\r
  PEI termination callback.\r
\r
  @param PeiServices         General purpose services available to every PEIM.\r
  @param NotifyDescriptor    Not uesed.\r
  @param Ppi                 Not uesed.\r
\r
  @retval EFI_SUCCESS        If the interface could be successfully\r
                             installed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI    \r
EndOfPeiPpiNotifyCallback (\r
  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
  IN VOID                       *Ppi\r
  )\r
{\r
  EFI_STATUS                  Status;\r
  UINT64                      LowUncableBase;\r
  EFI_PLATFORM_INFO_HOB       *PlatformInfo;\r
  UINT32                      HecBaseHigh;\r
  EFI_BOOT_MODE               BootMode;\r
  EFI_PEI_HOB_POINTERS        Hob;\r
\r
  Status = (*PeiServices)->GetBootMode(\r
                             PeiServices,\r
                             &BootMode\r
                             );\r
\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Set the some PCI and chipset range as UC\r
  // And align to 1M at leaset\r
  //\r
  Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
  ASSERT (Hob.Raw != NULL);\r
  PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
\r
  UpdateDefaultSetupValue (PlatformInfo);\r
\r
  DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", PlatformInfo->MemData.MemTolm));\r
  DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo->PciData.PciExpressBase));\r
  DEBUG (\r
    (EFI_D_ERROR,\r
    "PCIE   BASE: %lX     Size : %X\n",\r
    PlatformInfo->PciData.PciExpressBase,\r
    PlatformInfo->PciData.PciExpressSize)\r
    );\r
  DEBUG (\r
    (EFI_D_ERROR,\r
    "PCI32  BASE: %X     Limit: %X\n",\r
    PlatformInfo->PciData.PciResourceMem32Base,\r
    PlatformInfo->PciData.PciResourceMem32Limit)\r
    );\r
  DEBUG (\r
    (EFI_D_ERROR,\r
    "PCI64  BASE: %lX     Limit: %lX\n",\r
    PlatformInfo->PciData.PciResourceMem64Base,\r
    PlatformInfo->PciData.PciResourceMem64Limit)\r
    );\r
  DEBUG ((EFI_D_ERROR, "UC    START: %lX     End  : %lX\n", PlatformInfo->MemData.MemMir0, PlatformInfo->MemData.MemMir1));\r
\r
  LowUncableBase = PlatformInfo->MemData.MemMaxTolm;\r
  LowUncableBase &= (0x0FFF00000);\r
\r
  if (BootMode != BOOT_ON_S3_RESUME) {\r
    //\r
    // In BIOS, HECBASE will be always below 4GB\r
    //\r
    HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo->PciData.PciExpressBase, 28);\r
    ASSERT (HecBaseHigh < 16);\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Install Firmware Volume Hob's once there is main memory\r
\r
  @param PeiServices       General purpose services available to every PEIM.\r
  @param NotifyDescriptor  Notify that this module published.\r
  @param Ppi               PPI that was installed.\r
\r
  @retval EFI_SUCCESS     The function completed successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
MemoryDiscoveredPpiNotifyCallback (\r
  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
  IN VOID                       *Ppi\r
  )\r
{\r
  EFI_STATUS                  Status;\r
  EFI_BOOT_MODE               BootMode;\r
  EFI_CPUID_REGISTER          FeatureInfo;\r
  UINT8                       CpuAddressWidth;\r
  UINT16                      Pm1Cnt;\r
  EFI_PEI_HOB_POINTERS        Hob;\r
  EFI_PLATFORM_INFO_HOB       *PlatformInfo;\r
  UINT32                      RootComplexBar;\r
  UINT32                      PmcBase;\r
  UINT32                      IoBase;\r
  UINT32                      IlbBase;\r
  UINT32                      SpiBase;\r
  UINT32                      MphyBase;\r
\r
  //\r
  // Get Platform Info HOB\r
  //\r
  Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
  ASSERT (Hob.Raw != NULL);\r
  PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
\r
  Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);\r
\r
  //\r
  // Check if user wants to turn off in PEI phase\r
  //\r
  if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode != BOOT_ON_FLASH_UPDATE)) {\r
    CheckPowerOffNow();\r
  } else {\r
    Pm1Cnt  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);\r
    Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;\r
    IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r
  }\r
\r
  #ifndef MINNOW2_FSP_BUILD\r
  //\r
  // Set PEI cache mode here\r
  //\r
  SetPeiCacheMode (PeiServices);\r
  #endif\r
\r
  //\r
  //  Pulish memory tyoe info\r
  //\r
  PublishMemoryTypeInfo ();\r
\r
  //\r
  // Work done if on a S3 resume\r
  //\r
  if (BootMode == BOOT_ON_S3_RESUME) {\r
    //\r
    //Program the side band packet register to send a sideband message to Punit\r
    //To indicate that DRAM has been initialized and PUNIT FW base address in memory.\r
    //\r
    return EFI_SUCCESS;\r
  }\r
\r
  RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) & B_PCH_LPC_RCBA_BAR;\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    RootComplexBar,\r
    0x1000\r
    );\r
  DEBUG ((EFI_D_INFO, "RootComplexBar     : 0x%x\n", RootComplexBar));\r
\r
  PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) & B_PCH_LPC_PMC_BASE_BAR;\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    PmcBase,\r
    0x1000\r
    );\r
  DEBUG ((EFI_D_INFO, "PmcBase            : 0x%x\n", PmcBase));\r
\r
  IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR;\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    IoBase,\r
    0x4000\r
    );\r
  DEBUG ((EFI_D_INFO, "IoBase             : 0x%x\n", IoBase));\r
\r
  IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) & B_PCH_LPC_ILB_BASE_BAR;\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    IlbBase,\r
    0x1000\r
    );\r
  DEBUG ((EFI_D_INFO, "IlbBase            : 0x%x\n", IlbBase));\r
\r
  SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) & B_PCH_LPC_SPI_BASE_BAR;\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    SpiBase,\r
    0x1000\r
    );\r
  DEBUG ((EFI_D_INFO, "SpiBase            : 0x%x\n", SpiBase));\r
\r
  MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) & B_PCH_LPC_MPHY_BASE_BAR;\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    MphyBase,\r
    0x100000\r
    );\r
  DEBUG ((EFI_D_INFO, "MphyBase           : 0x%x\n", MphyBase));\r
\r
  //\r
  // Local APIC\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    LOCAL_APIC_ADDRESS,\r
    0x1000\r
  );\r
  DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS));\r
\r
  //\r
  // IO APIC\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    IO_APIC_ADDRESS,\r
    0x1000\r
  );\r
  DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS    : 0x%x\n", IO_APIC_ADDRESS));\r
\r
  //\r
  // Adding the PCIE Express area to the E820 memory table as type 2 memory.\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    PlatformInfo->PciData.PciExpressBase,\r
    PlatformInfo->PciData.PciExpressSize\r
    );\r
  DEBUG ((EFI_D_INFO, "PciExpressBase     : 0x%x\n", PlatformInfo->PciData.PciExpressBase));\r
\r
  //\r
  // Adding the Flashpart to the E820 memory table as type 2 memory.\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_FIRMWARE_DEVICE,\r
    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
    FixedPcdGet32 (PcdFlashAreaBaseAddress),\r
    FixedPcdGet32 (PcdFlashAreaSize)\r
    );\r
  DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress)));\r
\r
  //\r
  // Create a CPU hand-off information\r
  //\r
  CpuAddressWidth = 32;\r
  AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);\r
  if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) {\r
    AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);\r
    CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);\r
  }\r
\r
  BuildCpuHob(CpuAddressWidth, 16);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return Status;\r
\r
}\r
\r
\r
EFI_STATUS\r
ValidateFvHeader (\r
  IN EFI_FIRMWARE_VOLUME_HEADER            *FwVolHeader\r
  )\r
{\r
  UINT16  *Ptr;\r
  UINT16  HeaderLength;\r
  UINT16  Checksum;\r
\r
  //\r
  // Verify the header revision, header signature, length\r
  // Length of FvBlock cannot be 2**64-1\r
  // HeaderLength cannot be an odd number\r
  //\r
  if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||\r
      (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||\r
      (FwVolHeader->FvLength == ((UINT64) -1)) ||\r
      ((FwVolHeader->HeaderLength & 0x01) != 0)\r
      ) {\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  //\r
  // Verify the header checksum\r
  //\r
  HeaderLength  = (UINT16) (FwVolHeader->HeaderLength / 2);\r
  Ptr           = (UINT16 *) FwVolHeader;\r
  Checksum      = 0;\r
  while (HeaderLength > 0) {\r
    Checksum = *Ptr++;\r
    HeaderLength--;\r
  }\r
\r
  if (Checksum != 0) {\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
Commit	Line	Data
3cbfba02 DW	1	/** @file\r
	2	\r
	3	Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
	4	\r\r
9dc8036d MK	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
9dc8036d MK	6	\r
3cbfba02 DW	7	\r\r
	8	\r
	9	Module Name:\r
	10	\r
	11	MemoryCallback.c\r
	12	\r
	13	Abstract:\r
	14	\r
	15	EFI 2.0 PEIM to provide the platform support functionality on the Bridgeport.\r
	16	\r
	17	--*/\r
	18	\r
	19	#include "PlatformEarlyInit.h"\r
	20	\r
	21	\r
	22	VOID\r
	23	UpdateDefaultSetupValue (\r
	24	IN EFI_PLATFORM_INFO_HOB *PlatformInfo\r
	25	)\r
	26	{\r
	27	return;\r
	28	}\r
	29	\r
	30	/**\r
	31	PEI termination callback.\r
	32	\r
	33	@param PeiServices General purpose services available to every PEIM.\r
	34	@param NotifyDescriptor Not uesed.\r
	35	@param Ppi Not uesed.\r
	36	\r
	37	@retval EFI_SUCCESS If the interface could be successfully\r
	38	installed.\r
	39	\r
	40	**/\r
	41	EFI_STATUS\r
	42	EFIAPI \r
	43	EndOfPeiPpiNotifyCallback (\r
	44	IN CONST EFI_PEI_SERVICES **PeiServices,\r
	45	IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
	46	IN VOID *Ppi\r
	47	)\r
	48	{\r
	49	EFI_STATUS Status;\r
3cbfba02 DW	50	UINT64 LowUncableBase;\r
	51	EFI_PLATFORM_INFO_HOB *PlatformInfo;\r
	52	UINT32 HecBaseHigh;\r
	53	EFI_BOOT_MODE BootMode;\r
	54	EFI_PEI_HOB_POINTERS Hob;\r
	55	\r
	56	Status = (*PeiServices)->GetBootMode(\r
	57	PeiServices,\r
	58	&BootMode\r
	59	);\r
	60	\r
	61	ASSERT_EFI_ERROR (Status);\r
	62	\r
	63	//\r
	64	// Set the some PCI and chipset range as UC\r
	65	// And align to 1M at leaset\r
	66	//\r
	67	Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
	68	ASSERT (Hob.Raw != NULL);\r
	69	PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
	70	\r
	71	UpdateDefaultSetupValue (PlatformInfo);\r
	72	\r
	73	DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", PlatformInfo->MemData.MemTolm));\r
	74	DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo->PciData.PciExpressBase));\r
	75	DEBUG (\r
	76	(EFI_D_ERROR,\r
	77	"PCIE BASE: %lX Size : %X\n",\r
	78	PlatformInfo->PciData.PciExpressBase,\r
	79	PlatformInfo->PciData.PciExpressSize)\r
	80	);\r
	81	DEBUG (\r
	82	(EFI_D_ERROR,\r
	83	"PCI32 BASE: %X Limit: %X\n",\r
	84	PlatformInfo->PciData.PciResourceMem32Base,\r
	85	PlatformInfo->PciData.PciResourceMem32Limit)\r
	86	);\r
	87	DEBUG (\r
	88	(EFI_D_ERROR,\r
	89	"PCI64 BASE: %lX Limit: %lX\n",\r
	90	PlatformInfo->PciData.PciResourceMem64Base,\r
	91	PlatformInfo->PciData.PciResourceMem64Limit)\r
	92	);\r
	93	DEBUG ((EFI_D_ERROR, "UC START: %lX End : %lX\n", PlatformInfo->MemData.MemMir0, PlatformInfo->MemData.MemMir1));\r
	94	\r
	95	LowUncableBase = PlatformInfo->MemData.MemMaxTolm;\r
	96	LowUncableBase &= (0x0FFF00000);\r
3cbfba02 DW	97	\r
	98	if (BootMode != BOOT_ON_S3_RESUME) {\r
	99	//\r
	100	// In BIOS, HECBASE will be always below 4GB\r
	101	//\r
	102	HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo->PciData.PciExpressBase, 28);\r
	103	ASSERT (HecBaseHigh < 16);\r
	104	}\r
	105	\r
	106	return Status;\r
	107	}\r
	108	\r
	109	/**\r
	110	Install Firmware Volume Hob's once there is main memory\r
	111	\r
	112	@param PeiServices General purpose services available to every PEIM.\r
	113	@param NotifyDescriptor Notify that this module published.\r
	114	@param Ppi PPI that was installed.\r
	115	\r
	116	@retval EFI_SUCCESS The function completed successfully.\r
	117	\r
	118	**/\r
	119	EFI_STATUS\r
	120	EFIAPI\r
	121	MemoryDiscoveredPpiNotifyCallback (\r
	122	IN CONST EFI_PEI_SERVICES **PeiServices,\r
	123	IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
	124	IN VOID *Ppi\r
	125	)\r
	126	{\r
	127	EFI_STATUS Status;\r
	128	EFI_BOOT_MODE BootMode;\r
	129	EFI_CPUID_REGISTER FeatureInfo;\r
	130	UINT8 CpuAddressWidth;\r
	131	UINT16 Pm1Cnt;\r
	132	EFI_PEI_HOB_POINTERS Hob;\r
	133	EFI_PLATFORM_INFO_HOB *PlatformInfo;\r
	134	UINT32 RootComplexBar;\r
	135	UINT32 PmcBase;\r
	136	UINT32 IoBase;\r
	137	UINT32 IlbBase;\r
	138	UINT32 SpiBase;\r
	139	UINT32 MphyBase;\r
	140	\r
	141	//\r
	142	// Get Platform Info HOB\r
	143	//\r
	144	Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
	145	ASSERT (Hob.Raw != NULL);\r
	146	PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
	147	\r
	148	Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);\r
	149	\r
	150	//\r
	151	// Check if user wants to turn off in PEI phase\r
	152	//\r
	153	if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode != BOOT_ON_FLASH_UPDATE)) {\r
	154	CheckPowerOffNow();\r
	155	} else {\r
	156	Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);\r
	157	Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;\r
	158	IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r
	159	}\r
	160	\r
161	#ifndef MINNOW2_FSP_BUILD\r
162	//\r
163	// Set PEI cache mode here\r
164	//\r
165	SetPeiCacheMode (PeiServices);\r
166	#endif\r
167	\r
168	//\r
169	// Pulish memory tyoe info\r
170	//\r
171	PublishMemoryTypeInfo ();\r
172	\r
173	//\r
174	// Work done if on a S3 resume\r
175	//\r
176	if (BootMode == BOOT_ON_S3_RESUME) {\r
177	//\r
178	//Program the side band packet register to send a sideband message to Punit\r
179	//To indicate that DRAM has been initialized and PUNIT FW base address in memory.\r
180	//\r
181	return EFI_SUCCESS;\r
182	}\r
183	\r
184	RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) & B_PCH_LPC_RCBA_BAR;\r
185	BuildResourceDescriptorHob (\r
186	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
187	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
188	RootComplexBar,\r
189	0x1000\r
190	);\r
191	DEBUG ((EFI_D_INFO, "RootComplexBar : 0x%x\n", RootComplexBar));\r
192	\r
193	PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) & B_PCH_LPC_PMC_BASE_BAR;\r
194	BuildResourceDescriptorHob (\r
195	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
196	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
197	PmcBase,\r
198	0x1000\r
199	);\r
200	DEBUG ((EFI_D_INFO, "PmcBase : 0x%x\n", PmcBase));\r
201	\r
202	IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR;\r
203	BuildResourceDescriptorHob (\r
204	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
205	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
206	IoBase,\r
207	0x4000\r
208	);\r
209	DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase));\r
210	\r
211	IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) & B_PCH_LPC_ILB_BASE_BAR;\r
212	BuildResourceDescriptorHob (\r
213	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
214	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
215	IlbBase,\r
216	0x1000\r
217	);\r
218	DEBUG ((EFI_D_INFO, "IlbBase : 0x%x\n", IlbBase));\r
219	\r
220	SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) & B_PCH_LPC_SPI_BASE_BAR;\r
221	BuildResourceDescriptorHob (\r
222	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
223	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
224	SpiBase,\r
225	0x1000\r
226	);\r
227	DEBUG ((EFI_D_INFO, "SpiBase : 0x%x\n", SpiBase));\r
228	\r
229	MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) & B_PCH_LPC_MPHY_BASE_BAR;\r
230	BuildResourceDescriptorHob (\r
231	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
232	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
233	MphyBase,\r
234	0x100000\r
235	);\r
236	DEBUG ((EFI_D_INFO, "MphyBase : 0x%x\n", MphyBase));\r
237	\r
238	//\r
239	// Local APIC\r
240	//\r
241	BuildResourceDescriptorHob (\r
242	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
243	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
244	LOCAL_APIC_ADDRESS,\r
245	0x1000\r
246	);\r
247	DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS));\r
248	\r
249	//\r
250	// IO APIC\r
251	//\r
252	BuildResourceDescriptorHob (\r
253	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
254	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
255	IO_APIC_ADDRESS,\r
256	0x1000\r
257	);\r
258	DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS : 0x%x\n", IO_APIC_ADDRESS));\r
259	\r
260	//\r
261	// Adding the PCIE Express area to the E820 memory table as type 2 memory.\r
262	//\r
263	BuildResourceDescriptorHob (\r
264	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
265	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
266	PlatformInfo->PciData.PciExpressBase,\r
267	PlatformInfo->PciData.PciExpressSize\r
268	);\r
269	DEBUG ((EFI_D_INFO, "PciExpressBase : 0x%x\n", PlatformInfo->PciData.PciExpressBase));\r
270	\r
271	//\r
272	// Adding the Flashpart to the E820 memory table as type 2 memory.\r
273	//\r
274	BuildResourceDescriptorHob (\r
275	EFI_RESOURCE_FIRMWARE_DEVICE,\r
276	(EFI_RESOURCE_ATTRIBUTE_PRESENT \| EFI_RESOURCE_ATTRIBUTE_INITIALIZED \| EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
277	FixedPcdGet32 (PcdFlashAreaBaseAddress),\r
278	FixedPcdGet32 (PcdFlashAreaSize)\r
279	);\r
280	DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress)));\r
281	\r
282	//\r
283	// Create a CPU hand-off information\r
284	//\r
285	CpuAddressWidth = 32;\r
286	AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);\r
287	if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) {\r
288	AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);\r
289	CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);\r
290	}\r
291	\r
292	BuildCpuHob(CpuAddressWidth, 16);\r
293	ASSERT_EFI_ERROR (Status);\r
294	\r
295	return Status;\r
296	\r
297	}\r
298	\r
299	\r
300	EFI_STATUS\r
301	ValidateFvHeader (\r
302	IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader\r
303	)\r
304	{\r
305	UINT16 *Ptr;\r
306	UINT16 HeaderLength;\r
307	UINT16 Checksum;\r
308	\r
309	//\r
310	// Verify the header revision, header signature, length\r
311	// Length of FvBlock cannot be 2**64-1\r
312	// HeaderLength cannot be an odd number\r
313	//\r
314	if ((FwVolHeader->Revision != EFI_FVH_REVISION) \|\|\r
315	(FwVolHeader->Signature != EFI_FVH_SIGNATURE) \|\|\r
316	(FwVolHeader->FvLength == ((UINT64) -1)) \|\|\r
317	((FwVolHeader->HeaderLength & 0x01) != 0)\r
318	) {\r
319	return EFI_NOT_FOUND;\r
320	}\r
321	\r
322	//\r
323	// Verify the header checksum\r
324	//\r
325	HeaderLength = (UINT16) (FwVolHeader->HeaderLength / 2);\r
326	Ptr = (UINT16 *) FwVolHeader;\r
327	Checksum = 0;\r
328	while (HeaderLength > 0) {\r
329	Checksum = *Ptr++;\r
330	HeaderLength--;\r
331	}\r
332	\r
333	if (Checksum != 0) {\r
334	return EFI_NOT_FOUND;\r
335	}\r
336	\r
337	return EFI_SUCCESS;\r
338	}\r