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1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | \r | |
15 | Module Name:\r | |
16 | \r | |
17 | IchS3Save.c\r | |
18 | \r | |
19 | Abstract:\r | |
20 | \r | |
21 | SMM S3 handler Driver implementation file\r | |
22 | \r | |
23 | Revision History\r | |
24 | \r | |
25 | **/\r | |
26 | #include "SmmPlatform.h"\r | |
27 | \r | |
28 | extern UINT16 mAcpiBaseAddr;\r | |
29 | EFI_PHYSICAL_ADDRESS mRuntimeScriptTableBase;\r | |
30 | \r | |
31 | EFI_STATUS\r | |
32 | InitRuntimeScriptTable (\r | |
33 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
34 | )\r | |
35 | {\r | |
36 | EFI_STATUS Status;\r | |
37 | UINT32 VarAttrib;\r | |
38 | UINTN VarSize;\r | |
39 | ACPI_VARIABLE_SET_COMPATIBILITY *AcpiVariableBase;\r | |
40 | \r | |
41 | //\r | |
42 | // Allocate runtime ACPI script table space. We need it to save some\r | |
43 | // settings done by CSM, which runs after normal script table closed\r | |
44 | //\r | |
45 | Status = gBS->AllocatePages (\r | |
46 | AllocateAnyPages,\r | |
47 | EfiACPIReclaimMemory,\r | |
48 | 1,\r | |
49 | &mRuntimeScriptTableBase\r | |
50 | );\r | |
51 | if (EFI_ERROR(Status)) {\r | |
52 | return EFI_OUT_OF_RESOURCES ;\r | |
53 | }\r | |
54 | \r | |
55 | //\r | |
56 | // Save runtime script table base into global ACPI variable\r | |
57 | //\r | |
58 | VarAttrib = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS\r | |
59 | | EFI_VARIABLE_NON_VOLATILE;\r | |
60 | VarSize = sizeof (UINTN);\r | |
61 | Status = SystemTable->RuntimeServices->GetVariable (\r | |
62 | ACPI_GLOBAL_VARIABLE,\r | |
63 | &gEfiAcpiVariableCompatiblityGuid,\r | |
64 | &VarAttrib,\r | |
65 | &VarSize,\r | |
66 | &AcpiVariableBase\r | |
67 | );\r | |
68 | if (EFI_ERROR(Status)) {\r | |
69 | return Status;\r | |
70 | }\r | |
71 | \r | |
72 | AcpiVariableBase->RuntimeScriptTableBase = mRuntimeScriptTableBase;\r | |
73 | \r | |
74 | return EFI_SUCCESS;\r | |
75 | }\r | |
76 | \r | |
77 | EFI_STATUS\r | |
78 | SaveRuntimeScriptTable (\r | |
79 | VOID\r | |
80 | )\r | |
81 | {\r | |
82 | SMM_PCI_IO_ADDRESS PciAddress;\r | |
83 | UINT32 Data32;\r | |
84 | UINT16 Data16;\r | |
85 | UINT8 Data8;\r | |
86 | UINT8 Mask;\r | |
87 | UINTN Index;\r | |
88 | UINTN Offset;\r | |
89 | UINT8 RegTable[] = {\r | |
90 | \r | |
91 | //\r | |
92 | //Bus , Dev, Func, DMI\r | |
93 | //\r | |
94 | 0x00 , 0x00, 0x00,\r | |
95 | \r | |
96 | //\r | |
97 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
98 | //\r | |
99 | 0x00 , 0x08, 0x00, 0x00, 0x30, 0x00, 0x00, 0xa0,\r | |
100 | \r | |
101 | //\r | |
102 | //Bus , Dev, Func, LPC device\r | |
103 | //\r | |
104 | 0x00 , 0x1F, 0x00,\r | |
105 | \r | |
106 | //\r | |
107 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
108 | //\r | |
109 | 0x00 , 0x08, 0x00, 0x07, 0x00, 0x00, 0x90, 0x00,\r | |
110 | \r | |
111 | //\r | |
112 | //Bus , Dev, Func, PCIE device\r | |
113 | //\r | |
114 | 0x00 , 0x1C, 0x00,\r | |
115 | \r | |
116 | //\r | |
117 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
118 | //\r | |
119 | 0xC0 , 0x83, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,\r | |
120 | \r | |
121 | //\r | |
122 | //Bus , Dev, Func, PCIE device\r | |
123 | //\r | |
124 | 0x00 , 0x1C, 0x00,\r | |
125 | \r | |
126 | //\r | |
127 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
128 | //\r | |
129 | 0x03 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r | |
130 | \r | |
131 | //\r | |
132 | //Bus , Dev, Func, SATA device\r | |
133 | //\r | |
134 | 0x00 , 0x13, 0x00,\r | |
135 | \r | |
136 | //\r | |
137 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
138 | //\r | |
139 | 0xf4 , 0xab, 0x27, 0x10, 0xf1, 0x1d, 0x00, 0x40,\r | |
140 | \r | |
141 | //\r | |
142 | //Bus , Dev, Func, EHCI device\r | |
143 | //\r | |
144 | 0x00 , 0x1D, 0x00,\r | |
145 | \r | |
146 | //\r | |
147 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
148 | //\r | |
149 | 0x10 , 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,\r | |
150 | \r | |
151 | //\r | |
152 | //Bus , Dev, Func, SMBUS device\r | |
153 | //\r | |
154 | 0x00 , 0x1f, 0x03,\r | |
155 | \r | |
156 | //\r | |
157 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
158 | //\r | |
159 | 0x10 , 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r | |
160 | \r | |
161 | //\r | |
162 | //Bus , Dev, Func, SMBUS device\r | |
163 | //\r | |
164 | 0x00 , 0x1f, 0x03,\r | |
165 | \r | |
166 | //\r | |
167 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
168 | //\r | |
169 | 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r | |
170 | \r | |
171 | //\r | |
172 | //Bus , Dev, Func, VGA bus1\r | |
173 | //\r | |
174 | 0x01 , 0x00, 0x00,\r | |
175 | \r | |
176 | //\r | |
177 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
178 | //\r | |
179 | 0x58 , 0x81, 0x18, 0x01, 0xb0, 0x00, 0x00, 0x00,\r | |
180 | \r | |
181 | //\r | |
182 | //Bus , Dev, Func, VGA bus1\r | |
183 | //\r | |
184 | 0x01 , 0x00, 0x00,\r | |
185 | \r | |
186 | //\r | |
187 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
188 | //\r | |
189 | 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r | |
190 | \r | |
191 | //\r | |
192 | //Bus , Dev, Func, VGA bus1 function 1\r | |
193 | //\r | |
194 | 0x01 , 0x00, 0x01,\r | |
195 | \r | |
196 | //\r | |
197 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
198 | //\r | |
199 | 0x51 , 0x80, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00,\r | |
200 | \r | |
201 | //\r | |
202 | //Bus , Dev, Func, VGA bus1 function 1\r | |
203 | //\r | |
204 | 0x01 , 0x00, 0x01,\r | |
205 | \r | |
206 | //\r | |
207 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
208 | //\r | |
209 | 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r | |
210 | \r | |
211 | //\r | |
212 | //Bus , Dev, Func, IGD bus0 function 0\r | |
213 | //\r | |
214 | 0x00 , 0x02, 0x00,\r | |
215 | \r | |
216 | //\r | |
217 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
218 | //\r | |
219 | 0x42 , 0x81, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,\r | |
220 | \r | |
221 | //\r | |
222 | //Bus , Dev, Func, USB bus0 function 0\r | |
223 | //\r | |
224 | 0x00 , 0x16, 0x00,\r | |
225 | \r | |
226 | //\r | |
227 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
228 | //\r | |
229 | 0x32 , 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r | |
230 | \r | |
231 | //\r | |
232 | //Bus , Dev, Func, HD Audio bus0 function 0\r | |
233 | //\r | |
234 | 0x00 , 0x1B, 0x00,\r | |
235 | \r | |
236 | //\r | |
237 | //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r | |
238 | //\r | |
239 | 0x00 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,\r | |
240 | \r | |
241 | //\r | |
242 | //0xFF indicates the end of the table\r | |
243 | //\r | |
244 | 0xFF\r | |
245 | };\r | |
246 | \r | |
247 | //\r | |
248 | // These registers have to set in byte order\r | |
249 | //\r | |
250 | UINT8 ExtReg[] = { 0x9E, 0x9D }; // SMRAM settings\r | |
251 | \r | |
252 | \r | |
253 | \r | |
254 | //\r | |
255 | // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM\r | |
256 | // and vital to S3 resume. That's why we put save code here\r | |
257 | //\r | |
258 | PciAddress.Bus = 0;\r | |
259 | PciAddress.Device = 0;\r | |
260 | PciAddress.Function = 0;\r | |
261 | PciAddress.ExtendedRegister = 0;\r | |
262 | \r | |
263 | for (Index = 0; Index < 2; Index++) {\r | |
264 | //\r | |
265 | // Read SRAM setting from Pci(0, 0, 0)\r | |
266 | //\r | |
267 | PciAddress.Register = ExtReg[Index];\r | |
268 | Data8 = MmioRead8 (\r | |
269 | MmPciAddress (0,\r | |
270 | PciAddress.Bus,\r | |
271 | PciAddress.Device,\r | |
272 | PciAddress.Function,\r | |
273 | PciAddress.Register\r | |
274 | )\r | |
275 | );\r | |
276 | \r | |
277 | //\r | |
278 | // Save latest settings to runtime script table\r | |
279 | //\r | |
280 | S3BootScriptSavePciCfgWrite(\r | |
281 | S3BootScriptWidthUint8,\r | |
282 | *(UINT64*)&PciAddress,\r | |
283 | 1,\r | |
284 | &Data8\r | |
285 | );\r | |
286 | }\r | |
287 | \r | |
288 | \r | |
289 | //\r | |
290 | // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM\r | |
291 | // and vital to S3 resume. That's why we put save code here\r | |
292 | //\r | |
293 | Index = 0;\r | |
294 | while (RegTable[Index] != 0xFF) {\r | |
295 | \r | |
296 | PciAddress.Bus = RegTable[Index++];\r | |
297 | PciAddress.Device = RegTable[Index++];\r | |
298 | PciAddress.Function = RegTable[Index++];\r | |
299 | PciAddress.Register = 0;\r | |
300 | PciAddress.ExtendedRegister = 0;\r | |
301 | \r | |
302 | Data16 = MmioRead16 (\r | |
303 | MmPciAddress (0,\r | |
304 | PciAddress.Bus,\r | |
305 | PciAddress.Device,\r | |
306 | PciAddress.Function,\r | |
307 | PciAddress.Register\r | |
308 | )\r | |
309 | );\r | |
310 | \r | |
311 | if (Data16 == 0xFFFF) {\r | |
312 | Index+=8;\r | |
313 | continue;\r | |
314 | }\r | |
315 | \r | |
316 | for (Offset = 0, Mask = 0x01; Offset < 256; Offset+=4, Mask<<=1) {\r | |
317 | \r | |
318 | if (Mask == 0x00) {\r | |
319 | Mask = 0x01;\r | |
320 | }\r | |
321 | \r | |
322 | if (RegTable[Index + Offset/32] & Mask ) {\r | |
323 | \r | |
324 | PciAddress.Register = (UINT8)Offset;\r | |
325 | Data32 = MmioRead32 (MmPciAddress (0, PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register));\r | |
326 | \r | |
327 | //\r | |
328 | // Save latest settings to runtime script table\r | |
329 | //\r | |
330 | S3BootScriptSavePciCfgWrite (\r | |
331 | S3BootScriptWidthUint32,\r | |
332 | *(UINT64*)&PciAddress,\r | |
333 | 1,\r | |
334 | &Data32\r | |
335 | );\r | |
336 | }\r | |
337 | }\r | |
338 | \r | |
339 | Index += 8;\r | |
340 | \r | |
341 | }\r | |
342 | \r | |
343 | \r | |
344 | //\r | |
345 | // Save I/O ports to S3 script table\r | |
346 | //\r | |
347 | \r | |
348 | //\r | |
349 | // Selftest KBC\r | |
350 | //\r | |
351 | Data8 = 0xAA;\r | |
352 | S3BootScriptSaveIoWrite (\r | |
353 | S3BootScriptWidthUint8,\r | |
354 | 0x64,\r | |
355 | (UINTN)1,\r | |
356 | &Data8\r | |
357 | );\r | |
358 | \r | |
359 | Data32 = IoRead32(mAcpiBaseAddr + R_PCH_SMI_EN);\r | |
360 | \r | |
361 | S3BootScriptSaveIoWrite (\r | |
362 | S3BootScriptWidthUint32,\r | |
363 | (mAcpiBaseAddr + R_PCH_SMI_EN),\r | |
364 | 1,\r | |
365 | &Data32\r | |
366 | );\r | |
367 | \r | |
368 | //\r | |
369 | // Save B_ICH_TCO_CNT_LOCK so it will be done on S3 resume path.\r | |
370 | //\r | |
371 | Data16 = IoRead16(mAcpiBaseAddr + R_PCH_TCO_CNT);\r | |
372 | \r | |
373 | S3BootScriptSaveIoWrite (\r | |
374 | S3BootScriptWidthUint16,\r | |
375 | mAcpiBaseAddr + R_PCH_TCO_CNT,\r | |
376 | 1,\r | |
377 | &Data16\r | |
378 | );\r | |
379 | \r | |
380 | \r | |
381 | return EFI_SUCCESS;\r | |
382 | }\r |