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[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformSmm / S3Save.c
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3cbfba02
DW		 1/** @file\r
2\r
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
4 \r\r
9dc8036d
MK		 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
6\r
3cbfba02
DW		 7 \r\r
8\r
9\r
10Module Name:\r
11\r
12 IchS3Save.c\r
13\r
14Abstract:\r
15\r
16 SMM S3 handler Driver implementation file\r
17\r
18Revision History\r
19\r
20**/\r
21#include "SmmPlatform.h"\r
22\r
23extern UINT16 mAcpiBaseAddr;\r
24EFI_PHYSICAL_ADDRESS mRuntimeScriptTableBase;\r
25\r
26EFI_STATUS\r
27InitRuntimeScriptTable (\r
28 IN EFI_SYSTEM_TABLE *SystemTable\r
29 )\r
30{\r
31 EFI_STATUS Status;\r
32 UINT32 VarAttrib;\r
33 UINTN VarSize;\r
34 ACPI_VARIABLE_SET_COMPATIBILITY *AcpiVariableBase;\r
35\r
36 //\r
37 // Allocate runtime ACPI script table space. We need it to save some\r
38 // settings done by CSM, which runs after normal script table closed\r
39 //\r
40 Status = gBS->AllocatePages (\r
41 AllocateAnyPages,\r
42 EfiACPIReclaimMemory,\r
43 1,\r
44 &mRuntimeScriptTableBase\r
45 );\r
46 if (EFI_ERROR(Status)) {\r
47 return EFI_OUT_OF_RESOURCES ;\r
48 }\r
49\r
50 //\r
51 // Save runtime script table base into global ACPI variable\r
52 //\r
53 VarAttrib = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS\r
54 | EFI_VARIABLE_NON_VOLATILE;\r
55 VarSize = sizeof (UINTN);\r
56 Status = SystemTable->RuntimeServices->GetVariable (\r
57 ACPI_GLOBAL_VARIABLE,\r
58 &gEfiAcpiVariableCompatiblityGuid,\r
59 &VarAttrib,\r
60 &VarSize,\r
61 &AcpiVariableBase\r
62 );\r
63 if (EFI_ERROR(Status)) {\r
64 return Status;\r
65 }\r
66\r
67 AcpiVariableBase->RuntimeScriptTableBase = mRuntimeScriptTableBase;\r
68\r
69 return EFI_SUCCESS;\r
70}\r
71\r
72EFI_STATUS\r
73SaveRuntimeScriptTable (\r
74 VOID\r
75 )\r
76{\r
77 SMM_PCI_IO_ADDRESS PciAddress;\r
78 UINT32 Data32;\r
79 UINT16 Data16;\r
80 UINT8 Data8;\r
81 UINT8 Mask;\r
82 UINTN Index;\r
83 UINTN Offset;\r
84 UINT8 RegTable[] = {\r
85\r
86 //\r
87 //Bus , Dev, Func, DMI\r
88 //\r
89 0x00 , 0x00, 0x00,\r
90\r
91 //\r
92 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
93 //\r
94 0x00 , 0x08, 0x00, 0x00, 0x30, 0x00, 0x00, 0xa0,\r
95\r
96 //\r
97 //Bus , Dev, Func, LPC device\r
98 //\r
99 0x00 , 0x1F, 0x00,\r
100\r
101 //\r
102 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
103 //\r
104 0x00 , 0x08, 0x00, 0x07, 0x00, 0x00, 0x90, 0x00,\r
105\r
106 //\r
107 //Bus , Dev, Func, PCIE device\r
108 //\r
109 0x00 , 0x1C, 0x00,\r
110\r
111 //\r
112 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
113 //\r
114 0xC0 , 0x83, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,\r
115\r
116 //\r
117 //Bus , Dev, Func, PCIE device\r
118 //\r
119 0x00 , 0x1C, 0x00,\r
120\r
121 //\r
122 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
123 //\r
124 0x03 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
125\r
126 //\r
127 //Bus , Dev, Func, SATA device\r
128 //\r
129 0x00 , 0x13, 0x00,\r
130\r
131 //\r
132 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
133 //\r
134 0xf4 , 0xab, 0x27, 0x10, 0xf1, 0x1d, 0x00, 0x40,\r
135\r
136 //\r
137 //Bus , Dev, Func, EHCI device\r
138 //\r
139 0x00 , 0x1D, 0x00,\r
140\r
141 //\r
142 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
143 //\r
144 0x10 , 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,\r
145\r
146 //\r
147 //Bus , Dev, Func, SMBUS device\r
148 //\r
149 0x00 , 0x1f, 0x03,\r
150\r
151 //\r
152 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
153 //\r
154 0x10 , 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
155\r
156 //\r
157 //Bus , Dev, Func, SMBUS device\r
158 //\r
159 0x00 , 0x1f, 0x03,\r
160\r
161 //\r
162 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
163 //\r
164 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
165\r
166 //\r
167 //Bus , Dev, Func, VGA bus1\r
168 //\r
169 0x01 , 0x00, 0x00,\r
170\r
171 //\r
172 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
173 //\r
174 0x58 , 0x81, 0x18, 0x01, 0xb0, 0x00, 0x00, 0x00,\r
175\r
176 //\r
177 //Bus , Dev, Func, VGA bus1\r
178 //\r
179 0x01 , 0x00, 0x00,\r
180\r
181 //\r
182 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
183 //\r
184 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
185\r
186 //\r
187 //Bus , Dev, Func, VGA bus1 function 1\r
188 //\r
189 0x01 , 0x00, 0x01,\r
190\r
191 //\r
192 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
193 //\r
194 0x51 , 0x80, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00,\r
195\r
196 //\r
197 //Bus , Dev, Func, VGA bus1 function 1\r
198 //\r
199 0x01 , 0x00, 0x01,\r
200\r
201 //\r
202 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
203 //\r
204 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
205\r
206 //\r
207 //Bus , Dev, Func, IGD bus0 function 0\r
208 //\r
209 0x00 , 0x02, 0x00,\r
210\r
211 //\r
212 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
213 //\r
214 0x42 , 0x81, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,\r
215\r
216 //\r
217 //Bus , Dev, Func, USB bus0 function 0\r
218 //\r
219 0x00 , 0x16, 0x00,\r
220\r
221 //\r
222 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
223 //\r
224 0x32 , 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
225\r
226 //\r
227 //Bus , Dev, Func, HD Audio bus0 function 0\r
228 //\r
229 0x00 , 0x1B, 0x00,\r
230\r
231 //\r
232 //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
233 //\r
234 0x00 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,\r
235\r
236 //\r
237 //0xFF indicates the end of the table\r
238 //\r
239 0xFF\r
240 };\r
241\r
242 //\r
243 // These registers have to set in byte order\r
244 //\r
245 UINT8 ExtReg[] = { 0x9E, 0x9D }; // SMRAM settings\r
246\r
247\r
248\r
249 //\r
250 // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM\r
251 // and vital to S3 resume. That's why we put save code here\r
252 //\r
253 PciAddress.Bus = 0;\r
254 PciAddress.Device = 0;\r
255 PciAddress.Function = 0;\r
256 PciAddress.ExtendedRegister = 0;\r
257\r
258 for (Index = 0; Index < 2; Index++) {\r
259 //\r
260 // Read SRAM setting from Pci(0, 0, 0)\r
261 //\r
262 PciAddress.Register = ExtReg[Index];\r
263 Data8 = MmioRead8 (\r
264 MmPciAddress (0,\r
265 PciAddress.Bus,\r
266 PciAddress.Device,\r
267 PciAddress.Function,\r
268 PciAddress.Register\r
269 )\r
270 );\r
271\r
272 //\r
273 // Save latest settings to runtime script table\r
274 //\r
275 S3BootScriptSavePciCfgWrite(\r
276 S3BootScriptWidthUint8,\r
277 *(UINT64*)&PciAddress,\r
278 1,\r
279 &Data8\r
280 );\r
281 }\r
282\r
283\r
284 //\r
285 // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM\r
286 // and vital to S3 resume. That's why we put save code here\r
287 //\r
288 Index = 0;\r
289 while (RegTable[Index] != 0xFF) {\r
290\r
291 PciAddress.Bus = RegTable[Index++];\r
292 PciAddress.Device = RegTable[Index++];\r
293 PciAddress.Function = RegTable[Index++];\r
294 PciAddress.Register = 0;\r
295 PciAddress.ExtendedRegister = 0;\r
296\r
297 Data16 = MmioRead16 (\r
298 MmPciAddress (0,\r
299 PciAddress.Bus,\r
300 PciAddress.Device,\r
301 PciAddress.Function,\r
302 PciAddress.Register\r
303 )\r
304 );\r
305\r
306 if (Data16 == 0xFFFF) {\r
307 Index+=8;\r
308 continue;\r
309 }\r
310\r
311 for (Offset = 0, Mask = 0x01; Offset < 256; Offset+=4, Mask<<=1) {\r
312\r
313 if (Mask == 0x00) {\r
314 Mask = 0x01;\r
315 }\r
316\r
317 if (RegTable[Index + Offset/32] & Mask ) {\r
318\r
319 PciAddress.Register = (UINT8)Offset;\r
320 Data32 = MmioRead32 (MmPciAddress (0, PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register));\r
321\r
322 //\r
323 // Save latest settings to runtime script table\r
324 //\r
325 S3BootScriptSavePciCfgWrite (\r
326 S3BootScriptWidthUint32,\r
327 *(UINT64*)&PciAddress,\r
328 1,\r
329 &Data32\r
330 );\r
331 }\r
332 }\r
333\r
334 Index += 8;\r
335\r
336 }\r
337\r
338\r
339 //\r
340 // Save I/O ports to S3 script table\r
341 //\r
342\r
343 //\r
344 // Selftest KBC\r
345 //\r
346 Data8 = 0xAA;\r
347 S3BootScriptSaveIoWrite (\r
348 S3BootScriptWidthUint8,\r
349 0x64,\r
350 (UINTN)1,\r
351 &Data8\r
352 );\r
353\r
354 Data32 = IoRead32(mAcpiBaseAddr + R_PCH_SMI_EN);\r
355\r
356 S3BootScriptSaveIoWrite (\r
357 S3BootScriptWidthUint32,\r
358 (mAcpiBaseAddr + R_PCH_SMI_EN),\r
359 1,\r
360 &Data32\r
361 );\r
362\r
363 //\r
364 // Save B_ICH_TCO_CNT_LOCK so it will be done on S3 resume path.\r
365 //\r
366 Data16 = IoRead16(mAcpiBaseAddr + R_PCH_TCO_CNT);\r
367\r
368 S3BootScriptSaveIoWrite (\r
369 S3BootScriptWidthUint16,\r
370 mAcpiBaseAddr + R_PCH_TCO_CNT,\r
371 1,\r
372 &Data16\r
373 );\r
374\r
375\r
376 return EFI_SUCCESS;\r
377}\r
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