ArmPkg/CompilerIntrinsicsLib: Add uread, uwrite GCC assembly sources

[mirror_edk2.git] / Vlv2TbltDevicePkg / VlvPlatformInitDxe / VlvPlatformInit.c

\r
/*++\r
\r
Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
                                                                                   \r\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
                                                                                   \r\r
\r
\r
Module Name:\r
\r
  VlvPlatformInit.c\r
\r
Abstract:\r
\r
  This is the driver that initializes the Intel ValleyView.\r
\r
--*/\r
\r
#include "VlvPlatformInit.h"\r
#include <Protocol/VlvPlatformPolicy.h>\r
\r
extern DXE_VLV_PLATFORM_POLICY_PROTOCOL  *DxePlatformSaPolicy;\r
UINT64            GTTMMADR;\r
\r
DXE_VLV_PLATFORM_POLICY_PROTOCOL  *DxePlatformSaPolicy;\r
\r
/**\r
  "Poll Status" for GT Readiness\r
\r
 @param  Base             Base address of MMIO\r
 @param  Offset           MMIO Offset\r
 @param  Mask             Mask\r
 @param  Result           Value to wait for\r
\r
 @retval None\r
\r
**/\r
VOID\r
PollGtReady_hang (\r
  UINT64 Base,\r
  UINT32 Offset,\r
  UINT32 Mask,\r
  UINT32 Result\r
  )\r
{\r
  UINT32  GtStatus;\r
\r
  //\r
  // Register read\r
  //\r
  GtStatus = MmioRead32 ((UINTN)Base+ Offset);\r
\r
  while (((GtStatus & Mask) != Result)) {\r
\r
    GtStatus = MmioRead32 ((UINTN)Base + Offset);\r
  }\r
\r
}\r
\r
/**\r
  Do Post GT PM Init Steps after VBIOS Initialization.\r
\r
  @param Event             A pointer to the Event that triggered the callback.\r
  @param Context           A pointer to private data registered with the callback function.\r
\r
  @retval EFI_SUCCESS        GC_TODO\r
\r
\r
**/\r
EFI_STATUS\r
EFIAPI    \r
PostPmInitCallBack (\r
  IN EFI_EVENT Event,\r
  IN VOID      *Context\r
  )\r
{\r
  UINT64      OriginalGTTMMADR;\r
  UINT32      LoGTBaseAddress;\r
  UINT32      HiGTBaseAddress;\r
\r
  //\r
  // Enable Bus Master, I/O and Memory access on 0:2:0\r
  //\r
  PciOr8 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_CMD), (BIT2 | BIT1));\r
\r
  //\r
  // only 32bit read/write is legal for device 0:2:0\r
  //\r
  OriginalGTTMMADR  = (UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR));\r
  OriginalGTTMMADR  = LShiftU64 ((UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR + 4)), 32) | (OriginalGTTMMADR);\r
\r
  //\r
  // 64bit GTTMADR does not work for S3 save script table since it is executed in PEIM phase\r
  // Program temporarily 32bits GTTMMADR for POST and S3 resume\r
  //\r
  LoGTBaseAddress                   = (UINT32) (GTTMMADR & 0xFFFFFFFF);\r
  HiGTBaseAddress                   = (UINT32) RShiftU64 ((GTTMMADR & 0xFFFFFFFF00000000), 32);\r
  S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);\r
  S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);\r
\r
\r
\r
  //\r
  // Restore original GTTMMADR\r
  //\r
  LoGTBaseAddress                   = (UINT32) (OriginalGTTMMADR & 0xFFFFFFFF);\r
  HiGTBaseAddress                   = (UINT32) RShiftU64 ((OriginalGTTMMADR & 0xFFFFFFFF00000000), 32);\r
\r
  S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);\r
  S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);\r
\r
\r
  //\r
  // Lock the following registers, GGC, BDSM, BGSM\r
  //\r
  PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_MGGC_OFFSET), LockBit);\r
  PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_BSM_OFFSET), LockBit);\r
  PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_BGSM), LockBit);\r
\r
  gBS->CloseEvent (Event);\r
\r
  //\r
  // Return final status\r
  //\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
\r
  Routine Description:\r
\r
  Initialize GT Post Routines.\r
\r
  @param ImageHandle              Handle for the image of this driver\r
  @param DxePlatformSaPolicy      SA DxePlatformPolicy protocol\r
\r
  @retval EFI_SUCCESS             GT POST initialization complete\r
\r
**/\r
EFI_STATUS\r
IgdPmHook (\r
  IN EFI_HANDLE                      ImageHandle,\r
  IN DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicyParam\r
  )\r
{\r
\r
  EFI_EVENT             mConOutEvent;\r
  VOID                  *gConOutNotifyReg;\r
\r
  EFI_STATUS            Status;\r
\r
  EFI_PHYSICAL_ADDRESS  MemBaseAddress;\r
  UINT32                LoGTBaseAddress;\r
  UINT32                HiGTBaseAddress;\r
\r
  GTTMMADR    = 0;\r
  Status      = EFI_SUCCESS;\r
\r
  //\r
  // If device 0:2:0 (Internal Graphics Device, or GT) is enabled, then Program GTTMMADR,\r
  //\r
  if (PciRead16(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_VID))  != 0xFFFF) {\r
\r
    ASSERT (gDS!=NULL);\r
\r
    //\r
    // Enable Bus Master, I/O and Memory access on 0:2:0\r
    //\r
    PciOr8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD), (BIT2 | BIT1 | BIT0));\r
\r
    //\r
    // Means Allocate 4MB for GTTMADDR\r
    //\r
    MemBaseAddress = 0x0ffffffff;\r
\r
    Status = gDS->AllocateMemorySpace (\r
                    EfiGcdAllocateMaxAddressSearchBottomUp,\r
                    EfiGcdMemoryTypeMemoryMappedIo,\r
                    GTT_MEM_ALIGN,\r
                    GTTMMADR_SIZE_4MB,\r
                    &MemBaseAddress,\r
                    ImageHandle,\r
                    NULL\r
                    );\r
    ASSERT_EFI_ERROR (Status);\r
\r
    //\r
    // Program GT PM Settings if GTTMMADR allocation is Successful\r
    //\r
    GTTMMADR                          = (UINTN) MemBaseAddress;\r
\r
    LoGTBaseAddress                   = (UINT32) (MemBaseAddress & 0xFFFFFFFF);\r
    HiGTBaseAddress                   = (UINT32) RShiftU64 ((MemBaseAddress & 0xFFFFFFFF00000000), 32);\r
\r
    PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR), LoGTBaseAddress);\r
    PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR+4), HiGTBaseAddress);\r
\r
\r
    S3PciRead32(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR));\r
\r
\r
    S3MmioRead32(IGD_R_GTTMMADR + 4);\r
\r
\r
    S3PciRead8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD));\r
\r
    //\r
    // Do POST GT PM Init Steps after VBIOS Initialization in DoPostPmInitCallBack\r
    //\r
    Status = gBS->CreateEvent (\r
                    EVT_NOTIFY_SIGNAL,\r
                    TPL_CALLBACK,\r
                    (EFI_EVENT_NOTIFY)PostPmInitCallBack,\r
                    NULL,\r
                    &mConOutEvent\r
                    );\r
\r
    ASSERT_EFI_ERROR (Status);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
\r
\r
    Status = gBS->RegisterProtocolNotify (\r
                    &gEfiGraphicsOutputProtocolGuid,\r
                    mConOutEvent,\r
                    &gConOutNotifyReg\r
                    );\r
\r
\r
\r
    MmioWrite64 (IGD_R_GTTMMADR, 0);\r
\r
    //\r
    // Free allocated resources\r
    //\r
    gDS->FreeMemorySpace (\r
           MemBaseAddress,\r
           GTTMMADR_SIZE_4MB\r
           );\r
\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
\r
  This is the standard EFI driver point that detects\r
  whether there is an ICH southbridge in the system\r
  and if so, initializes the chip.\r
\r
  @param  ImageHandle             Handle for the image of this driver\r
  @param  SystemTable             Pointer to the EFI System Table\r
\r
  @retval EFI_SUCCESS             The function completed successfully\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
VlvPlatformInitEntryPoint (\r
  IN EFI_HANDLE       ImageHandle,\r
  IN EFI_SYSTEM_TABLE *SystemTable\r
  )\r
{\r
  EFI_STATUS                        Status;\r
\r
  Status = gBS->LocateProtocol (&gDxeVlvPlatformPolicyGuid, NULL, (void **)&DxePlatformSaPolicy);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // GtPostInit Initialization\r
  //\r
  DEBUG ((EFI_D_ERROR, "Initializing GT PowerManagement and other GT POST related\n"));\r
  IgdPmHook (ImageHandle, DxePlatformSaPolicy);\r
\r
  //\r
  // IgdOpRegion Install Initialization\r
  //\r
  DEBUG ((EFI_D_ERROR, "Initializing IGD OpRegion\n"));\r
  IgdOpRegionInit ();\r
\r
  return EFI_SUCCESS;\r
}\r
\r