]>
Commit | Line | Data |
---|---|---|
3cbfba02 DW |
1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | Module Name:\r | |
15 | \r | |
16 | LpcSio.h\r | |
17 | \r | |
18 | Abstract:\r | |
19 | \r | |
20 | Lpc driver's sio interface\r | |
21 | \r | |
22 | \r | |
23 | \r | |
24 | --*/\r | |
25 | \r | |
26 | #ifndef _LPC_SIO_H\r | |
27 | #define _LPC_SIO_H\r | |
28 | \r | |
29 | #include "Protocol/PciRootBridgeIo.h"\r | |
30 | \r | |
31 | #define VARSIOINSTALLED L"VarSIOProcotolInstalled"\r | |
32 | \r | |
33 | //\r | |
34 | // Port address\r | |
35 | //\r | |
36 | #define CONFIG_PORT 0x04E\r | |
37 | #define INDEX_PORT 0x04E\r | |
38 | #define DATA_PORT INDEX_PORT + 1\r | |
39 | \r | |
40 | //\r | |
41 | // Logical Device\r | |
42 | //\r | |
43 | #define SIO_COM 0x3\r | |
44 | #define SIO_MSWC 0x4\r | |
45 | #define SIO_MOUSE 0x5\r | |
46 | #define SIO_KEYBOARD 0x6\r | |
47 | #define SIO_SHM 0xF\r | |
48 | #define SIO_PM1 0x11\r | |
49 | #define SIO_PM2 0x12\r | |
50 | #define SIO_PM3 0x17\r | |
51 | #define SIO_ESHM 0x1D\r | |
52 | \r | |
53 | //\r | |
54 | // Global register\r | |
55 | //\r | |
56 | #define REG_LOGICAL_DEVICE 0x07\r | |
57 | #define REG_DEVICE_ID 0x20\r | |
58 | #define SIO_CONFIG_1 0x21\r | |
59 | #define REG_CHIP_REV 0x24\r | |
60 | #define SIO_CONFIG_5 0x25\r | |
61 | #define SIO_CONFIG_6 0x26\r | |
62 | #define REG_DEVICE_REV 0x27\r | |
63 | #define SIO_CONFIG_9 0x29\r | |
64 | #define SIO_CONFIG_D 0x2D\r | |
65 | \r | |
66 | #define ACTIVATE 0x30\r | |
67 | #define BASE_ADDRESS_HIGH 0x60\r | |
68 | #define BASE_ADDRESS_LOW 0x61\r | |
69 | #define BASE_ADDRESS_HIGH2 0x62\r | |
70 | #define BASE_ADDRESS_LOW2 0x63\r | |
71 | #define PRIMARY_INTERRUPT_SELECT 0x70\r | |
72 | #define DMA_CHANNEL_SELECT 0x74\r | |
73 | \r | |
74 | EFI_STATUS\r | |
75 | InitializeLpcSio (\r | |
76 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo\r | |
77 | );\r | |
78 | \r | |
79 | //\r | |
80 | // Prototypes for the sio internal function\r | |
81 | //\r | |
82 | //\r | |
83 | // Internal function\r | |
84 | //\r | |
85 | VOID\r | |
86 | LPCWPCE791SetDefault (\r | |
87 | VOID\r | |
88 | );\r | |
89 | \r | |
90 | VOID\r | |
91 | WriteRegisterAndSaveToScript (\r | |
92 | IN UINT8 Index,\r | |
93 | IN UINT8 Data\r | |
94 | );\r | |
95 | \r | |
96 | VOID\r | |
97 | FloppyWriteProtect (\r | |
98 | VOID\r | |
99 | );\r | |
100 | \r | |
101 | VOID\r | |
102 | DisableLogicalDevice (\r | |
103 | UINT8 DeviceId\r | |
104 | );\r | |
105 | \r | |
106 | #endif\r |