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CommitLineData
7d13299d 1/*
e965fc38 2 * emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
fb0343d5 9 * version 2.1 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
a8d25326 19
7b31bbc2 20#include "qemu/osdep.h"
740b1759 21#include "qemu/qemu-print.h"
3a841ab5 22#include "qapi/error.h"
3a841ab5 23#include "qapi/type-helpers.h"
78271684 24#include "hw/core/tcg-cpu-ops.h"
d9bb58e5 25#include "trace.h"
76cad711 26#include "disas/disas.h"
63c91552 27#include "exec/exec-all.h"
dcb32f1d 28#include "tcg/tcg.h"
1de7afc9 29#include "qemu/atomic.h"
79e2b9ae 30#include "qemu/rcu.h"
508127e2 31#include "exec/log.h"
8d04fb55 32#include "qemu/main-loop.h"
6220e900
PD
33#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
34#include "hw/i386/apic.h"
35#endif
d2528bdc 36#include "sysemu/cpus.h"
740b1759
CF
37#include "exec/cpu-all.h"
38#include "sysemu/cpu-timers.h"
5b5968c4 39#include "exec/replay-core.h"
3a841ab5 40#include "sysemu/tcg.h"
a3e7f702 41#include "exec/helper-proto-common.h"
a976a99a 42#include "tb-jmp-cache.h"
e5ceadff 43#include "tb-hash.h"
e5ceadff 44#include "tb-context.h"
5934660f 45#include "internal-common.h"
4c268d6d 46#include "internal-target.h"
c2aa5f81
ST
47
48/* -icount align implementation. */
49
50typedef struct SyncClocks {
51 int64_t diff_clk;
52 int64_t last_cpu_icount;
7f7bc144 53 int64_t realtime_clock;
c2aa5f81
ST
54} SyncClocks;
55
56#if !defined(CONFIG_USER_ONLY)
57/* Allow the guest to have a max 3ms advance.
58 * The difference between the 2 clocks could therefore
59 * oscillate around 0.
60 */
61#define VM_CLOCK_ADVANCE 3000000
7f7bc144
ST
62#define THRESHOLD_REDUCE 1.5
63#define MAX_DELAY_PRINT_RATE 2000000000LL
64#define MAX_NB_PRINTS 100
c2aa5f81 65
00c9a5c2
PMD
66int64_t max_delay;
67int64_t max_advance;
740b1759 68
5e140196 69static void align_clocks(SyncClocks *sc, CPUState *cpu)
c2aa5f81
ST
70{
71 int64_t cpu_icount;
72
73 if (!icount_align_option) {
74 return;
75 }
76
a953b5fa 77 cpu_icount = cpu->icount_extra + cpu->neg.icount_decr.u16.low;
8191d368 78 sc->diff_clk += icount_to_ns(sc->last_cpu_icount - cpu_icount);
c2aa5f81
ST
79 sc->last_cpu_icount = cpu_icount;
80
81 if (sc->diff_clk > VM_CLOCK_ADVANCE) {
82#ifndef _WIN32
83 struct timespec sleep_delay, rem_delay;
84 sleep_delay.tv_sec = sc->diff_clk / 1000000000LL;
85 sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL;
86 if (nanosleep(&sleep_delay, &rem_delay) < 0) {
a498d0ef 87 sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec;
c2aa5f81
ST
88 } else {
89 sc->diff_clk = 0;
90 }
91#else
92 Sleep(sc->diff_clk / SCALE_MS);
93 sc->diff_clk = 0;
94#endif
95 }
96}
97
7f7bc144
ST
98static void print_delay(const SyncClocks *sc)
99{
100 static float threshold_delay;
101 static int64_t last_realtime_clock;
102 static int nb_prints;
103
104 if (icount_align_option &&
105 sc->realtime_clock - last_realtime_clock >= MAX_DELAY_PRINT_RATE &&
106 nb_prints < MAX_NB_PRINTS) {
107 if ((-sc->diff_clk / (float)1000000000LL > threshold_delay) ||
108 (-sc->diff_clk / (float)1000000000LL <
109 (threshold_delay - THRESHOLD_REDUCE))) {
110 threshold_delay = (-sc->diff_clk / 1000000000LL) + 1;
740b1759
CF
111 qemu_printf("Warning: The guest is now late by %.1f to %.1f seconds\n",
112 threshold_delay - 1,
113 threshold_delay);
7f7bc144
ST
114 nb_prints++;
115 last_realtime_clock = sc->realtime_clock;
116 }
117 }
118}
119
5e140196 120static void init_delay_params(SyncClocks *sc, CPUState *cpu)
c2aa5f81
ST
121{
122 if (!icount_align_option) {
123 return;
124 }
2e91cc62
PB
125 sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
126 sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock;
5e140196 127 sc->last_cpu_icount
a953b5fa 128 = cpu->icount_extra + cpu->neg.icount_decr.u16.low;
27498bef
ST
129 if (sc->diff_clk < max_delay) {
130 max_delay = sc->diff_clk;
131 }
132 if (sc->diff_clk > max_advance) {
133 max_advance = sc->diff_clk;
134 }
7f7bc144
ST
135
136 /* Print every 2s max if the guest is late. We limit the number
137 of printed messages to NB_PRINT_MAX(currently 100) */
138 print_delay(sc);
c2aa5f81
ST
139}
140#else
141static void align_clocks(SyncClocks *sc, const CPUState *cpu)
142{
143}
144
145static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
146{
147}
148#endif /* CONFIG USER ONLY */
7d13299d 149
043e35d9
RH
150uint32_t curr_cflags(CPUState *cpu)
151{
84f15616
RH
152 uint32_t cflags = cpu->tcg_cflags;
153
04f5b647 154 /*
c2ffd754
RH
155 * Record gdb single-step. We should be exiting the TB by raising
156 * EXCP_DEBUG, but to simplify other tests, disable chaining too.
157 *
04f5b647
RH
158 * For singlestep and -d nochain, suppress goto_tb so that
159 * we can log -d cpu,exec after every TB.
160 */
c2ffd754
RH
161 if (unlikely(cpu->singlestep_enabled)) {
162 cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1;
0e33928c 163 } else if (qatomic_read(&one_insn_per_tb)) {
04f5b647
RH
164 cflags |= CF_NO_GOTO_TB | 1;
165 } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
fb957011 166 cflags |= CF_NO_GOTO_TB;
84f15616
RH
167 }
168
169 return cflags;
043e35d9
RH
170}
171
0c90ba16 172struct tb_desc {
f0a08b09
AJ
173 vaddr pc;
174 uint64_t cs_base;
0c90ba16 175 CPUArchState *env;
93b99616 176 tb_page_addr_t page_addr0;
0c90ba16
RH
177 uint32_t flags;
178 uint32_t cflags;
0c90ba16
RH
179};
180
181static bool tb_lookup_cmp(const void *p, const void *d)
182{
183 const TranslationBlock *tb = p;
184 const struct tb_desc *desc = d;
185
279513c7 186 if ((tb_cflags(tb) & CF_PCREL || tb->pc == desc->pc) &&
28905cfb 187 tb_page_addr0(tb) == desc->page_addr0 &&
0c90ba16
RH
188 tb->cs_base == desc->cs_base &&
189 tb->flags == desc->flags &&
0c90ba16
RH
190 tb_cflags(tb) == desc->cflags) {
191 /* check next page if needed */
28905cfb
RH
192 tb_page_addr_t tb_phys_page1 = tb_page_addr1(tb);
193 if (tb_phys_page1 == -1) {
0c90ba16
RH
194 return true;
195 } else {
93b99616 196 tb_page_addr_t phys_page1;
f0a08b09 197 vaddr virt_page1;
0c90ba16 198
9867b302
RH
199 /*
200 * We know that the first page matched, and an otherwise valid TB
201 * encountered an incomplete instruction at the end of that page,
202 * therefore we know that generating a new TB from the current PC
203 * must also require reading from the next page -- even if the
204 * second pages do not match, and therefore the resulting insn
205 * is different for the new TB. Therefore any exception raised
206 * here by the faulting lookup is not premature.
207 */
93b99616
RH
208 virt_page1 = TARGET_PAGE_ALIGN(desc->pc);
209 phys_page1 = get_page_addr_code(desc->env, virt_page1);
28905cfb 210 if (tb_phys_page1 == phys_page1) {
0c90ba16
RH
211 return true;
212 }
213 }
214 }
215 return false;
216}
217
f0a08b09
AJ
218static TranslationBlock *tb_htable_lookup(CPUState *cpu, vaddr pc,
219 uint64_t cs_base, uint32_t flags,
0c90ba16
RH
220 uint32_t cflags)
221{
222 tb_page_addr_t phys_pc;
223 struct tb_desc desc;
224 uint32_t h;
225
b77af26e 226 desc.env = cpu_env(cpu);
0c90ba16
RH
227 desc.cs_base = cs_base;
228 desc.flags = flags;
229 desc.cflags = cflags;
0c90ba16
RH
230 desc.pc = pc;
231 phys_pc = get_page_addr_code(desc.env, pc);
232 if (phys_pc == -1) {
233 return NULL;
234 }
93b99616 235 desc.page_addr0 = phys_pc;
4be79026 236 h = tb_hash_func(phys_pc, (cflags & CF_PCREL ? 0 : pc),
367189ef 237 flags, cs_base, cflags);
0c90ba16
RH
238 return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
239}
240
632cb63d 241/* Might cause an exception, so have a longjmp destination ready */
f0a08b09
AJ
242static inline TranslationBlock *tb_lookup(CPUState *cpu, vaddr pc,
243 uint64_t cs_base, uint32_t flags,
244 uint32_t cflags)
632cb63d
RH
245{
246 TranslationBlock *tb;
8ed558ec 247 CPUJumpCache *jc;
632cb63d
RH
248 uint32_t hash;
249
250 /* we should never be trying to look up an INVALID tb */
251 tcg_debug_assert(!(cflags & CF_INVALID));
252
253 hash = tb_jmp_cache_hash_func(pc);
8ed558ec 254 jc = cpu->tb_jmp_cache;
632cb63d 255
d157e540
PB
256 tb = qatomic_read(&jc->array[hash].tb);
257 if (likely(tb &&
258 jc->array[hash].pc == pc &&
259 tb->cs_base == cs_base &&
260 tb->flags == flags &&
261 tb_cflags(tb) == cflags)) {
262 goto hit;
632cb63d 263 }
2dd5b7a1 264
d157e540
PB
265 tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags);
266 if (tb == NULL) {
267 return NULL;
268 }
269
270 jc->array[hash].pc = pc;
271 qatomic_set(&jc->array[hash].tb, tb);
272
273hit:
274 /*
275 * As long as tb is not NULL, the contents are consistent. Therefore,
276 * the virtual PC has to match for non-CF_PCREL translations.
277 */
278 assert((tb_cflags(tb) & CF_PCREL) || tb->pc == pc);
632cb63d
RH
279 return tb;
280}
281
f0a08b09 282static void log_cpu_exec(vaddr pc, CPUState *cpu,
fbf59aad 283 const TranslationBlock *tb)
abb0cd93 284{
fbf59aad 285 if (qemu_log_in_addr_range(pc)) {
abb0cd93 286 qemu_log_mask(CPU_LOG_EXEC,
85314e13 287 "Trace %d: %p [%08" PRIx64
e60a7d0d 288 "/%016" VADDR_PRIx "/%08x/%08x] %s\n",
7eabad36
RH
289 cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc,
290 tb->flags, tb->cflags, lookup_symbol(pc));
abb0cd93 291
abb0cd93 292 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
c60f599b 293 FILE *logfile = qemu_log_trylock();
78b54858
RH
294 if (logfile) {
295 int flags = 0;
abb0cd93 296
78b54858
RH
297 if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
298 flags |= CPU_DUMP_FPU;
299 }
abb0cd93 300#if defined(TARGET_I386)
78b54858 301 flags |= CPU_DUMP_CCOP;
abb0cd93 302#endif
b84694de
IK
303 if (qemu_loglevel_mask(CPU_LOG_TB_VPU)) {
304 flags |= CPU_DUMP_VPU;
305 }
c769fbd7 306 cpu_dump_state(cpu, logfile, flags);
78b54858
RH
307 qemu_log_unlock(logfile);
308 }
abb0cd93 309 }
abb0cd93
RH
310 }
311}
312
f0a08b09 313static bool check_for_breakpoints_slow(CPUState *cpu, vaddr pc,
69993c4e 314 uint32_t *cflags)
10c37828
RH
315{
316 CPUBreakpoint *bp;
317 bool match_page = false;
318
10c37828
RH
319 /*
320 * Singlestep overrides breakpoints.
321 * This requirement is visible in the record-replay tests, where
322 * we would fail to make forward progress in reverse-continue.
323 *
324 * TODO: gdb singlestep should only override gdb breakpoints,
325 * so that one could (gdb) singlestep into the guest kernel's
326 * architectural breakpoint handler.
327 */
328 if (cpu->singlestep_enabled) {
329 return false;
330 }
331
332 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
333 /*
334 * If we have an exact pc match, trigger the breakpoint.
335 * Otherwise, note matches within the page.
336 */
337 if (pc == bp->pc) {
338 bool match_bp = false;
339
340 if (bp->flags & BP_GDB) {
341 match_bp = true;
342 } else if (bp->flags & BP_CPU) {
343#ifdef CONFIG_USER_ONLY
344 g_assert_not_reached();
345#else
991bd65d
RH
346 const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
347 assert(tcg_ops->debug_check_breakpoint);
348 match_bp = tcg_ops->debug_check_breakpoint(cpu);
10c37828
RH
349#endif
350 }
351
352 if (match_bp) {
353 cpu->exception_index = EXCP_DEBUG;
354 return true;
355 }
356 } else if (((pc ^ bp->pc) & TARGET_PAGE_MASK) == 0) {
357 match_page = true;
358 }
359 }
360
361 /*
362 * Within the same page as a breakpoint, single-step,
363 * returning to helper_lookup_tb_ptr after each insn looking
364 * for the actual breakpoint.
365 *
366 * TODO: Perhaps better to record all of the TBs associated
367 * with a given virtual page that contains a breakpoint, and
368 * then invalidate them when a new overlapping breakpoint is
369 * set on the page. Non-overlapping TBs would not be
370 * invalidated, nor would any TB need to be invalidated as
371 * breakpoints are removed.
372 */
373 if (match_page) {
374 *cflags = (*cflags & ~CF_COUNT_MASK) | CF_NO_GOTO_TB | 1;
375 }
376 return false;
377}
378
f0a08b09 379static inline bool check_for_breakpoints(CPUState *cpu, vaddr pc,
69993c4e
LL
380 uint32_t *cflags)
381{
382 return unlikely(!QTAILQ_EMPTY(&cpu->breakpoints)) &&
383 check_for_breakpoints_slow(cpu, pc, cflags);
384}
385
4288eb26
RH
386/**
387 * helper_lookup_tb_ptr: quick check for next tb
388 * @env: current cpu state
389 *
390 * Look for an existing TB matching the current cpu state.
391 * If found, return the code pointer. If not found, return
392 * the tcg epilogue so that we return into cpu_tb_exec.
393 */
394const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
395{
396 CPUState *cpu = env_cpu(env);
397 TranslationBlock *tb;
bb5de525
AJ
398 vaddr pc;
399 uint64_t cs_base;
10c37828 400 uint32_t flags, cflags;
4288eb26
RH
401
402 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
403
10c37828
RH
404 cflags = curr_cflags(cpu);
405 if (check_for_breakpoints(cpu, pc, &cflags)) {
406 cpu_loop_exit(cpu);
407 }
408
409 tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
4288eb26
RH
410 if (tb == NULL) {
411 return tcg_code_gen_epilogue;
412 }
abb0cd93 413
fbf59aad
RH
414 if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) {
415 log_cpu_exec(pc, cpu, tb);
416 }
abb0cd93 417
4288eb26
RH
418 return tb->tc.ptr;
419}
420
77211379 421/* Execute a TB, and fix up the CPU state afterwards if necessary */
c905a368
DB
422/*
423 * Disable CFI checks.
424 * TCG creates binary blobs at runtime, with the transformed code.
425 * A TB is a blob of binary code, created at runtime and called with an
426 * indirect function call. Since such function did not exist at compile time,
427 * the CFI runtime has no way to verify its signature and would fail.
428 * TCG is not considered a security-sensitive part of QEMU so this does not
429 * affect the impact of CFI in environment with high security requirements
430 */
eba40358
RH
431static inline TranslationBlock * QEMU_DISABLE_CFI
432cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
77211379 433{
b77af26e 434 CPUArchState *env = cpu_env(cpu);
819af24b
SF
435 uintptr_t ret;
436 TranslationBlock *last_tb;
db0c51a3 437 const void *tb_ptr = itb->tc.ptr;
1a830635 438
fbf59aad
RH
439 if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) {
440 log_cpu_exec(log_pc(cpu, itb), cpu, itb);
441 }
03afa5f8 442
653b87eb 443 qemu_thread_jit_execute();
819af24b 444 ret = tcg_qemu_tb_exec(env, tb_ptr);
464dacf6 445 cpu->neg.can_do_io = true;
e04660af 446 qemu_plugin_disable_mem_helpers(cpu);
eba40358
RH
447 /*
448 * TODO: Delay swapping back to the read-write region of the TB
449 * until we actually need to modify the TB. The read-only copy,
450 * coming from the rx region, shares the same host TLB entry as
451 * the code that executed the exit_tb opcode that arrived here.
452 * If we insist on touching both the RX and the RW pages, we
453 * double the host TLB pressure.
454 */
455 last_tb = tcg_splitwx_to_rw((void *)(ret & ~TB_EXIT_MASK));
456 *tb_exit = ret & TB_EXIT_MASK;
457
458 trace_exec_tb_exit(last_tb, *tb_exit);
6db8b538 459
eba40358 460 if (*tb_exit > TB_EXIT_IDX1) {
77211379
PM
461 /* We didn't start executing this TB (eg because the instruction
462 * counter hit zero); we must restore the guest PC to the address
463 * of the start of the TB.
464 */
991bd65d
RH
465 CPUClass *cc = cpu->cc;
466 const TCGCPUOps *tcg_ops = cc->tcg_ops;
fbf59aad 467
991bd65d
RH
468 if (tcg_ops->synchronize_from_tb) {
469 tcg_ops->synchronize_from_tb(cpu, last_tb);
bdf7ae5b 470 } else {
4be79026 471 tcg_debug_assert(!(tb_cflags(last_tb) & CF_PCREL));
bdf7ae5b 472 assert(cc->set_pc);
279513c7 473 cc->set_pc(cpu, last_tb->pc);
fbf59aad
RH
474 }
475 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
f0a08b09 476 vaddr pc = log_pc(cpu, last_tb);
fbf59aad 477 if (qemu_log_in_addr_range(pc)) {
e60a7d0d 478 qemu_log("Stopped execution of TB chain before %p [%016"
f0a08b09 479 VADDR_PRIx "] %s\n",
fbf59aad
RH
480 last_tb->tc.ptr, pc, lookup_symbol(pc));
481 }
bdf7ae5b 482 }
77211379 483 }
c9460d75
RH
484
485 /*
486 * If gdb single-step, and we haven't raised another exception,
487 * raise a debug exception. Single-step with another exception
488 * is handled in cpu_handle_exception.
489 */
490 if (unlikely(cpu->singlestep_enabled) && cpu->exception_index == -1) {
491 cpu->exception_index = EXCP_DEBUG;
492 cpu_loop_exit(cpu);
493 }
494
eba40358 495 return last_tb;
77211379
PM
496}
497
2e70f6ef 498
035ba06c
EH
499static void cpu_exec_enter(CPUState *cpu)
500{
991bd65d 501 const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
035ba06c 502
991bd65d
RH
503 if (tcg_ops->cpu_exec_enter) {
504 tcg_ops->cpu_exec_enter(cpu);
80c4750b 505 }
035ba06c
EH
506}
507
508static void cpu_exec_exit(CPUState *cpu)
fdbc2b57 509{
991bd65d 510 const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
035ba06c 511
991bd65d
RH
512 if (tcg_ops->cpu_exec_exit) {
513 tcg_ops->cpu_exec_exit(cpu);
80c4750b 514 }
035ba06c
EH
515}
516
cb62bd15
RH
517static void cpu_exec_longjmp_cleanup(CPUState *cpu)
518{
519 /* Non-buggy compilers preserve this; assert the correct value. */
520 g_assert(cpu == current_cpu);
521
522#ifdef CONFIG_USER_ONLY
523 clear_helper_retaddr();
524 if (have_mmap_lock()) {
525 mmap_unlock();
526 }
deba7870
RH
527#else
528 /*
529 * For softmmu, a tlb_fill fault during translation will land here,
530 * and we need to release any page locks held. In system mode we
531 * have one tcg_ctx per thread, so we know it was this cpu doing
532 * the translation.
533 *
534 * Alternative 1: Install a cleanup to be called via an exception
535 * handling safe longjmp. It seems plausible that all our hosts
536 * support such a thing. We'd have to properly register unwind info
537 * for the JIT for EH, rather that just for GDB.
538 *
539 * Alternative 2: Set and restore cpu->jmp_env in tb_gen_code to
540 * capture the cpu_loop_exit longjmp, perform the cleanup, and
541 * jump again to arrive here.
542 */
543 if (tcg_ctx->gen_tb) {
544 tb_unlock_pages(tcg_ctx->gen_tb);
545 tcg_ctx->gen_tb = NULL;
546 }
cb62bd15 547#endif
195801d7
SH
548 if (bql_locked()) {
549 bql_unlock();
cb62bd15
RH
550 }
551 assert_no_pages_locked();
552}
553
035ba06c
EH
554void cpu_exec_step_atomic(CPUState *cpu)
555{
b77af26e 556 CPUArchState *env = cpu_env(cpu);
fdbc2b57 557 TranslationBlock *tb;
bb5de525
AJ
558 vaddr pc;
559 uint64_t cs_base;
258afb48 560 uint32_t flags, cflags;
eba40358 561 int tb_exit;
fdbc2b57 562
08e73c48 563 if (sigsetjmp(cpu->jmp_env, 0) == 0) {
886cc689 564 start_exclusive();
bfff072c
DC
565 g_assert(cpu == current_cpu);
566 g_assert(!cpu->running);
567 cpu->running = true;
886cc689 568
6f04cb1c 569 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
6f04cb1c 570
258afb48
RH
571 cflags = curr_cflags(cpu);
572 /* Execute in a serial context. */
573 cflags &= ~CF_PARALLEL;
574 /* After 1 insn, return and release the exclusive lock. */
575 cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1;
10c37828
RH
576 /*
577 * No need to check_for_breakpoints here.
578 * We only arrive in cpu_exec_step_atomic after beginning execution
579 * of an insn that includes an atomic operation we can't handle.
580 * Any breakpoint for this insn will have been recognized earlier.
581 */
258afb48
RH
582
583 tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
4e2ca83e
EC
584 if (tb == NULL) {
585 mmap_lock();
95590e24 586 tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
4e2ca83e
EC
587 mmap_unlock();
588 }
08e73c48 589
035ba06c 590 cpu_exec_enter(cpu);
08e73c48 591 /* execute the generated code */
4e2ca83e 592 trace_exec_tb(tb, pc);
eba40358 593 cpu_tb_exec(cpu, tb, &tb_exit);
035ba06c 594 cpu_exec_exit(cpu);
08e73c48 595 } else {
cb62bd15 596 cpu_exec_longjmp_cleanup(cpu);
08e73c48 597 }
426eeecd 598
886cc689
AB
599 /*
600 * As we start the exclusive region before codegen we must still
601 * be in the region if we longjump out of either the codegen or
602 * the execution.
603 */
604 g_assert(cpu_in_exclusive_context(cpu));
bfff072c 605 cpu->running = false;
886cc689 606 end_exclusive();
fdbc2b57
RH
607}
608
a8583393
RH
609void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr)
610{
2fd2e78d
RH
611 /*
612 * Get the rx view of the structure, from which we find the
613 * executable code address, and tb_target_set_jmp_target can
614 * produce a pc-relative displacement to jmp_target_addr[n].
615 */
616 const TranslationBlock *c_tb = tcg_splitwx_to_rx(tb);
617 uintptr_t offset = tb->jmp_insn_offset[n];
618 uintptr_t jmp_rx = (uintptr_t)tb->tc.ptr + offset;
619 uintptr_t jmp_rw = jmp_rx - tcg_splitwx_diff;
620
9da6079b 621 tb->jmp_target_addr[n] = addr;
2fd2e78d 622 tb_target_set_jmp_target(c_tb, n, jmp_rx, jmp_rw);
a8583393
RH
623}
624
a8583393
RH
625static inline void tb_add_jump(TranslationBlock *tb, int n,
626 TranslationBlock *tb_next)
627{
194125e3
EC
628 uintptr_t old;
629
653b87eb 630 qemu_thread_jit_write();
a8583393 631 assert(n < ARRAY_SIZE(tb->jmp_list_next));
194125e3
EC
632 qemu_spin_lock(&tb_next->jmp_lock);
633
634 /* make sure the destination TB is valid */
635 if (tb_next->cflags & CF_INVALID) {
636 goto out_unlock_next;
637 }
638 /* Atomically claim the jump destination slot only if it was NULL */
d73415a3
SH
639 old = qatomic_cmpxchg(&tb->jmp_dest[n], (uintptr_t)NULL,
640 (uintptr_t)tb_next);
194125e3
EC
641 if (old) {
642 goto out_unlock_next;
a8583393 643 }
194125e3
EC
644
645 /* patch the native jump address */
646 tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc.ptr);
647
648 /* add in TB jmp list */
649 tb->jmp_list_next[n] = tb_next->jmp_list_head;
650 tb_next->jmp_list_head = (uintptr_t)tb | n;
651
652 qemu_spin_unlock(&tb_next->jmp_lock);
653
fbf59aad
RH
654 qemu_log_mask(CPU_LOG_EXEC, "Linking TBs %p index %d -> %p\n",
655 tb->tc.ptr, n, tb_next->tc.ptr);
194125e3 656 return;
a8583393 657
194125e3
EC
658 out_unlock_next:
659 qemu_spin_unlock(&tb_next->jmp_lock);
660 return;
a8583393
RH
661}
662
8b2d34e9
SF
663static inline bool cpu_handle_halt(CPUState *cpu)
664{
0596fa11 665#ifndef CONFIG_USER_ONLY
8b2d34e9 666 if (cpu->halted) {
0596fa11 667#if defined(TARGET_I386)
4084893d 668 if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
8b2d34e9 669 X86CPU *x86_cpu = X86_CPU(cpu);
195801d7 670 bql_lock();
8b2d34e9
SF
671 apic_poll_irq(x86_cpu->apic_state);
672 cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL);
195801d7 673 bql_unlock();
8b2d34e9 674 }
0596fa11 675#endif /* TARGET_I386 */
8b2d34e9 676 if (!cpu_has_work(cpu)) {
8b2d34e9
SF
677 return true;
678 }
679
680 cpu->halted = 0;
681 }
0596fa11 682#endif /* !CONFIG_USER_ONLY */
8b2d34e9
SF
683
684 return false;
685}
686
ea284766 687static inline void cpu_handle_debug_exception(CPUState *cpu)
1009d2ed 688{
991bd65d 689 const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
1009d2ed
JK
690 CPUWatchpoint *wp;
691
ff4700b0
AF
692 if (!cpu->watchpoint_hit) {
693 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1009d2ed
JK
694 wp->flags &= ~BP_WATCHPOINT_HIT;
695 }
696 }
86025ee4 697
991bd65d
RH
698 if (tcg_ops->debug_excp_handler) {
699 tcg_ops->debug_excp_handler(cpu);
710384d0 700 }
1009d2ed
JK
701}
702
ea284766
SF
703static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
704{
17b50b0c
PD
705 if (cpu->exception_index < 0) {
706#ifndef CONFIG_USER_ONLY
707 if (replay_has_exception()
a953b5fa 708 && cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0) {
a11bbb6a 709 /* Execute just one insn to trigger exception pending in the log */
c3e97f64 710 cpu->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT)
cf9b5790 711 | CF_NOIRQ | 1;
17b50b0c
PD
712 }
713#endif
a11bbb6a 714 return false;
17b50b0c 715 }
991bd65d 716
17b50b0c
PD
717 if (cpu->exception_index >= EXCP_INTERRUPT) {
718 /* exit request from the cpu execution loop */
719 *ret = cpu->exception_index;
720 if (*ret == EXCP_DEBUG) {
721 cpu_handle_debug_exception(cpu);
722 }
723 cpu->exception_index = -1;
724 return true;
991bd65d
RH
725 }
726
ea284766 727#if defined(CONFIG_USER_ONLY)
991bd65d
RH
728 /*
729 * If user mode only, we simulate a fake exception which will be
730 * handled outside the cpu execution loop.
731 */
ea284766 732#if defined(TARGET_I386)
991bd65d
RH
733 const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
734 tcg_ops->fake_user_interrupt(cpu);
12096421 735#endif /* TARGET_I386 */
991bd65d
RH
736 *ret = cpu->exception_index;
737 cpu->exception_index = -1;
738 return true;
17b50b0c 739#else
991bd65d
RH
740 if (replay_exception()) {
741 const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
a7ba744f 742
991bd65d
RH
743 bql_lock();
744 tcg_ops->do_interrupt(cpu);
745 bql_unlock();
746 cpu->exception_index = -1;
747
748 if (unlikely(cpu->singlestep_enabled)) {
749 /*
750 * After processing the exception, ensure an EXCP_DEBUG is
751 * raised when single-stepping so that GDB doesn't miss the
752 * next instruction.
753 */
754 *ret = EXCP_DEBUG;
755 cpu_handle_debug_exception(cpu);
ea284766 756 return true;
ea284766 757 }
991bd65d
RH
758 } else if (!replay_has_interrupt()) {
759 /* give a chance to iothread in replay mode */
760 *ret = EXCP_INTERRUPT;
761 return true;
ea284766 762 }
991bd65d 763#endif
ea284766
SF
764
765 return false;
766}
767
77c0fc4e 768#ifndef CONFIG_USER_ONLY
4084893d
PD
769/*
770 * CPU_INTERRUPT_POLL is a virtual event which gets converted into a
771 * "real" interrupt event later. It does not need to be recorded for
772 * replay purposes.
773 */
0fdc69b7 774static inline bool need_replay_interrupt(CPUState *cpu, int interrupt_request)
4084893d
PD
775{
776#if defined(TARGET_I386)
777 return !(interrupt_request & CPU_INTERRUPT_POLL);
778#else
0fdc69b7
PMD
779 const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
780 return !tcg_ops->need_replay_interrupt
781 || tcg_ops->need_replay_interrupt(interrupt_request);
4084893d
PD
782#endif
783}
77c0fc4e 784#endif /* !CONFIG_USER_ONLY */
4084893d 785
93c6091b
PMD
786static inline bool icount_exit_request(CPUState *cpu)
787{
788 if (!icount_enabled()) {
789 return false;
790 }
791 if (cpu->cflags_next_tb != -1 && !(cpu->cflags_next_tb & CF_USE_ICOUNT)) {
792 return false;
793 }
794 return cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0;
795}
796
209b71b6 797static inline bool cpu_handle_interrupt(CPUState *cpu,
c385e6e4
SF
798 TranslationBlock **last_tb)
799{
aff0e204
AB
800 /*
801 * If we have requested custom cflags with CF_NOIRQ we should
802 * skip checking here. Any pending interrupts will get picked up
803 * by the next TB we execute under normal cflags.
804 */
805 if (cpu->cflags_next_tb != -1 && cpu->cflags_next_tb & CF_NOIRQ) {
806 return false;
807 }
808
17b50b0c
PD
809 /* Clear the interrupt flag now since we're processing
810 * cpu->interrupt_request and cpu->exit_request.
d84be02d
DH
811 * Ensure zeroing happens before reading cpu->exit_request or
812 * cpu->interrupt_request (see also smp_wmb in cpu_exit())
17b50b0c 813 */
a953b5fa 814 qatomic_set_mb(&cpu->neg.icount_decr.u16.high, 0);
c385e6e4 815
d73415a3 816 if (unlikely(qatomic_read(&cpu->interrupt_request))) {
8d04fb55 817 int interrupt_request;
195801d7 818 bql_lock();
8d04fb55 819 interrupt_request = cpu->interrupt_request;
c385e6e4
SF
820 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
821 /* Mask out external interrupts for this step. */
822 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
823 }
824 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
825 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
826 cpu->exception_index = EXCP_DEBUG;
195801d7 827 bql_unlock();
209b71b6 828 return true;
c385e6e4 829 }
77c0fc4e 830#if !defined(CONFIG_USER_ONLY)
c385e6e4
SF
831 if (replay_mode == REPLAY_MODE_PLAY && !replay_has_interrupt()) {
832 /* Do nothing */
833 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
834 replay_interrupt();
835 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
836 cpu->halted = 1;
837 cpu->exception_index = EXCP_HLT;
195801d7 838 bql_unlock();
209b71b6 839 return true;
c385e6e4
SF
840 }
841#if defined(TARGET_I386)
842 else if (interrupt_request & CPU_INTERRUPT_INIT) {
843 X86CPU *x86_cpu = X86_CPU(cpu);
844 CPUArchState *env = &x86_cpu->env;
845 replay_interrupt();
65c9d60a 846 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0);
c385e6e4
SF
847 do_cpu_init(x86_cpu);
848 cpu->exception_index = EXCP_HALTED;
195801d7 849 bql_unlock();
209b71b6 850 return true;
c385e6e4
SF
851 }
852#else
853 else if (interrupt_request & CPU_INTERRUPT_RESET) {
854 replay_interrupt();
855 cpu_reset(cpu);
195801d7 856 bql_unlock();
209b71b6 857 return true;
c385e6e4 858 }
77c0fc4e 859#endif /* !TARGET_I386 */
c385e6e4
SF
860 /* The target hook has 3 exit conditions:
861 False when the interrupt isn't processed,
862 True when it is, and we should restart on a new TB,
863 and via longjmp via cpu_loop_exit. */
864 else {
991bd65d 865 const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
77c0fc4e 866
991bd65d
RH
867 if (tcg_ops->cpu_exec_interrupt &&
868 tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) {
0fdc69b7 869 if (need_replay_interrupt(cpu, interrupt_request)) {
4084893d
PD
870 replay_interrupt();
871 }
ba3c35d9
RH
872 /*
873 * After processing the interrupt, ensure an EXCP_DEBUG is
874 * raised when single-stepping so that GDB doesn't miss the
875 * next instruction.
876 */
5b7b197c
LM
877 if (unlikely(cpu->singlestep_enabled)) {
878 cpu->exception_index = EXCP_DEBUG;
195801d7 879 bql_unlock();
5b7b197c
LM
880 return true;
881 }
882 cpu->exception_index = -1;
c385e6e4
SF
883 *last_tb = NULL;
884 }
8b1fe3f4
SF
885 /* The target hook may have updated the 'cpu->interrupt_request';
886 * reload the 'interrupt_request' value */
887 interrupt_request = cpu->interrupt_request;
c385e6e4 888 }
77c0fc4e 889#endif /* !CONFIG_USER_ONLY */
8b1fe3f4 890 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
c385e6e4
SF
891 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
892 /* ensure that no TB jump will be modified as
893 the program flow was changed */
894 *last_tb = NULL;
895 }
8d04fb55
JK
896
897 /* If we exit via cpu_loop_exit/longjmp it is reset in cpu_exec */
195801d7 898 bql_unlock();
c385e6e4 899 }
8d04fb55 900
cfb2d02b 901 /* Finally, check if we need to exit to the main loop. */
93c6091b 902 if (unlikely(qatomic_read(&cpu->exit_request)) || icount_exit_request(cpu)) {
d73415a3 903 qatomic_set(&cpu->exit_request, 0);
5f3bdfd4
PD
904 if (cpu->exception_index == -1) {
905 cpu->exception_index = EXCP_INTERRUPT;
906 }
209b71b6 907 return true;
c385e6e4 908 }
209b71b6
PB
909
910 return false;
c385e6e4
SF
911}
912
928de9ee 913static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
f0a08b09
AJ
914 vaddr pc, TranslationBlock **last_tb,
915 int *tb_exit)
928de9ee 916{
1aab16c2 917 int32_t insns_left;
928de9ee 918
fbf59aad 919 trace_exec_tb(tb, pc);
eba40358 920 tb = cpu_tb_exec(cpu, tb, tb_exit);
1aab16c2
PB
921 if (*tb_exit != TB_EXIT_REQUESTED) {
922 *last_tb = tb;
923 return;
924 }
925
926 *last_tb = NULL;
a953b5fa 927 insns_left = qatomic_read(&cpu->neg.icount_decr.u32);
1aab16c2 928 if (insns_left < 0) {
e5143e30
AB
929 /* Something asked us to stop executing chained TBs; just
930 * continue round the main loop. Whatever requested the exit
30f3dda2 931 * will also have set something else (eg exit_request or
17b50b0c
PD
932 * interrupt_request) which will be handled by
933 * cpu_handle_interrupt. cpu_handle_interrupt will also
934 * clear cpu->icount_decr.u16.high.
928de9ee 935 */
1aab16c2 936 return;
928de9ee 937 }
1aab16c2
PB
938
939 /* Instruction counter expired. */
740b1759 940 assert(icount_enabled());
1aab16c2 941#ifndef CONFIG_USER_ONLY
eda5f7c6 942 /* Ensure global icount has gone forward */
8191d368 943 icount_update(cpu);
eda5f7c6 944 /* Refill decrementer and continue execution. */
df3a2de5 945 insns_left = MIN(0xffff, cpu->icount_budget);
a953b5fa 946 cpu->neg.icount_decr.u16.low = insns_left;
eda5f7c6 947 cpu->icount_extra = cpu->icount_budget - insns_left;
bc662a33
AB
948
949 /*
950 * If the next tb has more instructions than we have left to
951 * execute we need to ensure we find/generate a TB with exactly
952 * insns_left instructions in it.
953 */
c8cf47a9
PM
954 if (insns_left > 0 && insns_left < tb->icount) {
955 assert(insns_left <= CF_COUNT_MASK);
956 assert(cpu->icount_extra == 0);
bc662a33 957 cpu->cflags_next_tb = (tb->cflags & ~CF_COUNT_MASK) | insns_left;
928de9ee 958 }
1aab16c2 959#endif
928de9ee
SF
960}
961
7d13299d
FB
962/* main execution loop */
963
61710a7e
RH
964static int __attribute__((noinline))
965cpu_exec_loop(CPUState *cpu, SyncClocks *sc)
7d13299d 966{
c385e6e4 967 int ret;
4515e58d
PB
968
969 /* if an exception is pending, we execute it here */
970 while (!cpu_handle_exception(cpu, &ret)) {
971 TranslationBlock *last_tb = NULL;
972 int tb_exit = 0;
973
974 while (!cpu_handle_interrupt(cpu, &last_tb)) {
9b990ee5 975 TranslationBlock *tb;
bb5de525
AJ
976 vaddr pc;
977 uint64_t cs_base;
11c1d5f8
RH
978 uint32_t flags, cflags;
979
b77af26e 980 cpu_get_tb_cpu_state(cpu_env(cpu), &pc, &cs_base, &flags);
10c37828 981
11c1d5f8
RH
982 /*
983 * When requested, use an exact setting for cflags for the next
984 * execution. This is used for icount, precise smc, and stop-
985 * after-access watchpoints. Since this request should never
986 * have CF_INVALID set, -1 is a convenient invalid value that
987 * does not require tcg headers for cpu_common_reset.
988 */
989 cflags = cpu->cflags_next_tb;
9b990ee5 990 if (cflags == -1) {
c0ae396a 991 cflags = curr_cflags(cpu);
9b990ee5
RH
992 } else {
993 cpu->cflags_next_tb = -1;
994 }
995
10c37828
RH
996 if (check_for_breakpoints(cpu, pc, &cflags)) {
997 break;
998 }
11c1d5f8
RH
999
1000 tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
1001 if (tb == NULL) {
3371802f 1002 CPUJumpCache *jc;
a976a99a
RH
1003 uint32_t h;
1004
11c1d5f8
RH
1005 mmap_lock();
1006 tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
1007 mmap_unlock();
3371802f 1008
11c1d5f8
RH
1009 /*
1010 * We add the TB in the virtual pc hash table
1011 * for the fast lookup
1012 */
a976a99a 1013 h = tb_jmp_cache_hash_func(pc);
3371802f 1014 jc = cpu->tb_jmp_cache;
d157e540
PB
1015 jc->array[h].pc = pc;
1016 qatomic_set(&jc->array[h].tb, tb);
11c1d5f8
RH
1017 }
1018
1019#ifndef CONFIG_USER_ONLY
1020 /*
1021 * We don't take care of direct jumps when address mapping
1022 * changes in system emulation. So it's not safe to make a
1023 * direct jump to a TB spanning two pages because the mapping
1024 * for the second page can change.
1025 */
28905cfb 1026 if (tb_page_addr1(tb) != -1) {
11c1d5f8
RH
1027 last_tb = NULL;
1028 }
1029#endif
1030 /* See if we can patch the calling TB. */
1031 if (last_tb) {
1032 tb_add_jump(last_tb, tb_exit, tb);
1033 }
1034
fbf59aad 1035 cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit);
11c1d5f8 1036
4515e58d
PB
1037 /* Try to align the host and virtual clocks
1038 if the guest is in advance */
61710a7e
RH
1039 align_clocks(sc, cpu);
1040 }
1041 }
1042 return ret;
1043}
1044
1045static int cpu_exec_setjmp(CPUState *cpu, SyncClocks *sc)
1046{
1047 /* Prepare setjmp context for exception handling. */
1048 if (unlikely(sigsetjmp(cpu->jmp_env, 0) != 0)) {
cb62bd15 1049 cpu_exec_longjmp_cleanup(cpu);
61710a7e
RH
1050 }
1051
1052 return cpu_exec_loop(cpu, sc);
1053}
1054
1055int cpu_exec(CPUState *cpu)
1056{
1057 int ret;
1058 SyncClocks sc = { 0 };
1059
1060 /* replay_interrupt may need current_cpu */
1061 current_cpu = cpu;
1062
1063 if (cpu_handle_halt(cpu)) {
1064 return EXCP_HALTED;
4515e58d 1065 }
3fb2ded1 1066
f5e9362a 1067 RCU_READ_LOCK_GUARD();
61710a7e
RH
1068 cpu_exec_enter(cpu);
1069
1070 /*
1071 * Calculate difference between guest clock and host clock.
1072 * This delay includes the delay of the last cycle, so
1073 * what we have to do is sleep until it is 0. As for the
1074 * advance/delay we gain here, we try to fix it next time.
1075 */
1076 init_delay_params(&sc, cpu);
1077
1078 ret = cpu_exec_setjmp(cpu, &sc);
1079
035ba06c 1080 cpu_exec_exit(cpu);
7d13299d
FB
1081 return ret;
1082}
740b1759 1083
fa312f2e 1084bool tcg_exec_realizefn(CPUState *cpu, Error **errp)
7df5e3d6
CF
1085{
1086 static bool tcg_target_initialized;
7df5e3d6
CF
1087
1088 if (!tcg_target_initialized) {
991bd65d 1089 cpu->cc->tcg_ops->initialize();
7df5e3d6
CF
1090 tcg_target_initialized = true;
1091 }
7df5e3d6 1092
4e4fa6c1
RH
1093 cpu->tb_jmp_cache = g_new0(CPUJumpCache, 1);
1094 tlb_init(cpu);
7df5e3d6
CF
1095#ifndef CONFIG_USER_ONLY
1096 tcg_iommu_init_notifier_list(cpu);
1097#endif /* !CONFIG_USER_ONLY */
4e4fa6c1 1098 /* qemu_plugin_vcpu_init_hook delayed until cpu_index assigned. */
fa312f2e
PMD
1099
1100 return true;
7df5e3d6
CF
1101}
1102
1103/* undo the initializations in reverse order */
1104void tcg_exec_unrealizefn(CPUState *cpu)
1105{
1106#ifndef CONFIG_USER_ONLY
1107 tcg_iommu_free_notifier_list(cpu);
1108#endif /* !CONFIG_USER_ONLY */
1109
7df5e3d6 1110 tlb_destroy(cpu);
4731f89b 1111 g_free_rcu(cpu->tb_jmp_cache, rcu);
7df5e3d6 1112}