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ARM: dts: exynos: Remove "cooling-{min|max}-level" for CPU nodes
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / exynos5250.dtsi
CommitLineData
b074abb7
KK		 1/*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
fe273c3e 20#include <dt-bindings/clock/exynos5250.h>
e6c21cba 21#include "exynos5.dtsi"
9843a223 22#include "exynos4-cpu-thermal.dtsi"
602408e3 23#include <dt-bindings/clock/exynos-audss-clk.h>
b074abb7
KK		 24
25/ {
8bdb31b4 26 compatible = "samsung,exynos5250", "samsung,exynos5";
b074abb7 27
79989ba3
TA		 28 aliases {
29 spi0 = &spi_0;
30 spi1 = &spi_1;
31 spi2 = &spi_2;
1128658a
SAB		 32 gsc0 = &gsc_0;
33 gsc1 = &gsc_1;
34 gsc2 = &gsc_2;
35 gsc3 = &gsc_3;
c8149df0
YK		 36 mshc0 = &mmc_0;
37 mshc1 = &mmc_1;
38 mshc2 = &mmc_2;
39 mshc3 = &mmc_3;
b9fa3e7b
AK		 40 i2c4 = &i2c_4;
41 i2c5 = &i2c_5;
42 i2c6 = &i2c_6;
43 i2c7 = &i2c_7;
44 i2c8 = &i2c_8;
ba0d7ed3 45 i2c9 = &i2c_9;
f8bfe2b0
TA		 46 pinctrl0 = &pinctrl_0;
47 pinctrl1 = &pinctrl_1;
48 pinctrl2 = &pinctrl_2;
49 pinctrl3 = &pinctrl_3;
79989ba3
TA		 50 };
51
1897d2f3
CK		 52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
bf4a0bed 56 cpu0: cpu@0 {
1897d2f3
CK		 57 device_type = "cpu";
58 compatible = "arm,cortex-a15";
59 reg = <0>;
0da80563 60 clock-frequency = <1700000000>;
846c5300
TA		 61 clocks = <&clock CLK_ARM_CLK>;
62 clock-names = "cpu";
63 clock-latency = <140000>;
64
65 operating-points = <
66 1700000 1300000
67 1600000 1250000
68 1500000 1225000
69 1400000 1200000
70 1300000 1150000
71 1200000 1125000
72 1100000 1100000
73 1000000 1075000
74 900000 1050000
75 800000 1025000
76 700000 1012500
77 600000 1000000
78 500000 975000
79 400000 950000
80 300000 937500
81 200000 925000
82 >;
bf4a0bed 83 #cooling-cells = <2>; /* min followed by max */
1897d2f3
CK		 84 };
85 cpu@1 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a15";
88 reg = <1>;
0da80563 89 clock-frequency = <1700000000>;
1897d2f3 90 };
79989ba3
TA		 91 };
92
5d99cc59 93 soc: soc {
8dccafaa 94 sysram@2020000 {
5d99cc59
KK		 95 compatible = "mmio-sram";
96 reg = <0x02020000 0x30000>;
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges = <0 0x02020000 0x30000>;
100
101 smp-sysram@0 {
102 compatible = "samsung,exynos4210-sysram";
103 reg = <0x0 0x1000>;
104 };
105
106 smp-sysram@2f000 {
107 compatible = "samsung,exynos4210-sysram-ns";
108 reg = <0x2f000 0x1000>;
109 };
b3205dea
SK		 110 };
111
5d99cc59
KK		 112 pd_gsc: gsc-power-domain@10044000 {
113 compatible = "samsung,exynos4210-pd";
114 reg = <0x10044000 0x20>;
115 #power-domain-cells = <0>;
55d74adf 116 label = "GSC";
b3205dea 117 };
6f9e95e6 118
5d99cc59
KK		 119 pd_mfc: mfc-power-domain@10044040 {
120 compatible = "samsung,exynos4210-pd";
121 reg = <0x10044040 0x20>;
122 #power-domain-cells = <0>;
55d74adf 123 label = "MFC";
5d99cc59 124 };
6f9e95e6 125
5d99cc59
KK		 126 pd_disp1: disp1-power-domain@100440A0 {
127 compatible = "samsung,exynos4210-pd";
128 reg = <0x100440A0 0x20>;
129 #power-domain-cells = <0>;
55d74adf 130 label = "DISP1";
5d99cc59
KK		 131 clocks = <&clock CLK_FIN_PLL>,
132 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
133 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
134 clock-names = "oscclk", "clk0", "clk1";
135 };
2d2c9a8d 136
5d99cc59
KK		 137 clock: clock-controller@10010000 {
138 compatible = "samsung,exynos5250-clock";
139 reg = <0x10010000 0x30000>;
140 #clock-cells = <1>;
141 };
d8bafc87 142
5d99cc59
KK		 143 clock_audss: audss-clock-controller@3810000 {
144 compatible = "samsung,exynos5250-audss-clock";
145 reg = <0x03810000 0x0C>;
146 #clock-cells = <1>;
147 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
148 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
149 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
150 };
bba23d95 151
5d99cc59
KK		 152 timer {
153 compatible = "arm,armv7-timer";
c92a4fb2
KK		 154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
5d99cc59
KK		 158 /*
159 * Unfortunately we need this since some versions
160 * of U-Boot on Exynos don't set the CNTFRQ register,
161 * so we need the value from DT.
162 */
163 clock-frequency = <24000000>;
164 };
b074abb7 165
5d99cc59
KK		 166 mct@101C0000 {
167 compatible = "samsung,exynos4210-mct";
168 reg = <0x101C0000 0x800>;
169 interrupt-controller;
bbd9700a 170 #interrupt-cells = <2>;
5d99cc59
KK		 171 interrupt-parent = <&mct_map>;
172 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
173 <4 0>, <5 0>;
174 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
175 clock-names = "fin_pll", "mct";
176
177 mct_map: mct-map {
178 #interrupt-cells = <2>;
179 #address-cells = <0>;
180 #size-cells = <0>;
181 interrupt-map = <0x0 0 &combiner 23 3>,
182 <0x1 0 &combiner 23 4>,
183 <0x2 0 &combiner 25 2>,
184 <0x3 0 &combiner 25 3>,
27e64b27
KK		 185 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
186 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 187 };
bbd9700a 188 };
bbd9700a 189
5d99cc59
KK		 190 pmu {
191 compatible = "arm,cortex-a15-pmu";
192 interrupt-parent = <&combiner>;
193 interrupts = <1 2>, <22 4>;
194 };
4f801e59 195
5d99cc59
KK		 196 pinctrl_0: pinctrl@11400000 {
197 compatible = "samsung,exynos5250-pinctrl";
198 reg = <0x11400000 0x1000>;
888950b0 199 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
f8bfe2b0 200
5d99cc59
KK		 201 wakup_eint: wakeup-interrupt-controller {
202 compatible = "samsung,exynos4210-wakeup-eint";
203 interrupt-parent = <&gic>;
888950b0 204 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 205 };
f8bfe2b0 206 };
f8bfe2b0 207
5d99cc59
KK		 208 pinctrl_1: pinctrl@13400000 {
209 compatible = "samsung,exynos5250-pinctrl";
210 reg = <0x13400000 0x1000>;
888950b0 211 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 212 };
f8bfe2b0 213
5d99cc59
KK		 214 pinctrl_2: pinctrl@10d10000 {
215 compatible = "samsung,exynos5250-pinctrl";
216 reg = <0x10d10000 0x1000>;
888950b0 217 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 218 };
f8bfe2b0 219
8dccafaa 220 pinctrl_3: pinctrl@3860000 {
5d99cc59
KK		 221 compatible = "samsung,exynos5250-pinctrl";
222 reg = <0x03860000 0x1000>;
888950b0 223 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59 224 };
f8bfe2b0 225
5d99cc59
KK		 226 pmu_system_controller: system-controller@10040000 {
227 compatible = "samsung,exynos5250-pmu", "syscon";
228 reg = <0x10040000 0x5000>;
229 clock-names = "clkout16";
230 clocks = <&clock CLK_FIN_PLL>;
231 #clock-cells = <1>;
232 interrupt-controller;
233 #interrupt-cells = <3>;
234 interrupt-parent = <&gic>;
235 };
c680036a 236
5d99cc59
KK		 237 watchdog@101D0000 {
238 compatible = "samsung,exynos5250-wdt";
239 reg = <0x101D0000 0x100>;
888950b0 240 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 241 clocks = <&clock CLK_WDT>;
242 clock-names = "watchdog";
243 samsung,syscon-phandle = <&pmu_system_controller>;
244 };
b074abb7 245
5d99cc59
KK		 246 g2d@10850000 {
247 compatible = "samsung,exynos5250-g2d";
248 reg = <0x10850000 0x1000>;
888950b0 249 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 250 clocks = <&clock CLK_G2D>;
251 clock-names = "fimg2d";
252 iommus = <&sysmmu_g2d>;
253 };
21aa5217 254
5d99cc59
KK		 255 mfc: codec@11000000 {
256 compatible = "samsung,mfc-v6";
257 reg = <0x11000000 0x10000>;
888950b0 258 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 259 power-domains = <&pd_mfc>;
260 clocks = <&clock CLK_MFC>;
261 clock-names = "mfc";
262 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
263 iommu-names = "left", "right";
264 };
2eae613b 265
5d99cc59
KK		 266 rotator: rotator@11C00000 {
267 compatible = "samsung,exynos5250-rotator";
268 reg = <0x11C00000 0x64>;
888950b0 269 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 270 clocks = <&clock CLK_ROTATOR>;
271 clock-names = "rotator";
272 iommus = <&sysmmu_rotator>;
273 };
d35e20d9 274
5d99cc59
KK		 275 tmu: tmu@10060000 {
276 compatible = "samsung,exynos5250-tmu";
277 reg = <0x10060000 0x100>;
888950b0 278 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 279 clocks = <&clock CLK_TMU>;
280 clock-names = "tmu_apbif";
281 #include "exynos4412-tmu-sensor-conf.dtsi"
282 };
ef405e04 283
5d99cc59
KK		 284 sata: sata@122F0000 {
285 compatible = "snps,dwc-ahci";
286 samsung,sata-freq = <66>;
287 reg = <0x122F0000 0x1ff>;
888950b0 288 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 289 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
290 clock-names = "sata", "sclk_sata";
291 phys = <&sata_phy>;
292 phy-names = "sata-phy";
293 status = "disabled";
294 };
9843a223 295
5d99cc59
KK		 296 sata_phy: sata-phy@12170000 {
297 compatible = "samsung,exynos5250-sata-phy";
298 reg = <0x12170000 0x1ff>;
299 clocks = <&clock CLK_SATA_PHYCTRL>;
300 clock-names = "sata_phyctrl";
301 #phy-cells = <0>;
302 samsung,syscon-phandle = <&pmu_system_controller>;
303 status = "disabled";
bf4a0bed 304 };
bf4a0bed 305
5d99cc59
KK		 306 /* i2c_0-3 are defined in exynos5.dtsi */
307 i2c_4: i2c@12CA0000 {
308 compatible = "samsung,s3c2440-i2c";
309 reg = <0x12CA0000 0x100>;
888950b0 310 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 311 #address-cells = <1>;
312 #size-cells = <0>;
313 clocks = <&clock CLK_I2C4>;
314 clock-names = "i2c";
315 pinctrl-names = "default";
316 pinctrl-0 = <&i2c4_bus>;
317 status = "disabled";
318 };
c47d244a 319
5d99cc59
KK		 320 i2c_5: i2c@12CB0000 {
321 compatible = "samsung,s3c2440-i2c";
322 reg = <0x12CB0000 0x100>;
888950b0 323 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 324 #address-cells = <1>;
325 #size-cells = <0>;
326 clocks = <&clock CLK_I2C5>;
327 clock-names = "i2c";
328 pinctrl-names = "default";
329 pinctrl-0 = <&i2c5_bus>;
330 status = "disabled";
331 };
c47d244a 332
5d99cc59
KK		 333 i2c_6: i2c@12CC0000 {
334 compatible = "samsung,s3c2440-i2c";
335 reg = <0x12CC0000 0x100>;
888950b0 336 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 337 #address-cells = <1>;
338 #size-cells = <0>;
339 clocks = <&clock CLK_I2C6>;
340 clock-names = "i2c";
341 pinctrl-names = "default";
342 pinctrl-0 = <&i2c6_bus>;
343 status = "disabled";
344 };
b074abb7 345
5d99cc59
KK		 346 i2c_7: i2c@12CD0000 {
347 compatible = "samsung,s3c2440-i2c";
348 reg = <0x12CD0000 0x100>;
888950b0 349 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 350 #address-cells = <1>;
351 #size-cells = <0>;
352 clocks = <&clock CLK_I2C7>;
353 clock-names = "i2c";
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c7_bus>;
356 status = "disabled";
357 };
b074abb7 358
5d99cc59
KK		 359 i2c_8: i2c@12CE0000 {
360 compatible = "samsung,s3c2440-hdmiphy-i2c";
361 reg = <0x12CE0000 0x1000>;
888950b0 362 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 363 #address-cells = <1>;
364 #size-cells = <0>;
365 clocks = <&clock CLK_I2C_HDMI>;
366 clock-names = "i2c";
367 status = "disabled";
c55af083
MS		 368
369 hdmiphy: hdmiphy@38 {
370 compatible = "samsung,exynos4212-hdmiphy";
371 reg = <0x38>;
372 };
5d99cc59 373 };
b074abb7 374
5d99cc59
KK		 375 i2c_9: i2c@121D0000 {
376 compatible = "samsung,exynos5-sata-phy-i2c";
377 reg = <0x121D0000 0x100>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 clocks = <&clock CLK_SATA_PHYI2C>;
381 clock-names = "i2c";
382 status = "disabled";
383 };
3e3e9ce4 384
5d99cc59
KK		 385 spi_0: spi@12d20000 {
386 compatible = "samsung,exynos4210-spi";
387 status = "disabled";
388 reg = <0x12d20000 0x100>;
888950b0 389 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 390 dmas = <&pdma0 5
391 &pdma0 4>;
392 dma-names = "tx", "rx";
393 #address-cells = <1>;
394 #size-cells = <0>;
395 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
396 clock-names = "spi", "spi_busclk0";
397 pinctrl-names = "default";
398 pinctrl-0 = <&spi0_bus>;
399 };
24025f6f 400
5d99cc59
KK		 401 spi_1: spi@12d30000 {
402 compatible = "samsung,exynos4210-spi";
403 status = "disabled";
404 reg = <0x12d30000 0x100>;
888950b0 405 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 406 dmas = <&pdma1 5
407 &pdma1 4>;
408 dma-names = "tx", "rx";
409 #address-cells = <1>;
410 #size-cells = <0>;
411 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
412 clock-names = "spi", "spi_busclk0";
413 pinctrl-names = "default";
414 pinctrl-0 = <&spi1_bus>;
415 };
b074abb7 416
5d99cc59
KK		 417 spi_2: spi@12d40000 {
418 compatible = "samsung,exynos4210-spi";
419 status = "disabled";
420 reg = <0x12d40000 0x100>;
888950b0 421 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 422 dmas = <&pdma0 7
423 &pdma0 6>;
424 dma-names = "tx", "rx";
425 #address-cells = <1>;
426 #size-cells = <0>;
427 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
428 clock-names = "spi", "spi_busclk0";
429 pinctrl-names = "default";
430 pinctrl-0 = <&spi2_bus>;
431 };
79989ba3 432
5d99cc59
KK		 433 mmc_0: mmc@12200000 {
434 compatible = "samsung,exynos5250-dw-mshc";
888950b0 435 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 436 #address-cells = <1>;
437 #size-cells = <0>;
438 reg = <0x12200000 0x1000>;
439 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
440 clock-names = "biu", "ciu";
441 fifo-depth = <0x80>;
442 status = "disabled";
443 };
79989ba3 444
5d99cc59
KK		 445 mmc_1: mmc@12210000 {
446 compatible = "samsung,exynos5250-dw-mshc";
888950b0 447 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 448 #address-cells = <1>;
449 #size-cells = <0>;
450 reg = <0x12210000 0x1000>;
451 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
452 clock-names = "biu", "ciu";
453 fifo-depth = <0x80>;
454 status = "disabled";
455 };
79989ba3 456
5d99cc59
KK		 457 mmc_2: mmc@12220000 {
458 compatible = "samsung,exynos5250-dw-mshc";
888950b0 459 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 460 #address-cells = <1>;
461 #size-cells = <0>;
462 reg = <0x12220000 0x1000>;
463 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
464 clock-names = "biu", "ciu";
465 fifo-depth = <0x80>;
466 status = "disabled";
467 };
84bd48a0 468
5d99cc59
KK		 469 mmc_3: mmc@12230000 {
470 compatible = "samsung,exynos5250-dw-mshc";
471 reg = <0x12230000 0x1000>;
888950b0 472 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 473 #address-cells = <1>;
474 #size-cells = <0>;
475 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
476 clock-names = "biu", "ciu";
477 fifo-depth = <0x80>;
478 status = "disabled";
479 };
84bd48a0 480
8dccafaa 481 i2s0: i2s@3830000 {
5d99cc59
KK		 482 compatible = "samsung,s5pv210-i2s";
483 status = "disabled";
484 reg = <0x03830000 0x100>;
485 dmas = <&pdma0 10
486 &pdma0 9
487 &pdma0 8>;
488 dma-names = "tx", "rx", "tx-sec";
489 clocks = <&clock_audss EXYNOS_I2S_BUS>,
490 <&clock_audss EXYNOS_I2S_BUS>,
491 <&clock_audss EXYNOS_SCLK_I2S>;
492 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
493 samsung,idma-addr = <0x03000000>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2s0_bus>;
496 };
84bd48a0 497
5d99cc59
KK		 498 i2s1: i2s@12D60000 {
499 compatible = "samsung,s3c6410-i2s";
500 status = "disabled";
501 reg = <0x12D60000 0x100>;
502 dmas = <&pdma1 12
503 &pdma1 11>;
504 dma-names = "tx", "rx";
505 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
506 clock-names = "iis", "i2s_opclk0";
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2s1_bus>;
509 };
84bd48a0 510
5d99cc59
KK		 511 i2s2: i2s@12D70000 {
512 compatible = "samsung,s3c6410-i2s";
513 status = "disabled";
514 reg = <0x12D70000 0x100>;
515 dmas = <&pdma0 12
516 &pdma0 11>;
517 dma-names = "tx", "rx";
518 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
519 clock-names = "iis", "i2s_opclk0";
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2s2_bus>;
522 };
4c4c7463 523
5d99cc59
KK		 524 usb_dwc3 {
525 compatible = "samsung,exynos5250-dwusb3";
526 clocks = <&clock CLK_USB3>;
527 clock-names = "usbdrd30";
528 #address-cells = <1>;
529 #size-cells = <1>;
530 ranges;
531
532 usbdrd_dwc3: dwc3@12000000 {
533 compatible = "synopsys,dwc3";
534 reg = <0x12000000 0x10000>;
888950b0 535 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 536 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
537 phy-names = "usb2-phy", "usb3-phy";
538 };
539 };
4c4c7463 540
5d99cc59
KK		 541 usbdrd_phy: phy@12100000 {
542 compatible = "samsung,exynos5250-usbdrd-phy";
543 reg = <0x12100000 0x100>;
544 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
545 clock-names = "phy", "ref";
546 samsung,pmu-syscon = <&pmu_system_controller>;
547 #phy-cells = <1>;
548 };
4c4c7463 549
5d99cc59
KK		 550 ehci: usb@12110000 {
551 compatible = "samsung,exynos4210-ehci";
552 reg = <0x12110000 0x100>;
888950b0 553 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0b3dc97e 554
5d99cc59
KK		 555 clocks = <&clock CLK_USB2>;
556 clock-names = "usbhost";
557 #address-cells = <1>;
558 #size-cells = <0>;
559 port@0 {
560 reg = <0>;
561 phys = <&usb2_phy_gen 1>;
562 };
896db3b3 563 };
517083f4 564
5d99cc59
KK		 565 ohci: usb@12120000 {
566 compatible = "samsung,exynos4210-ohci";
567 reg = <0x12120000 0x100>;
888950b0 568 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
b3cd7d87 569
5d99cc59
KK		 570 clocks = <&clock CLK_USB2>;
571 clock-names = "usbhost";
572 #address-cells = <1>;
573 #size-cells = <0>;
574 port@0 {
575 reg = <0>;
576 phys = <&usb2_phy_gen 1>;
577 };
dba2f058 578 };
13cbd1e3 579
5d99cc59
KK		 580 usb2_phy_gen: phy@12130000 {
581 compatible = "samsung,exynos5250-usb2-phy";
582 reg = <0x12130000 0x100>;
583 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
584 clock-names = "phy", "ref";
585 #phy-cells = <1>;
586 samsung,sysreg-phandle = <&sysreg_system_controller>;
587 samsung,pmureg-phandle = <&pmu_system_controller>;
588 };
b3cd7d87 589
5d99cc59
KK		 590 amba {
591 #address-cells = <1>;
592 #size-cells = <1>;
593 compatible = "simple-bus";
594 interrupt-parent = <&gic>;
595 ranges;
596
597 pdma0: pdma@121A0000 {
598 compatible = "arm,pl330", "arm,primecell";
599 reg = <0x121A0000 0x1000>;
888950b0 600 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 601 clocks = <&clock CLK_PDMA0>;
602 clock-names = "apb_pclk";
603 #dma-cells = <1>;
604 #dma-channels = <8>;
605 #dma-requests = <32>;
606 };
607
608 pdma1: pdma@121B0000 {
609 compatible = "arm,pl330", "arm,primecell";
610 reg = <0x121B0000 0x1000>;
888950b0 611 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 612 clocks = <&clock CLK_PDMA1>;
613 clock-names = "apb_pclk";
614 #dma-cells = <1>;
615 #dma-channels = <8>;
616 #dma-requests = <32>;
617 };
618
619 mdma0: mdma@10800000 {
620 compatible = "arm,pl330", "arm,primecell";
621 reg = <0x10800000 0x1000>;
888950b0 622 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 623 clocks = <&clock CLK_MDMA0>;
624 clock-names = "apb_pclk";
625 #dma-cells = <1>;
626 #dma-channels = <8>;
627 #dma-requests = <1>;
628 };
629
630 mdma1: mdma@11C10000 {
631 compatible = "arm,pl330", "arm,primecell";
632 reg = <0x11C10000 0x1000>;
888950b0 633 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 634 clocks = <&clock CLK_MDMA1>;
635 clock-names = "apb_pclk";
636 #dma-cells = <1>;
637 #dma-channels = <8>;
638 #dma-requests = <1>;
639 };
dba2f058 640 };
7d40d867 641
5d99cc59 642 gsc_0: gsc@13e00000 {
fee58abd 643 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
5d99cc59 644 reg = <0x13e00000 0x1000>;
888950b0 645 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 646 power-domains = <&pd_gsc>;
647 clocks = <&clock CLK_GSCL0>;
648 clock-names = "gscl";
304e262c 649 iommus = <&sysmmu_gsc0>;
5d99cc59 650 };
dba2f058 651
5d99cc59 652 gsc_1: gsc@13e10000 {
fee58abd 653 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
5d99cc59 654 reg = <0x13e10000 0x1000>;
888950b0 655 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 656 power-domains = <&pd_gsc>;
657 clocks = <&clock CLK_GSCL1>;
658 clock-names = "gscl";
304e262c 659 iommus = <&sysmmu_gsc1>;
b074abb7 660 };
b074abb7 661
5d99cc59 662 gsc_2: gsc@13e20000 {
fee58abd 663 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
5d99cc59 664 reg = <0x13e20000 0x1000>;
888950b0 665 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 666 power-domains = <&pd_gsc>;
667 clocks = <&clock CLK_GSCL2>;
668 clock-names = "gscl";
304e262c 669 iommus = <&sysmmu_gsc2>;
5d99cc59 670 };
1128658a 671
5d99cc59 672 gsc_3: gsc@13e30000 {
fee58abd 673 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
5d99cc59 674 reg = <0x13e30000 0x1000>;
888950b0 675 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 676 power-domains = <&pd_gsc>;
677 clocks = <&clock CLK_GSCL3>;
678 clock-names = "gscl";
304e262c 679 iommus = <&sysmmu_gsc3>;
5d99cc59 680 };
1128658a 681
5d99cc59
KK		 682 hdmi: hdmi@14530000 {
683 compatible = "samsung,exynos4212-hdmi";
684 reg = <0x14530000 0x70000>;
685 power-domains = <&pd_disp1>;
888950b0 686 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 687 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
688 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
689 <&clock CLK_MOUT_HDMI>;
690 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
691 "sclk_hdmiphy", "mout_hdmi";
692 samsung,syscon-phandle = <&pmu_system_controller>;
c55af083 693 phy = <&hdmiphy>;
e96849e3 694 status = "disabled";
5d99cc59 695 };
1128658a 696
5343b157
MS		 697 hdmicec: cec@101B0000 {
698 compatible = "samsung,s5p-cec";
699 reg = <0x101B0000 0x200>;
700 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&clock CLK_HDMI_CEC>;
702 clock-names = "hdmicec";
703 samsung,syscon-phandle = <&pmu_system_controller>;
704 hdmi-phandle = <&hdmi>;
705 pinctrl-names = "default";
706 pinctrl-0 = <&hdmi_cec>;
707 status = "disabled";
708 };
709
e96849e3 710 mixer: mixer@14450000 {
5d99cc59
KK		 711 compatible = "samsung,exynos5250-mixer";
712 reg = <0x14450000 0x10000>;
713 power-domains = <&pd_disp1>;
888950b0 714 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 715 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
716 <&clock CLK_SCLK_HDMI>;
717 clock-names = "mixer", "hdmi", "sclk_hdmi";
718 iommus = <&sysmmu_tv>;
e96849e3 719 status = "disabled";
5d99cc59 720 };
566cf8ee 721
5d99cc59
KK		 722 dp_phy: video-phy {
723 compatible = "samsung,exynos5250-dp-video-phy";
724 samsung,pmu-syscon = <&pmu_system_controller>;
725 #phy-cells = <0>;
726 };
5af0d8a3 727
5d99cc59
KK		 728 adc: adc@12D10000 {
729 compatible = "samsung,exynos-adc-v1";
730 reg = <0x12D10000 0x100>;
888950b0 731 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 732 clocks = <&clock CLK_ADC>;
733 clock-names = "adc";
734 #io-channel-cells = <1>;
735 io-channel-ranges;
736 samsung,syscon-phandle = <&pmu_system_controller>;
737 status = "disabled";
738 };
ad4aebe1 739
5d99cc59
KK		 740 sss@10830000 {
741 compatible = "samsung,exynos4210-secss";
742 reg = <0x10830000 0x300>;
888950b0 743 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
5d99cc59
KK		 744 clocks = <&clock CLK_SSS>;
745 clock-names = "secss";
746 };
77899d53 747
5d99cc59
KK		 748 sysmmu_g2d: sysmmu@10A60000 {
749 compatible = "samsung,exynos-sysmmu";
750 reg = <0x10A60000 0x1000>;
751 interrupt-parent = <&combiner>;
752 interrupts = <24 5>;
753 clock-names = "sysmmu", "master";
754 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
755 #iommu-cells = <0>;
756 };
183af252 757
5d99cc59
KK		 758 sysmmu_mfc_r: sysmmu@11200000 {
759 compatible = "samsung,exynos-sysmmu";
760 reg = <0x11200000 0x1000>;
761 interrupt-parent = <&combiner>;
762 interrupts = <6 2>;
763 power-domains = <&pd_mfc>;
764 clock-names = "sysmmu", "master";
765 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
766 #iommu-cells = <0>;
767 };
6cbfdd73 768
5d99cc59
KK		 769 sysmmu_mfc_l: sysmmu@11210000 {
770 compatible = "samsung,exynos-sysmmu";
771 reg = <0x11210000 0x1000>;
772 interrupt-parent = <&combiner>;
773 interrupts = <8 5>;
774 power-domains = <&pd_mfc>;
775 clock-names = "sysmmu", "master";
776 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
777 #iommu-cells = <0>;
778 };
6cbfdd73 779
5d99cc59
KK		 780 sysmmu_rotator: sysmmu@11D40000 {
781 compatible = "samsung,exynos-sysmmu";
782 reg = <0x11D40000 0x1000>;
783 interrupt-parent = <&combiner>;
784 interrupts = <4 0>;
785 clock-names = "sysmmu", "master";
786 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
787 #iommu-cells = <0>;
788 };
6cbfdd73 789
5d99cc59
KK		 790 sysmmu_jpeg: sysmmu@11F20000 {
791 compatible = "samsung,exynos-sysmmu";
792 reg = <0x11F20000 0x1000>;
793 interrupt-parent = <&combiner>;
794 interrupts = <4 2>;
795 power-domains = <&pd_gsc>;
796 clock-names = "sysmmu", "master";
797 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
798 #iommu-cells = <0>;
799 };
6cbfdd73 800
5d99cc59
KK		 801 sysmmu_fimc_isp: sysmmu@13260000 {
802 compatible = "samsung,exynos-sysmmu";
803 reg = <0x13260000 0x1000>;
804 interrupt-parent = <&combiner>;
805 interrupts = <10 6>;
806 clock-names = "sysmmu";
807 clocks = <&clock CLK_SMMU_FIMC_ISP>;
808 #iommu-cells = <0>;
809 };
6cbfdd73 810
5d99cc59
KK		 811 sysmmu_fimc_drc: sysmmu@13270000 {
812 compatible = "samsung,exynos-sysmmu";
813 reg = <0x13270000 0x1000>;
814 interrupt-parent = <&combiner>;
815 interrupts = <11 6>;
816 clock-names = "sysmmu";
817 clocks = <&clock CLK_SMMU_FIMC_DRC>;
818 #iommu-cells = <0>;
819 };
6cbfdd73 820
5d99cc59
KK		 821 sysmmu_fimc_fd: sysmmu@132A0000 {
822 compatible = "samsung,exynos-sysmmu";
823 reg = <0x132A0000 0x1000>;
824 interrupt-parent = <&combiner>;
825 interrupts = <5 0>;
826 clock-names = "sysmmu";
827 clocks = <&clock CLK_SMMU_FIMC_FD>;
828 #iommu-cells = <0>;
829 };
6cbfdd73 830
5d99cc59
KK		 831 sysmmu_fimc_scc: sysmmu@13280000 {
832 compatible = "samsung,exynos-sysmmu";
833 reg = <0x13280000 0x1000>;
834 interrupt-parent = <&combiner>;
835 interrupts = <5 2>;
836 clock-names = "sysmmu";
837 clocks = <&clock CLK_SMMU_FIMC_SCC>;
838 #iommu-cells = <0>;
839 };
6cbfdd73 840
5d99cc59
KK		 841 sysmmu_fimc_scp: sysmmu@13290000 {
842 compatible = "samsung,exynos-sysmmu";
843 reg = <0x13290000 0x1000>;
844 interrupt-parent = <&combiner>;
845 interrupts = <3 6>;
846 clock-names = "sysmmu";
847 clocks = <&clock CLK_SMMU_FIMC_SCP>;
848 #iommu-cells = <0>;
849 };
6cbfdd73 850
5d99cc59
KK		 851 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
852 compatible = "samsung,exynos-sysmmu";
853 reg = <0x132B0000 0x1000>;
854 interrupt-parent = <&combiner>;
855 interrupts = <5 4>;
856 clock-names = "sysmmu";
857 clocks = <&clock CLK_SMMU_FIMC_MCU>;
858 #iommu-cells = <0>;
859 };
6cbfdd73 860
5d99cc59
KK		 861 sysmmu_fimc_odc: sysmmu@132C0000 {
862 compatible = "samsung,exynos-sysmmu";
863 reg = <0x132C0000 0x1000>;
864 interrupt-parent = <&combiner>;
865 interrupts = <11 0>;
866 clock-names = "sysmmu";
867 clocks = <&clock CLK_SMMU_FIMC_ODC>;
868 #iommu-cells = <0>;
869 };
6cbfdd73 870
5d99cc59
KK		 871 sysmmu_fimc_dis0: sysmmu@132D0000 {
872 compatible = "samsung,exynos-sysmmu";
873 reg = <0x132D0000 0x1000>;
874 interrupt-parent = <&combiner>;
875 interrupts = <10 4>;
876 clock-names = "sysmmu";
877 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
878 #iommu-cells = <0>;
879 };
6cbfdd73 880
5d99cc59
KK		 881 sysmmu_fimc_dis1: sysmmu@132E0000{
882 compatible = "samsung,exynos-sysmmu";
883 reg = <0x132E0000 0x1000>;
884 interrupt-parent = <&combiner>;
885 interrupts = <9 4>;
886 clock-names = "sysmmu";
887 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
888 #iommu-cells = <0>;
889 };
6cbfdd73 890
5d99cc59
KK		 891 sysmmu_fimc_3dnr: sysmmu@132F0000 {
892 compatible = "samsung,exynos-sysmmu";
893 reg = <0x132F0000 0x1000>;
894 interrupt-parent = <&combiner>;
895 interrupts = <5 6>;
896 clock-names = "sysmmu";
897 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
898 #iommu-cells = <0>;
899 };
6cbfdd73 900
5d99cc59
KK		 901 sysmmu_fimc_lite0: sysmmu@13C40000 {
902 compatible = "samsung,exynos-sysmmu";
903 reg = <0x13C40000 0x1000>;
904 interrupt-parent = <&combiner>;
905 interrupts = <3 4>;
906 power-domains = <&pd_gsc>;
907 clock-names = "sysmmu", "master";
908 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
909 #iommu-cells = <0>;
910 };
6cbfdd73 911
5d99cc59
KK		 912 sysmmu_fimc_lite1: sysmmu@13C50000 {
913 compatible = "samsung,exynos-sysmmu";
914 reg = <0x13C50000 0x1000>;
915 interrupt-parent = <&combiner>;
916 interrupts = <24 1>;
917 power-domains = <&pd_gsc>;
918 clock-names = "sysmmu", "master";
919 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
920 #iommu-cells = <0>;
921 };
6cbfdd73 922
5d99cc59
KK		 923 sysmmu_gsc0: sysmmu@13E80000 {
924 compatible = "samsung,exynos-sysmmu";
925 reg = <0x13E80000 0x1000>;
926 interrupt-parent = <&combiner>;
927 interrupts = <2 0>;
928 power-domains = <&pd_gsc>;
929 clock-names = "sysmmu", "master";
930 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
931 #iommu-cells = <0>;
932 };
6cbfdd73 933
5d99cc59
KK		 934 sysmmu_gsc1: sysmmu@13E90000 {
935 compatible = "samsung,exynos-sysmmu";
936 reg = <0x13E90000 0x1000>;
937 interrupt-parent = <&combiner>;
938 interrupts = <2 2>;
939 power-domains = <&pd_gsc>;
940 clock-names = "sysmmu", "master";
941 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
942 #iommu-cells = <0>;
943 };
6cbfdd73 944
5d99cc59
KK		 945 sysmmu_gsc2: sysmmu@13EA0000 {
946 compatible = "samsung,exynos-sysmmu";
947 reg = <0x13EA0000 0x1000>;
948 interrupt-parent = <&combiner>;
949 interrupts = <2 4>;
950 power-domains = <&pd_gsc>;
951 clock-names = "sysmmu", "master";
952 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
953 #iommu-cells = <0>;
954 };
6cbfdd73 955
5d99cc59
KK		 956 sysmmu_gsc3: sysmmu@13EB0000 {
957 compatible = "samsung,exynos-sysmmu";
958 reg = <0x13EB0000 0x1000>;
959 interrupt-parent = <&combiner>;
960 interrupts = <2 6>;
961 power-domains = <&pd_gsc>;
962 clock-names = "sysmmu", "master";
963 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
964 #iommu-cells = <0>;
965 };
6cbfdd73 966
5d99cc59
KK		 967 sysmmu_fimd1: sysmmu@14640000 {
968 compatible = "samsung,exynos-sysmmu";
969 reg = <0x14640000 0x1000>;
970 interrupt-parent = <&combiner>;
971 interrupts = <3 2>;
972 power-domains = <&pd_disp1>;
973 clock-names = "sysmmu", "master";
974 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
975 #iommu-cells = <0>;
976 };
6cbfdd73 977
5d99cc59
KK		 978 sysmmu_tv: sysmmu@14650000 {
979 compatible = "samsung,exynos-sysmmu";
980 reg = <0x14650000 0x1000>;
981 interrupt-parent = <&combiner>;
982 interrupts = <7 4>;
983 power-domains = <&pd_disp1>;
984 clock-names = "sysmmu", "master";
985 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
986 #iommu-cells = <0>;
987 };
6cbfdd73
MS		 988 };
989
5d99cc59
KK		 990 thermal-zones {
991 cpu_thermal: cpu-thermal {
992 polling-delay-passive = <0>;
993 polling-delay = <0>;
994 thermal-sensors = <&tmu 0>;
6cbfdd73 995
5d99cc59
KK		 996 cooling-maps {
997 map0 {
998 /* Corresponds to 800MHz at freq_table */
999 cooling-device = <&cpu0 9 9>;
1000 };
1001 map1 {
1002 /* Corresponds to 200MHz at freq_table */
1003 cooling-device = <&cpu0 15 15>;
1004 };
1005 };
1006 };
6cbfdd73 1007 };
b074abb7 1008};
e9a2f409
KK		 1009
1010&dp {
1011 power-domains = <&pd_disp1>;
1012 clocks = <&clock CLK_DP>;
1013 clock-names = "dp";
1014 phys = <&dp_phy>;
1015 phy-names = "dp";
1016};
1017
1018&fimd {
1019 power-domains = <&pd_disp1>;
1020 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1021 clock-names = "sclk_fimd", "fimd";
6cbfdd73 1022 iommus = <&sysmmu_fimd1>;
e9a2f409
KK		 1023};
1024
5a124fe0
KK		 1025&i2c_0 {
1026 clocks = <&clock CLK_I2C0>;
1027 clock-names = "i2c";
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&i2c0_bus>;
1030};
1031
1032&i2c_1 {
1033 clocks = <&clock CLK_I2C1>;
1034 clock-names = "i2c";
1035 pinctrl-names = "default";
1036 pinctrl-0 = <&i2c1_bus>;
1037};
1038
1039&i2c_2 {
1040 clocks = <&clock CLK_I2C2>;
1041 clock-names = "i2c";
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&i2c2_bus>;
1044};
1045
1046&i2c_3 {
1047 clocks = <&clock CLK_I2C3>;
1048 clock-names = "i2c";
1049 pinctrl-names = "default";
1050 pinctrl-0 = <&i2c3_bus>;
1051};
1052
1053&pwm {
1054 clocks = <&clock CLK_PWM>;
1055 clock-names = "timers";
1056};
1057
e9a2f409
KK		 1058&rtc {
1059 clocks = <&clock CLK_RTC>;
1060 clock-names = "rtc";
1061 interrupt-parent = <&pmu_system_controller>;
1062 status = "disabled";
1063};
1064
1065&serial_0 {
1066 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1067 clock-names = "uart", "clk_uart_baud0";
3590312f
MS		 1068 dmas = <&pdma0 13>, <&pdma0 14>;
1069 dma-names = "rx", "tx";
e9a2f409
KK		 1070};
1071
1072&serial_1 {
1073 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1074 clock-names = "uart", "clk_uart_baud0";
3590312f
MS		 1075 dmas = <&pdma1 15>, <&pdma1 16>;
1076 dma-names = "rx", "tx";
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KK		 1077};
1078
1079&serial_2 {
1080 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1081 clock-names = "uart", "clk_uart_baud0";
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MS		 1082 dmas = <&pdma0 15>, <&pdma0 16>;
1083 dma-names = "rx", "tx";
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KK		 1084};
1085
1086&serial_3 {
1087 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1088 clock-names = "uart", "clk_uart_baud0";
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MS		 1089 dmas = <&pdma1 17>, <&pdma1 18>;
1090 dma-names = "rx", "tx";
e9a2f409 1091};
dc561797
JMC		 1092
1093#include "exynos5250-pinctrl.dtsi"
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