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ARM: dts: exynos: Remove "cooling-{min|max}-level" for CPU nodes
authorViresh Kumar <viresh.kumar@linaro.org>
Fri, 9 Feb 2018 08:58:01 +0000 (14:28 +0530)
committerJuerg Haefliger <juergh@canonical.com>
Wed, 24 Jul 2019 01:57:02 +0000 (19:57 -0600)
BugLink: https://bugs.launchpad.net/bugs/1836802
commit cd6f55457eb449a388e793abd676e3a5b73510bc upstream.

The "cooling-min-level" and "cooling-max-level" properties are not
parsed by any part of the kernel currently and the max cooling state of
a CPU cooling device is found by referring to the cpufreq table instead.

Remove the unused properties from the CPU nodes.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Andrea Righi <andrea.righi@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>
arch/arm/boot/dts/exynos4210.dtsi patch | blob | blame | history
arch/arm/boot/dts/exynos4412.dtsi patch | blob | blame | history
arch/arm/boot/dts/exynos5250.dtsi patch | blob | blame | history
arch/arm/boot/dts/exynos5420-cpus.dtsi patch | blob | blame | history
arch/arm/boot/dts/exynos5422-cpus.dtsi patch | blob | blame | history

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 03dd61f6480955e657ea3b53e043c2fa4735770b..a33666d87c1706485b9a1acad74bb6448134ce66 100644 (file)
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -52,8 +52,6 @@
                                400000  975000
                                200000  950000
                        >;
-                       cooling-min-level = <4>;
-                       cooling-max-level = <2>;
                        #cooling-cells = <2>; /* min followed by max */
                };
 
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index b255ac55b1c1ea11c375f64723eb3dc1a1a8ccd4..9f16bde98911ed61870ae8513c449330dc4ffe12 100644 (file)
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -45,8 +45,6 @@
                        clocks = <&clock CLK_ARM_CLK>;
                        clock-names = "cpu";
                        operating-points-v2 = <&cpu0_opp_table>;
-                       cooling-min-level = <13>;
-                       cooling-max-level = <7>;
                        #cooling-cells = <2>; /* min followed by max */
                };
 
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 358fb4329487101a2d683ad23066de8cac35e7a9..3028843cb05266a30679ec28fd67b050b6b4617e 100644 (file)
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -80,8 +80,6 @@
                                 300000  937500
                                 200000  925000
                        >;
-                       cooling-min-level = <15>;
-                       cooling-max-level = <9>;
                        #cooling-cells = <2>; /* min followed by max */
                };
                cpu@1 {
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index d7d703aa1699ded9804162b2ed1b089fd625acec..7a41b225c1a8175eaba80f44ef36872600860363 100644 (file)
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -33,8 +33,6 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <11>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <1024>;
                };
@@ -46,8 +44,6 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <11>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <1024>;
                };
@@ -59,8 +55,6 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <11>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <1024>;
                };
@@ -72,8 +66,6 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <11>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <1024>;
                };
@@ -86,8 +78,6 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <7>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <539>;
                };
@@ -99,8 +89,6 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <7>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <539>;
                };
@@ -112,8 +100,6 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <7>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <539>;
                };
@@ -125,8 +111,6 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <7>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <539>;
                };
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index ec01d8020c2da99a1096514a93bbaadea14a03af..1ef8464af7c7f847c1acc86062cfce34dec0a6b7 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -32,8 +32,6 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <11>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <539>;
                };
@@ -45,8 +43,6 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <11>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <539>;
                };
@@ -58,8 +54,6 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <11>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <539>;
                };
@@ -71,8 +65,6 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <11>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <539>;
                };
@@ -85,8 +77,6 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <15>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <1024>;
                };
@@ -98,8 +88,6 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <15>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <1024>;
                };
@@ -111,8 +99,6 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <15>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <1024>;
                };
@@ -124,8 +110,6 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <15>;
                        #cooling-cells = <2>; /* min followed by max */
                        capacity-dmips-mhz = <1024>;
                };
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