[mirror_ubuntu-disco-kernel.git] / arch / arm / kernel / head.S

/*
 *  linux/arch/arm/kernel/head.S
 *
 *  Copyright (C) 1994-2002 Russell King
 *  Copyright (c) 2003 ARM Limited
 *  All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  Kernel startup code for all 32-bit CPUs
 */
#include <linux/linkage.h>
#include <linux/init.h>

#include <asm/assembler.h>
#include <asm/domain.h>
#include <asm/ptrace.h>
#include <asm/asm-offsets.h>
#include <asm/memory.h>
#include <asm/thread_info.h>
#include <asm/system.h>

#if (PHYS_OFFSET & 0x001fffff)
#error "PHYS_OFFSET must be at an even 2MiB boundary!"
#endif

#define KERNEL_RAM_VADDR	(PAGE_OFFSET + TEXT_OFFSET)
#define KERNEL_RAM_PADDR	(PHYS_OFFSET + TEXT_OFFSET)

/*
 * swapper_pg_dir is the virtual address of the initial page table.
 * We place the page tables 16K below KERNEL_RAM_VADDR.  Therefore, we must
 * make sure that KERNEL_RAM_VADDR is correctly set.  Currently, we expect
 * the least significant 16 bits to be 0x8000, but we could probably
 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
 */
#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
#error KERNEL_RAM_VADDR must start at 0xXXXX8000
#endif

	.globl	swapper_pg_dir
	.equ	swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000

	.macro	pgtbl, rd
	ldr	\rd, =(KERNEL_RAM_PADDR - 0x4000)
	.endm

#ifdef CONFIG_XIP_KERNEL
#define TEXTADDR  XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
#else
#define TEXTADDR  KERNEL_RAM_VADDR
#endif

/*
 * Kernel startup entry point.
 * ---------------------------
 *
 * This is normally called from the decompressor code.  The requirements
 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
 * r1 = machine nr.
 *
 * This code is mostly position independent, so if you link the kernel at
 * 0xc0008000, you call this at __pa(0xc0008000).
 *
 * See linux/arch/arm/tools/mach-types for the complete list of machine
 * numbers for r1.
 *
 * We're trying to keep crap to a minimum; DO NOT add any machine specific
 * crap here - that's what the boot loader (or in extreme, well justified
 * circumstances, zImage) is for.
 */
	__INIT
	.type	stext, %function
ENTRY(stext)
	msr	cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
						@ and irqs disabled
	mrc	p15, 0, r9, c0, c0		@ get processor id
	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
	movs	r10, r5				@ invalid processor (r5=0)?
	beq	__error_p			@ yes, error 'p'
	bl	__lookup_machine_type		@ r5=machinfo
	movs	r8, r5				@ invalid machine (r5=0)?
	beq	__error_a			@ yes, error 'a'
	bl	__create_page_tables

	/*
	 * The following calls CPU specific code in a position independent
	 * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of
	 * xxx_proc_info structure selected by __lookup_machine_type
	 * above.  On return, the CPU will be ready for the MMU to be
	 * turned on, and r0 will hold the CPU control register value.
	 */
	ldr	r13, __switch_data		@ address to jump to after
						@ mmu has been enabled
	adr	lr, __enable_mmu		@ return (PIC) address
	add	pc, r10, #PROCINFO_INITFUNC

#if defined(CONFIG_SMP)
	.type   secondary_startup, #function
ENTRY(secondary_startup)
	/*
	 * Common entry point for secondary CPUs.
	 *
	 * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
	 * the processor type - there is no need to check the machine type
	 * as it has already been validated by the primary processor.
	 */
	msr	cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
	mrc	p15, 0, r9, c0, c0		@ get processor id
	bl	__lookup_processor_type
	movs	r10, r5				@ invalid processor?
	moveq	r0, #'p'			@ yes, error 'p'
	beq	__error

	/*
	 * Use the page tables supplied from  __cpu_up.
	 */
	adr	r4, __secondary_data
	ldmia	r4, {r5, r7, r13}		@ address to jump to after
	sub	r4, r4, r5			@ mmu has been enabled
	ldr	r4, [r7, r4]			@ get secondary_data.pgdir
	adr	lr, __enable_mmu		@ return address
	add	pc, r10, #PROCINFO_INITFUNC	@ initialise processor
						@ (return control reg)

	/*
	 * r6  = &secondary_data
	 */
ENTRY(__secondary_switched)
	ldr	sp, [r7, #4]			@ get secondary_data.stack
	mov	fp, #0
	b	secondary_start_kernel

	.type	__secondary_data, %object
__secondary_data:
	.long	.
	.long	secondary_data
	.long	__secondary_switched
#endif /* defined(CONFIG_SMP) */


/*
 * Setup common bits before finally enabling the MMU.  Essentially
 * this is just loading the page table pointer and domain access
 * registers.
 */
	.type	__enable_mmu, %function
__enable_mmu:
#ifdef CONFIG_ALIGNMENT_TRAP
	orr	r0, r0, #CR_A
#else
	bic	r0, r0, #CR_A
#endif
#ifdef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CR_C
#endif
#ifdef CONFIG_CPU_BPREDICT_DISABLE
	bic	r0, r0, #CR_Z
#endif
#ifdef CONFIG_CPU_ICACHE_DISABLE
	bic	r0, r0, #CR_I
#endif
	mov	r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
		      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
		      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
		      domain_val(DOMAIN_IO, DOMAIN_CLIENT))
	mcr	p15, 0, r5, c3, c0, 0		@ load domain access register
	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer
	b	__turn_mmu_on

/*
 * Enable the MMU.  This completely changes the structure of the visible
 * memory space.  You will not be able to trace execution through this.
 * If you have an enquiry about this, *please* check the linux-arm-kernel
 * mailing list archives BEFORE sending another post to the list.
 *
 *  r0  = cp#15 control register
 *  r13 = *virtual* address to jump to upon completion
 *
 * other registers depend on the function called upon completion
 */
	.align	5
	.type	__turn_mmu_on, %function
__turn_mmu_on:
	mov	r0, r0
	mcr	p15, 0, r0, c1, c0, 0		@ write control reg
	mrc	p15, 0, r3, c0, c0, 0		@ read id reg
	mov	r3, r3
	mov	r3, r3
	mov	pc, r13


/*
 * Setup the initial page tables.  We only setup the barest
 * amount which are required to get the kernel running, which
 * generally means mapping in the kernel code.
 *
 * r8  = machinfo
 * r9  = cpuid
 * r10 = procinfo
 *
 * Returns:
 *  r0, r3, r6, r7 corrupted
 *  r4 = physical page table address
 */
	.type	__create_page_tables, %function
__create_page_tables:
	pgtbl	r4				@ page table address

	/*
	 * Clear the 16K level 1 swapper page table
	 */
	mov	r0, r4
	mov	r3, #0
	add	r6, r0, #0x4000
1:	str	r3, [r0], #4
	str	r3, [r0], #4
	str	r3, [r0], #4
	str	r3, [r0], #4
	teq	r0, r6
	bne	1b

	ldr	r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags

	/*
	 * Create identity mapping for first MB of kernel to
	 * cater for the MMU enable.  This identity mapping
	 * will be removed by paging_init().  We use our current program
	 * counter to determine corresponding section base address.
	 */
	mov	r6, pc, lsr #20			@ start of kernel section
	orr	r3, r7, r6, lsl #20		@ flags + kernel base
	str	r3, [r4, r6, lsl #2]		@ identity mapping

	/*
	 * Now setup the pagetables for our kernel direct
	 * mapped region.
	 */
	add	r0, r4,  #(TEXTADDR & 0xff000000) >> 18	@ start of kernel
	str	r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!

	ldr	r6, =(_end - PAGE_OFFSET - 1)	@ r6 = number of sections
	mov	r6, r6, lsr #20			@ needed for kernel minus 1

1:	add	r3, r3, #1 << 20
	str	r3, [r0, #4]!
	subs	r6, r6, #1
	bgt	1b

	/*
	 * Then map first 1MB of ram in case it contains our boot params.
	 */
	add	r0, r4, #PAGE_OFFSET >> 18
	orr	r6, r7, #(PHYS_OFFSET & 0xff000000)
	orr	r6, r6, #(PHYS_OFFSET & 0x00e00000)
	str	r6, [r0]

#ifdef CONFIG_XIP_KERNEL
	/*
	 * Map some ram to cover our .data and .bss areas.
	 * Mapping 3MB should be plenty.
	 */
	sub	r3, r4, #PHYS_OFFSET
	mov	r3, r3, lsr #20
	add	r0, r0, r3, lsl #2
	add	r6, r6, r3, lsl #20
	str	r6, [r0], #4
	add	r6, r6, #(1 << 20)
	str	r6, [r0], #4
	add	r6, r6, #(1 << 20)
	str	r6, [r0]
#endif

#ifdef CONFIG_DEBUG_LL
	ldr	r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
	/*
	 * Map in IO space for serial debugging.
	 * This allows debug messages to be output
	 * via a serial console before paging_init.
	 */
	ldr	r3, [r8, #MACHINFO_PGOFFIO]
	add	r0, r4, r3
	rsb	r3, r3, #0x4000			@ PTRS_PER_PGD*sizeof(long)
	cmp	r3, #0x0800			@ limit to 512MB
	movhi	r3, #0x0800
	add	r6, r0, r3
	ldr	r3, [r8, #MACHINFO_PHYSIO]
	orr	r3, r3, r7
1:	str	r3, [r0], #4
	add	r3, r3, #1 << 20
	teq	r0, r6
	bne	1b
#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
	/*
	 * If we're using the NetWinder or CATS, we also need to map
	 * in the 16550-type serial port for the debug messages
	 */
	add	r0, r4, #0xff000000 >> 18
	orr	r3, r7, #0x7c000000
	str	r3, [r0]
#endif
#ifdef CONFIG_ARCH_RPC
	/*
	 * Map in screen at 0x02000000 & SCREEN2_BASE
	 * Similar reasons here - for debug.  This is
	 * only for Acorn RiscPC architectures.
	 */
	add	r0, r4, #0x02000000 >> 18
	orr	r3, r7, #0x02000000
	str	r3, [r0]
	add	r0, r4, #0xd8000000 >> 18
	str	r3, [r0]
#endif
#endif
	mov	pc, lr
	.ltorg

#include "head-common.S"
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/kernel/head.S
	3	*
	4	* Copyright (C) 1994-2002 Russell King
e65f38ed RK	5	* Copyright (c) 2003 ARM Limited
e65f38ed RK	6	* All Rights Reserved
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* Kernel startup code for all 32-bit CPUs
	13	*/
1da177e4 LT	14	#include <linux/linkage.h>
	15	#include <linux/init.h>
	16
	17	#include <asm/assembler.h>
	18	#include <asm/domain.h>
1da177e4	19	#include <asm/ptrace.h>
e6ae744d	20	#include <asm/asm-offsets.h>
f09b9979	21	#include <asm/memory.h>
4f7a1812	22	#include <asm/thread_info.h>
1da177e4 LT	23	#include <asm/system.h>
1da177e4 LT	24
d4e1c889 LW	25	#if (PHYS_OFFSET & 0x001fffff)
	26	#error "PHYS_OFFSET must be at an even 2MiB boundary!"
	27	#endif
	28
f06b97ff RK	29	#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
f06b97ff RK	30	#define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET)
9d4f13e5	31
1da177e4	32	/*
37d07b72	33	* swapper_pg_dir is the virtual address of the initial page table.
f06b97ff RK	34	* We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
f06b97ff RK	35	* make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
37d07b72	36	* the least significant 16 bits to be 0x8000, but we could probably
f06b97ff	37	* relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
1da177e4	38	*/
f06b97ff RK	39	#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
f06b97ff RK	40	#error KERNEL_RAM_VADDR must start at 0xXXXX8000
1da177e4 LT	41	#endif
	42
	43	.globl swapper_pg_dir
f06b97ff	44	.equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
1da177e4	45
37d07b72	46	.macro pgtbl, rd
f06b97ff	47	ldr \rd, =(KERNEL_RAM_PADDR - 0x4000)
1da177e4	48	.endm
1da177e4	49
37d07b72 NP	50	#ifdef CONFIG_XIP_KERNEL
	51	#define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
	52	#else
f06b97ff	53	#define TEXTADDR KERNEL_RAM_VADDR
1da177e4 LT	54	#endif
	55
	56	/*
	57	* Kernel startup entry point.
	58	* ---------------------------
	59	*
	60	* This is normally called from the decompressor code. The requirements
	61	* are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
	62	* r1 = machine nr.
	63	*
	64	* This code is mostly position independent, so if you link the kernel at
	65	* 0xc0008000, you call this at __pa(0xc0008000).
	66	*
	67	* See linux/arch/arm/tools/mach-types for the complete list of machine
	68	* numbers for r1.
	69	*
	70	* We're trying to keep crap to a minimum; DO NOT add any machine specific
	71	* crap here - that's what the boot loader (or in extreme, well justified
	72	* circumstances, zImage) is for.
	73	*/
	74	__INIT
	75	.type stext, %function
	76	ENTRY(stext)
801194e3	77	msr cpsr_c, #PSR_F_BIT \| PSR_I_BIT \| SVC_MODE @ ensure svc mode
1da177e4	78	@ and irqs disabled
0f44ba1d	79	mrc p15, 0, r9, c0, c0 @ get processor id
1da177e4 LT	80	bl __lookup_processor_type @ r5=procinfo r9=cpuid
1da177e4 LT	81	movs r10, r5 @ invalid processor (r5=0)?
3c0bdac3	82	beq __error_p @ yes, error 'p'
1da177e4 LT	83	bl __lookup_machine_type @ r5=machinfo
	84	movs r8, r5 @ invalid machine (r5=0)?
	85	beq __error_a @ yes, error 'a'
	86	bl __create_page_tables
	87
	88	/*
	89	* The following calls CPU specific code in a position independent
	90	* manner. See arch/arm/mm/proc-*.S for details. r10 = base of
	91	* xxx_proc_info structure selected by __lookup_machine_type
	92	* above. On return, the CPU will be ready for the MMU to be
	93	* turned on, and r0 will hold the CPU control register value.
	94	*/
	95	ldr r13, __switch_data @ address to jump to after
	96	@ mmu has been enabled
	97	adr lr, __enable_mmu @ return (PIC) address
	98	add pc, r10, #PROCINFO_INITFUNC
	99
e65f38ed RK	100	#if defined(CONFIG_SMP)
	101	.type secondary_startup, #function
	102	ENTRY(secondary_startup)
	103	/*
	104	* Common entry point for secondary CPUs.
	105	*
	106	* Ensure that we're in SVC mode, and IRQs are disabled. Lookup
	107	* the processor type - there is no need to check the machine type
	108	* as it has already been validated by the primary processor.
	109	*/
801194e3	110	msr cpsr_c, #PSR_F_BIT \| PSR_I_BIT \| SVC_MODE
0f44ba1d	111	mrc p15, 0, r9, c0, c0 @ get processor id
e65f38ed RK	112	bl __lookup_processor_type
	113	movs r10, r5 @ invalid processor?
	114	moveq r0, #'p' @ yes, error 'p'
	115	beq __error
	116
	117	/*
	118	* Use the page tables supplied from __cpu_up.
	119	*/
	120	adr r4, __secondary_data
34d92626	121	ldmia r4, {r5, r7, r13} @ address to jump to after
e65f38ed	122	sub r4, r4, r5 @ mmu has been enabled
34d92626	123	ldr r4, [r7, r4] @ get secondary_data.pgdir
e65f38ed	124	adr lr, __enable_mmu @ return address
90af774a	125	add pc, r10, #PROCINFO_INITFUNC @ initialise processor
e65f38ed RK	126	@ (return control reg)
	127
	128	/*
	129	* r6 = &secondary_data
	130	*/
	131	ENTRY(__secondary_switched)
34d92626	132	ldr sp, [r7, #4] @ get secondary_data.stack
e65f38ed RK	133	mov fp, #0
	134	b secondary_start_kernel
	135
	136	.type __secondary_data, %object
	137	__secondary_data:
	138	.long .
	139	.long secondary_data
	140	.long __secondary_switched
	141	#endif /* defined(CONFIG_SMP) */
	142
1da177e4 LT	143
	144
	145	/*
	146	* Setup common bits before finally enabling the MMU. Essentially
	147	* this is just loading the page table pointer and domain access
	148	* registers.
	149	*/
	150	.type __enable_mmu, %function
	151	__enable_mmu:
	152	#ifdef CONFIG_ALIGNMENT_TRAP
	153	orr r0, r0, #CR_A
	154	#else
	155	bic r0, r0, #CR_A
	156	#endif
	157	#ifdef CONFIG_CPU_DCACHE_DISABLE
	158	bic r0, r0, #CR_C
	159	#endif
	160	#ifdef CONFIG_CPU_BPREDICT_DISABLE
	161	bic r0, r0, #CR_Z
	162	#endif
	163	#ifdef CONFIG_CPU_ICACHE_DISABLE
	164	bic r0, r0, #CR_I
	165	#endif
	166	mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) \| \
	167	domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) \| \
	168	domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) \| \
	169	domain_val(DOMAIN_IO, DOMAIN_CLIENT))
	170	mcr p15, 0, r5, c3, c0, 0 @ load domain access register
	171	mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
	172	b __turn_mmu_on
	173
	174	/*
	175	* Enable the MMU. This completely changes the structure of the visible
	176	* memory space. You will not be able to trace execution through this.
	177	* If you have an enquiry about this, please check the linux-arm-kernel
	178	* mailing list archives BEFORE sending another post to the list.
	179	*
	180	* r0 = cp#15 control register
	181	* r13 = virtual address to jump to upon completion
	182	*
	183	* other registers depend on the function called upon completion
	184	*/
	185	.align 5
	186	.type __turn_mmu_on, %function
	187	__turn_mmu_on:
	188	mov r0, r0
	189	mcr p15, 0, r0, c1, c0, 0 @ write control reg
	190	mrc p15, 0, r3, c0, c0, 0 @ read id reg
	191	mov r3, r3
	192	mov r3, r3
	193	mov pc, r13
	194
	195
	196
	197	/*
	198	* Setup the initial page tables. We only setup the barest
	199	* amount which are required to get the kernel running, which
	200	* generally means mapping in the kernel code.
	201	*
	202	* r8 = machinfo
	203	* r9 = cpuid
	204	* r10 = procinfo
	205	*
	206	* Returns:
2df96b34	207	* r0, r3, r6, r7 corrupted
1da177e4 LT	208	* r4 = physical page table address
	209	*/
	210	.type __create_page_tables, %function
	211	__create_page_tables:
37d07b72	212	pgtbl r4 @ page table address
1da177e4 LT	213
	214	/*
	215	* Clear the 16K level 1 swapper page table
	216	*/
	217	mov r0, r4
	218	mov r3, #0
	219	add r6, r0, #0x4000
	220	1: str r3, [r0], #4
	221	str r3, [r0], #4
	222	str r3, [r0], #4
	223	str r3, [r0], #4
	224	teq r0, r6
	225	bne 1b
	226
8799ee9f	227	ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
1da177e4 LT	228
	229	/*
	230	* Create identity mapping for first MB of kernel to
	231	* cater for the MMU enable. This identity mapping
	232	* will be removed by paging_init(). We use our current program
	233	* counter to determine corresponding section base address.
	234	*/
	235	mov r6, pc, lsr #20 @ start of kernel section
	236	orr r3, r7, r6, lsl #20 @ flags + kernel base
	237	str r3, [r4, r6, lsl #2] @ identity mapping
	238
	239	/*
	240	* Now setup the pagetables for our kernel direct
2552fc27	241	* mapped region.
1da177e4 LT	242	*/
	243	add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
	244	str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
2552fc27 LB	245
	246	ldr r6, =(_end - PAGE_OFFSET - 1) @ r6 = number of sections
	247	mov r6, r6, lsr #20 @ needed for kernel minus 1
	248
	249	1: add r3, r3, #1 << 20
	250	str r3, [r0, #4]!
	251	subs r6, r6, #1
	252	bgt 1b
1da177e4 LT	253
	254	/*
	255	* Then map first 1MB of ram in case it contains our boot params.
	256	*/
f09b9979	257	add r0, r4, #PAGE_OFFSET >> 18
d4e1c889 LW	258	orr r6, r7, #(PHYS_OFFSET & 0xff000000)
d4e1c889 LW	259	orr r6, r6, #(PHYS_OFFSET & 0x00e00000)
1da177e4 LT	260	str r6, [r0]
	261
	262	#ifdef CONFIG_XIP_KERNEL
	263	/*
	264	* Map some ram to cover our .data and .bss areas.
	265	* Mapping 3MB should be plenty.
	266	*/
2df96b34	267	sub r3, r4, #PHYS_OFFSET
1da177e4 LT	268	mov r3, r3, lsr #20
	269	add r0, r0, r3, lsl #2
	270	add r6, r6, r3, lsl #20
	271	str r6, [r0], #4
	272	add r6, r6, #(1 << 20)
	273	str r6, [r0], #4
	274	add r6, r6, #(1 << 20)
	275	str r6, [r0]
	276	#endif
	277
c77b0427	278	#ifdef CONFIG_DEBUG_LL
8799ee9f	279	ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
1da177e4 LT	280	/*
	281	* Map in IO space for serial debugging.
	282	* This allows debug messages to be output
	283	* via a serial console before paging_init.
	284	*/
	285	ldr r3, [r8, #MACHINFO_PGOFFIO]
	286	add r0, r4, r3
	287	rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
	288	cmp r3, #0x0800 @ limit to 512MB
	289	movhi r3, #0x0800
	290	add r6, r0, r3
	291	ldr r3, [r8, #MACHINFO_PHYSIO]
	292	orr r3, r3, r7
	293	1: str r3, [r0], #4
	294	add r3, r3, #1 << 20
	295	teq r0, r6
	296	bne 1b
	297	#if defined(CONFIG_ARCH_NETWINDER) \|\| defined(CONFIG_ARCH_CATS)
	298	/*
3c0bdac3 RK	299	* If we're using the NetWinder or CATS, we also need to map
3c0bdac3 RK	300	* in the 16550-type serial port for the debug messages
1da177e4	301	*/
c77b0427 RK	302	add r0, r4, #0xff000000 >> 18
	303	orr r3, r7, #0x7c000000
	304	str r3, [r0]
1da177e4	305	#endif
1da177e4 LT	306	#ifdef CONFIG_ARCH_RPC
	307	/*
	308	* Map in screen at 0x02000000 & SCREEN2_BASE
	309	* Similar reasons here - for debug. This is
	310	* only for Acorn RiscPC architectures.
	311	*/
c77b0427 RK	312	add r0, r4, #0x02000000 >> 18
c77b0427 RK	313	orr r3, r7, #0x02000000
1da177e4	314	str r3, [r0]
c77b0427	315	add r0, r4, #0xd8000000 >> 18
1da177e4	316	str r3, [r0]
c77b0427	317	#endif
1da177e4 LT	318	#endif
	319	mov pc, lr
	320	.ltorg
	321
75d90832	322	#include "head-common.S"