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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/head.S | |
3 | * | |
4 | * Copyright (C) 1994-2002 Russell King | |
e65f38ed RK |
5 | * Copyright (c) 2003 ARM Limited |
6 | * All Rights Reserved | |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Kernel startup code for all 32-bit CPUs | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/linkage.h> |
15 | #include <linux/init.h> | |
16 | ||
17 | #include <asm/assembler.h> | |
18 | #include <asm/domain.h> | |
1da177e4 | 19 | #include <asm/ptrace.h> |
e6ae744d | 20 | #include <asm/asm-offsets.h> |
f09b9979 | 21 | #include <asm/memory.h> |
4f7a1812 | 22 | #include <asm/thread_info.h> |
1da177e4 LT |
23 | #include <asm/system.h> |
24 | ||
d4e1c889 LW |
25 | #if (PHYS_OFFSET & 0x001fffff) |
26 | #error "PHYS_OFFSET must be at an even 2MiB boundary!" | |
27 | #endif | |
28 | ||
f06b97ff RK |
29 | #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) |
30 | #define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET) | |
9d4f13e5 | 31 | |
9d20fdd5 | 32 | |
1da177e4 | 33 | /* |
37d07b72 | 34 | * swapper_pg_dir is the virtual address of the initial page table. |
f06b97ff RK |
35 | * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must |
36 | * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect | |
37d07b72 | 37 | * the least significant 16 bits to be 0x8000, but we could probably |
f06b97ff | 38 | * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. |
1da177e4 | 39 | */ |
f06b97ff RK |
40 | #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 |
41 | #error KERNEL_RAM_VADDR must start at 0xXXXX8000 | |
1da177e4 LT |
42 | #endif |
43 | ||
44 | .globl swapper_pg_dir | |
f06b97ff | 45 | .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 |
1da177e4 | 46 | |
37d07b72 | 47 | .macro pgtbl, rd |
f06b97ff | 48 | ldr \rd, =(KERNEL_RAM_PADDR - 0x4000) |
1da177e4 | 49 | .endm |
1da177e4 | 50 | |
37d07b72 | 51 | #ifdef CONFIG_XIP_KERNEL |
e98ff7f6 NP |
52 | #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) |
53 | #define KERNEL_END _edata_loc | |
37d07b72 | 54 | #else |
e98ff7f6 NP |
55 | #define KERNEL_START KERNEL_RAM_VADDR |
56 | #define KERNEL_END _end | |
1da177e4 LT |
57 | #endif |
58 | ||
59 | /* | |
60 | * Kernel startup entry point. | |
61 | * --------------------------- | |
62 | * | |
63 | * This is normally called from the decompressor code. The requirements | |
64 | * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, | |
9d20fdd5 | 65 | * r1 = machine nr, r2 = atags pointer. |
1da177e4 LT |
66 | * |
67 | * This code is mostly position independent, so if you link the kernel at | |
68 | * 0xc0008000, you call this at __pa(0xc0008000). | |
69 | * | |
70 | * See linux/arch/arm/tools/mach-types for the complete list of machine | |
71 | * numbers for r1. | |
72 | * | |
73 | * We're trying to keep crap to a minimum; DO NOT add any machine specific | |
74 | * crap here - that's what the boot loader (or in extreme, well justified | |
75 | * circumstances, zImage) is for. | |
76 | */ | |
2abc1c50 | 77 | __HEAD |
1da177e4 | 78 | ENTRY(stext) |
b86040a5 | 79 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode |
1da177e4 | 80 | @ and irqs disabled |
0f44ba1d | 81 | mrc p15, 0, r9, c0, c0 @ get processor id |
1da177e4 LT |
82 | bl __lookup_processor_type @ r5=procinfo r9=cpuid |
83 | movs r10, r5 @ invalid processor (r5=0)? | |
3c0bdac3 | 84 | beq __error_p @ yes, error 'p' |
1da177e4 LT |
85 | bl __lookup_machine_type @ r5=machinfo |
86 | movs r8, r5 @ invalid machine (r5=0)? | |
87 | beq __error_a @ yes, error 'a' | |
9d20fdd5 | 88 | bl __vet_atags |
1da177e4 LT |
89 | bl __create_page_tables |
90 | ||
91 | /* | |
92 | * The following calls CPU specific code in a position independent | |
93 | * manner. See arch/arm/mm/proc-*.S for details. r10 = base of | |
94 | * xxx_proc_info structure selected by __lookup_machine_type | |
95 | * above. On return, the CPU will be ready for the MMU to be | |
96 | * turned on, and r0 will hold the CPU control register value. | |
97 | */ | |
a4ae4134 | 98 | ldr r13, =__mmap_switched @ address to jump to after |
1da177e4 | 99 | @ mmu has been enabled |
b86040a5 CM |
100 | adr lr, BSYM(__enable_mmu) @ return (PIC) address |
101 | ARM( add pc, r10, #PROCINFO_INITFUNC ) | |
102 | THUMB( add r12, r10, #PROCINFO_INITFUNC ) | |
103 | THUMB( mov pc, r12 ) | |
93ed3970 | 104 | ENDPROC(stext) |
a4ae4134 | 105 | .ltorg |
1da177e4 | 106 | |
e65f38ed | 107 | #if defined(CONFIG_SMP) |
e65f38ed RK |
108 | ENTRY(secondary_startup) |
109 | /* | |
110 | * Common entry point for secondary CPUs. | |
111 | * | |
112 | * Ensure that we're in SVC mode, and IRQs are disabled. Lookup | |
113 | * the processor type - there is no need to check the machine type | |
114 | * as it has already been validated by the primary processor. | |
115 | */ | |
b86040a5 | 116 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 |
0f44ba1d | 117 | mrc p15, 0, r9, c0, c0 @ get processor id |
e65f38ed RK |
118 | bl __lookup_processor_type |
119 | movs r10, r5 @ invalid processor? | |
120 | moveq r0, #'p' @ yes, error 'p' | |
121 | beq __error | |
122 | ||
123 | /* | |
124 | * Use the page tables supplied from __cpu_up. | |
125 | */ | |
126 | adr r4, __secondary_data | |
b86040a5 | 127 | ldmia r4, {r5, r7, r12} @ address to jump to after |
e65f38ed | 128 | sub r4, r4, r5 @ mmu has been enabled |
34d92626 | 129 | ldr r4, [r7, r4] @ get secondary_data.pgdir |
b86040a5 CM |
130 | adr lr, BSYM(__enable_mmu) @ return address |
131 | mov r13, r12 @ __secondary_switched address | |
132 | ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor | |
133 | @ (return control reg) | |
134 | THUMB( add r12, r10, #PROCINFO_INITFUNC ) | |
135 | THUMB( mov pc, r12 ) | |
93ed3970 | 136 | ENDPROC(secondary_startup) |
e65f38ed RK |
137 | |
138 | /* | |
139 | * r6 = &secondary_data | |
140 | */ | |
141 | ENTRY(__secondary_switched) | |
34d92626 | 142 | ldr sp, [r7, #4] @ get secondary_data.stack |
e65f38ed RK |
143 | mov fp, #0 |
144 | b secondary_start_kernel | |
93ed3970 | 145 | ENDPROC(__secondary_switched) |
e65f38ed RK |
146 | |
147 | .type __secondary_data, %object | |
148 | __secondary_data: | |
149 | .long . | |
150 | .long secondary_data | |
151 | .long __secondary_switched | |
152 | #endif /* defined(CONFIG_SMP) */ | |
153 | ||
1da177e4 LT |
154 | |
155 | ||
156 | /* | |
157 | * Setup common bits before finally enabling the MMU. Essentially | |
158 | * this is just loading the page table pointer and domain access | |
159 | * registers. | |
160 | */ | |
1da177e4 LT |
161 | __enable_mmu: |
162 | #ifdef CONFIG_ALIGNMENT_TRAP | |
163 | orr r0, r0, #CR_A | |
164 | #else | |
165 | bic r0, r0, #CR_A | |
166 | #endif | |
167 | #ifdef CONFIG_CPU_DCACHE_DISABLE | |
168 | bic r0, r0, #CR_C | |
169 | #endif | |
170 | #ifdef CONFIG_CPU_BPREDICT_DISABLE | |
171 | bic r0, r0, #CR_Z | |
172 | #endif | |
173 | #ifdef CONFIG_CPU_ICACHE_DISABLE | |
174 | bic r0, r0, #CR_I | |
175 | #endif | |
176 | mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ | |
177 | domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ | |
178 | domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ | |
179 | domain_val(DOMAIN_IO, DOMAIN_CLIENT)) | |
180 | mcr p15, 0, r5, c3, c0, 0 @ load domain access register | |
181 | mcr p15, 0, r4, c2, c0, 0 @ load page table pointer | |
182 | b __turn_mmu_on | |
93ed3970 | 183 | ENDPROC(__enable_mmu) |
1da177e4 LT |
184 | |
185 | /* | |
186 | * Enable the MMU. This completely changes the structure of the visible | |
187 | * memory space. You will not be able to trace execution through this. | |
188 | * If you have an enquiry about this, *please* check the linux-arm-kernel | |
189 | * mailing list archives BEFORE sending another post to the list. | |
190 | * | |
191 | * r0 = cp#15 control register | |
192 | * r13 = *virtual* address to jump to upon completion | |
193 | * | |
194 | * other registers depend on the function called upon completion | |
195 | */ | |
196 | .align 5 | |
1da177e4 LT |
197 | __turn_mmu_on: |
198 | mov r0, r0 | |
199 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
200 | mrc p15, 0, r3, c0, c0, 0 @ read id reg | |
201 | mov r3, r3 | |
b86040a5 CM |
202 | mov r3, r13 |
203 | mov pc, r3 | |
93ed3970 | 204 | ENDPROC(__turn_mmu_on) |
1da177e4 LT |
205 | |
206 | ||
207 | /* | |
208 | * Setup the initial page tables. We only setup the barest | |
209 | * amount which are required to get the kernel running, which | |
210 | * generally means mapping in the kernel code. | |
211 | * | |
212 | * r8 = machinfo | |
213 | * r9 = cpuid | |
214 | * r10 = procinfo | |
215 | * | |
216 | * Returns: | |
2df96b34 | 217 | * r0, r3, r6, r7 corrupted |
1da177e4 LT |
218 | * r4 = physical page table address |
219 | */ | |
1da177e4 | 220 | __create_page_tables: |
37d07b72 | 221 | pgtbl r4 @ page table address |
1da177e4 LT |
222 | |
223 | /* | |
224 | * Clear the 16K level 1 swapper page table | |
225 | */ | |
226 | mov r0, r4 | |
227 | mov r3, #0 | |
228 | add r6, r0, #0x4000 | |
229 | 1: str r3, [r0], #4 | |
230 | str r3, [r0], #4 | |
231 | str r3, [r0], #4 | |
232 | str r3, [r0], #4 | |
233 | teq r0, r6 | |
234 | bne 1b | |
235 | ||
8799ee9f | 236 | ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags |
1da177e4 LT |
237 | |
238 | /* | |
239 | * Create identity mapping for first MB of kernel to | |
240 | * cater for the MMU enable. This identity mapping | |
241 | * will be removed by paging_init(). We use our current program | |
242 | * counter to determine corresponding section base address. | |
243 | */ | |
b86040a5 CM |
244 | mov r6, pc |
245 | mov r6, r6, lsr #20 @ start of kernel section | |
1da177e4 LT |
246 | orr r3, r7, r6, lsl #20 @ flags + kernel base |
247 | str r3, [r4, r6, lsl #2] @ identity mapping | |
248 | ||
249 | /* | |
250 | * Now setup the pagetables for our kernel direct | |
2552fc27 | 251 | * mapped region. |
1da177e4 | 252 | */ |
e98ff7f6 NP |
253 | add r0, r4, #(KERNEL_START & 0xff000000) >> 18 |
254 | str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! | |
255 | ldr r6, =(KERNEL_END - 1) | |
256 | add r0, r0, #4 | |
257 | add r6, r4, r6, lsr #18 | |
258 | 1: cmp r0, r6 | |
259 | add r3, r3, #1 << 20 | |
260 | strls r3, [r0], #4 | |
261 | bls 1b | |
1da177e4 | 262 | |
ec3622d9 NP |
263 | #ifdef CONFIG_XIP_KERNEL |
264 | /* | |
265 | * Map some ram to cover our .data and .bss areas. | |
266 | */ | |
267 | orr r3, r7, #(KERNEL_RAM_PADDR & 0xff000000) | |
40435792 | 268 | .if (KERNEL_RAM_PADDR & 0x00f00000) |
ec3622d9 | 269 | orr r3, r3, #(KERNEL_RAM_PADDR & 0x00f00000) |
40435792 | 270 | .endif |
ec3622d9 NP |
271 | add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18 |
272 | str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]! | |
273 | ldr r6, =(_end - 1) | |
274 | add r0, r0, #4 | |
275 | add r6, r4, r6, lsr #18 | |
276 | 1: cmp r0, r6 | |
277 | add r3, r3, #1 << 20 | |
278 | strls r3, [r0], #4 | |
279 | bls 1b | |
280 | #endif | |
281 | ||
1da177e4 LT |
282 | /* |
283 | * Then map first 1MB of ram in case it contains our boot params. | |
284 | */ | |
f09b9979 | 285 | add r0, r4, #PAGE_OFFSET >> 18 |
d4e1c889 | 286 | orr r6, r7, #(PHYS_OFFSET & 0xff000000) |
40435792 NP |
287 | .if (PHYS_OFFSET & 0x00f00000) |
288 | orr r6, r6, #(PHYS_OFFSET & 0x00f00000) | |
289 | .endif | |
1da177e4 LT |
290 | str r6, [r0] |
291 | ||
c77b0427 | 292 | #ifdef CONFIG_DEBUG_LL |
8799ee9f | 293 | ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags |
1da177e4 LT |
294 | /* |
295 | * Map in IO space for serial debugging. | |
296 | * This allows debug messages to be output | |
297 | * via a serial console before paging_init. | |
298 | */ | |
299 | ldr r3, [r8, #MACHINFO_PGOFFIO] | |
300 | add r0, r4, r3 | |
301 | rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) | |
302 | cmp r3, #0x0800 @ limit to 512MB | |
303 | movhi r3, #0x0800 | |
304 | add r6, r0, r3 | |
305 | ldr r3, [r8, #MACHINFO_PHYSIO] | |
306 | orr r3, r3, r7 | |
307 | 1: str r3, [r0], #4 | |
308 | add r3, r3, #1 << 20 | |
309 | teq r0, r6 | |
310 | bne 1b | |
311 | #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) | |
312 | /* | |
3c0bdac3 RK |
313 | * If we're using the NetWinder or CATS, we also need to map |
314 | * in the 16550-type serial port for the debug messages | |
1da177e4 | 315 | */ |
c77b0427 RK |
316 | add r0, r4, #0xff000000 >> 18 |
317 | orr r3, r7, #0x7c000000 | |
318 | str r3, [r0] | |
1da177e4 | 319 | #endif |
1da177e4 LT |
320 | #ifdef CONFIG_ARCH_RPC |
321 | /* | |
322 | * Map in screen at 0x02000000 & SCREEN2_BASE | |
323 | * Similar reasons here - for debug. This is | |
324 | * only for Acorn RiscPC architectures. | |
325 | */ | |
c77b0427 RK |
326 | add r0, r4, #0x02000000 >> 18 |
327 | orr r3, r7, #0x02000000 | |
1da177e4 | 328 | str r3, [r0] |
c77b0427 | 329 | add r0, r4, #0xd8000000 >> 18 |
1da177e4 | 330 | str r3, [r0] |
c77b0427 | 331 | #endif |
1da177e4 LT |
332 | #endif |
333 | mov pc, lr | |
93ed3970 | 334 | ENDPROC(__create_page_tables) |
1da177e4 LT |
335 | .ltorg |
336 | ||
75d90832 | 337 | #include "head-common.S" |