]> git.proxmox.com Git - mirror_ubuntu-disco-kernel.git/blame - arch/arm/kernel/smp.c
Merge tag 'for-linus-20190118' of git://git.kernel.dk/linux-block
[mirror_ubuntu-disco-kernel.git] / arch / arm / kernel / smp.c
CommitLineData
1da177e4
LT
1/*
2 * linux/arch/arm/kernel/smp.c
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
c97d4869 10#include <linux/module.h>
1da177e4
LT
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
68e21be2 14#include <linux/sched/mm.h>
ef8bd77f 15#include <linux/sched/hotplug.h>
68db0cf1 16#include <linux/sched/task_stack.h>
1da177e4
LT
17#include <linux/interrupt.h>
18#include <linux/cache.h>
19#include <linux/profile.h>
20#include <linux/errno.h>
21#include <linux/mm.h>
4e950f6f 22#include <linux/err.h>
1da177e4 23#include <linux/cpu.h>
1da177e4 24#include <linux/seq_file.h>
c97d4869 25#include <linux/irq.h>
96f0e003 26#include <linux/nmi.h>
bc28248e
RK
27#include <linux/percpu.h>
28#include <linux/clockchips.h>
3c030bea 29#include <linux/completion.h>
ec971ea5 30#include <linux/cpufreq.h>
bf18525f 31#include <linux/irq_work.h>
1da177e4 32
60063497 33#include <linux/atomic.h>
26602161 34#include <asm/bugs.h>
abcee5fb 35#include <asm/smp.h>
1da177e4
LT
36#include <asm/cacheflush.h>
37#include <asm/cpu.h>
42578c82 38#include <asm/cputype.h>
5a567d78 39#include <asm/exception.h>
8903826d 40#include <asm/idmap.h>
c9018aab 41#include <asm/topology.h>
e65f38ed
RK
42#include <asm/mmu_context.h>
43#include <asm/pgtable.h>
44#include <asm/pgalloc.h>
383fb3ee 45#include <asm/procinfo.h>
1da177e4 46#include <asm/processor.h>
37b05b63 47#include <asm/sections.h>
1da177e4
LT
48#include <asm/tlbflush.h>
49#include <asm/ptrace.h>
d6257288 50#include <asm/smp_plat.h>
4588c34d 51#include <asm/virt.h>
abcee5fb 52#include <asm/mach/arch.h>
eb08375e 53#include <asm/mpu.h>
1da177e4 54
365ec7b1
NP
55#define CREATE_TRACE_POINTS
56#include <trace/events/ipi.h>
57
e65f38ed
RK
58/*
59 * as from 2.5, kernels no longer have an init_tasks structure
60 * so we need some other way of telling a new secondary core
61 * where to place its SVC stack
62 */
63struct secondary_data secondary_data;
64
28e8e29c
MZ
65/*
66 * control for which core is the next to come out of the secondary
67 * boot "holding pen"
68 */
8bd26e3a 69volatile int pen_release = -1;
28e8e29c 70
1da177e4 71enum ipi_msg_type {
559a5939
SB
72 IPI_WAKEUP,
73 IPI_TIMER,
1da177e4
LT
74 IPI_RESCHEDULE,
75 IPI_CALL_FUNC,
76 IPI_CPU_STOP,
bf18525f 77 IPI_IRQ_WORK,
5135d875 78 IPI_COMPLETION,
e7273ff4
MZ
79 IPI_CPU_BACKTRACE,
80 /*
81 * SGI8-15 can be reserved by secure firmware, and thus may
82 * not be usable by the kernel. Please keep the above limited
83 * to at most 8 entries.
84 */
1da177e4
LT
85};
86
149c2415
RK
87static DECLARE_COMPLETION(cpu_running);
88
7619751f 89static struct smp_operations smp_ops __ro_after_init;
abcee5fb 90
4caa9dda 91void __init smp_set_ops(const struct smp_operations *ops)
abcee5fb
MZ
92{
93 if (ops)
94 smp_ops = *ops;
95};
96
4756dcbf
CC
97static unsigned long get_arch_pgd(pgd_t *pgd)
98{
b2c3e38a
RK
99#ifdef CONFIG_ARM_LPAE
100 return __phys_to_pfn(virt_to_phys(pgd));
101#else
102 return virt_to_phys(pgd);
103#endif
4756dcbf
CC
104}
105
383fb3ee
RK
106#if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR)
107static int secondary_biglittle_prepare(unsigned int cpu)
108{
109 if (!cpu_vtable[cpu])
110 cpu_vtable[cpu] = kzalloc(sizeof(*cpu_vtable[cpu]), GFP_KERNEL);
111
112 return cpu_vtable[cpu] ? 0 : -ENOMEM;
113}
114
115static void secondary_biglittle_init(void)
116{
117 init_proc_vtable(lookup_processor(read_cpuid_id())->proc);
118}
119#else
120static int secondary_biglittle_prepare(unsigned int cpu)
121{
122 return 0;
123}
124
125static void secondary_biglittle_init(void)
126{
127}
128#endif
129
8bd26e3a 130int __cpu_up(unsigned int cpu, struct task_struct *idle)
1da177e4 131{
1da177e4
LT
132 int ret;
133
084bb5bc
GU
134 if (!smp_ops.smp_boot_secondary)
135 return -ENOSYS;
136
383fb3ee
RK
137 ret = secondary_biglittle_prepare(cpu);
138 if (ret)
139 return ret;
140
e65f38ed
RK
141 /*
142 * We need to tell the secondary core where to find
143 * its stack and the page tables.
144 */
32d39a93 145 secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
eb08375e 146#ifdef CONFIG_ARM_MPU
a0995c08 147 secondary_data.mpu_rgn_info = &mpu_rgn_info;
eb08375e
JA
148#endif
149
c4a1f032 150#ifdef CONFIG_MMU
b2c3e38a 151 secondary_data.pgdir = virt_to_phys(idmap_pgd);
4756dcbf 152 secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
c4a1f032 153#endif
efcfc46e 154 sync_cache_w(&secondary_data);
e65f38ed 155
1da177e4
LT
156 /*
157 * Now bring the CPU into our world.
158 */
084bb5bc 159 ret = smp_ops.smp_boot_secondary(cpu, idle);
e65f38ed 160 if (ret == 0) {
e65f38ed
RK
161 /*
162 * CPU was successfully started, wait for it
163 * to come online or time out.
164 */
149c2415
RK
165 wait_for_completion_timeout(&cpu_running,
166 msecs_to_jiffies(1000));
e65f38ed 167
58613cd1
RK
168 if (!cpu_online(cpu)) {
169 pr_crit("CPU%u: failed to come online\n", cpu);
e65f38ed 170 ret = -EIO;
58613cd1
RK
171 }
172 } else {
173 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
e65f38ed
RK
174 }
175
e65f38ed 176
eb08375e 177 memset(&secondary_data, 0, sizeof(secondary_data));
1da177e4
LT
178 return ret;
179}
180
abcee5fb 181/* platform specific SMP operations */
ac6c7998 182void __init smp_init_cpus(void)
abcee5fb
MZ
183{
184 if (smp_ops.smp_init_cpus)
185 smp_ops.smp_init_cpus();
186}
187
fee3fd4f
GU
188int platform_can_secondary_boot(void)
189{
190 return !!smp_ops.smp_boot_secondary;
191}
192
2103f6cb
SW
193int platform_can_cpu_hotplug(void)
194{
195#ifdef CONFIG_HOTPLUG_CPU
196 if (smp_ops.cpu_kill)
197 return 1;
198#endif
199
200 return 0;
201}
202
a054a811 203#ifdef CONFIG_HOTPLUG_CPU
ac6c7998 204static int platform_cpu_kill(unsigned int cpu)
abcee5fb
MZ
205{
206 if (smp_ops.cpu_kill)
207 return smp_ops.cpu_kill(cpu);
208 return 1;
209}
210
ac6c7998 211static int platform_cpu_disable(unsigned int cpu)
abcee5fb
MZ
212{
213 if (smp_ops.cpu_disable)
214 return smp_ops.cpu_disable(cpu);
215
787047ee
SB
216 return 0;
217}
218
219int platform_can_hotplug_cpu(unsigned int cpu)
220{
221 /* cpu_die must be specified to support hotplug */
222 if (!smp_ops.cpu_die)
223 return 0;
224
225 if (smp_ops.cpu_can_disable)
226 return smp_ops.cpu_can_disable(cpu);
227
abcee5fb
MZ
228 /*
229 * By default, allow disabling all CPUs except the first one,
230 * since this is special on a lot of platforms, e.g. because
231 * of clock tick interrupts.
232 */
787047ee 233 return cpu != 0;
abcee5fb 234}
787047ee 235
a054a811
RK
236/*
237 * __cpu_disable runs on the processor to be shutdown.
238 */
8bd26e3a 239int __cpu_disable(void)
a054a811
RK
240{
241 unsigned int cpu = smp_processor_id();
a054a811
RK
242 int ret;
243
8e2a43f5 244 ret = platform_cpu_disable(cpu);
a054a811
RK
245 if (ret)
246 return ret;
247
248 /*
249 * Take this CPU offline. Once we clear this, we can't return,
250 * and we must not schedule until we're ready to give up the cpu.
251 */
e03cdade 252 set_cpu_online(cpu, false);
a054a811
RK
253
254 /*
255 * OK - migrate IRQs away from this CPU
256 */
257 migrate_irqs();
258
259 /*
260 * Flush user cache and TLB mappings, and then remove this CPU
261 * from the vm mask set of all processes.
e6b866e9
LP
262 *
263 * Caches are flushed to the Level of Unification Inner Shareable
264 * to write-back dirty lines to unified caches shared by all CPUs.
a054a811 265 */
e6b866e9 266 flush_cache_louis();
a054a811
RK
267 local_flush_tlb_all();
268
a054a811
RK
269 return 0;
270}
271
3c030bea
RK
272static DECLARE_COMPLETION(cpu_died);
273
a054a811
RK
274/*
275 * called on the thread which is asking for a CPU to be shutdown -
276 * waits until shutdown has completed, or it is timed out.
277 */
8bd26e3a 278void __cpu_die(unsigned int cpu)
a054a811 279{
3c030bea
RK
280 if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
281 pr_err("CPU%u: cpu didn't die\n", cpu);
282 return;
283 }
035e7875 284 pr_debug("CPU%u: shutdown\n", cpu);
3c030bea 285
98f1b5a7 286 clear_tasks_mm_cpumask(cpu);
51acdfd1
RK
287 /*
288 * platform_cpu_kill() is generally expected to do the powering off
289 * and/or cutting of clocks to the dying CPU. Optionally, this may
290 * be done by the CPU which is dying in preference to supporting
291 * this call, but that means there is _no_ synchronisation between
292 * the requesting CPU and the dying CPU actually losing power.
293 */
a054a811 294 if (!platform_cpu_kill(cpu))
4ed89f22 295 pr_err("CPU%u: unable to kill\n", cpu);
a054a811
RK
296}
297
298/*
299 * Called from the idle thread for the CPU which has been shutdown.
300 *
301 * Note that we disable IRQs here, but do not re-enable them
302 * before returning to the caller. This is also the behaviour
303 * of the other hotplug-cpu capable cores, so presumably coming
304 * out of idle fixes this.
305 */
9205b797 306void arch_cpu_idle_dead(void)
a054a811
RK
307{
308 unsigned int cpu = smp_processor_id();
309
a054a811
RK
310 idle_task_exit();
311
f36d3401 312 local_irq_disable();
f36d3401 313
51acdfd1
RK
314 /*
315 * Flush the data out of the L1 cache for this CPU. This must be
316 * before the completion to ensure that data is safely written out
317 * before platform_cpu_kill() gets called - which may disable
318 * *this* CPU and power down its cache.
319 */
320 flush_cache_louis();
321
322 /*
323 * Tell __cpu_die() that this CPU is now safe to dispose of. Once
324 * this returns, power and/or clocks can be removed at any point
325 * from this CPU and its cache by platform_cpu_kill().
326 */
aa033810 327 complete(&cpu_died);
3c030bea 328
a054a811 329 /*
51acdfd1
RK
330 * Ensure that the cache lines associated with that completion are
331 * written out. This covers the case where _this_ CPU is doing the
332 * powering down, to ensure that the completion is visible to the
333 * CPU waiting for this one.
334 */
335 flush_cache_louis();
336
337 /*
338 * The actual CPU shutdown procedure is at least platform (if not
339 * CPU) specific. This may remove power, or it may simply spin.
340 *
341 * Platforms are generally expected *NOT* to return from this call,
342 * although there are some which do because they have no way to
343 * power down the CPU. These platforms are the _only_ reason we
344 * have a return path which uses the fragment of assembly below.
345 *
346 * The return path should not be used for platforms which can
347 * power off the CPU.
a054a811 348 */
0a301110
RK
349 if (smp_ops.cpu_die)
350 smp_ops.cpu_die(cpu);
a054a811 351
668bc386
RK
352 pr_warn("CPU%u: smp_ops.cpu_die() returned, trying to resuscitate\n",
353 cpu);
354
a054a811
RK
355 /*
356 * Do not return to the idle loop - jump back to the secondary
357 * cpu initialisation. There's some initialisation which needs
358 * to be repeated to undo the effects of taking the CPU offline.
359 */
360 __asm__("mov sp, %0\n"
faabfa08 361 " mov fp, #0\n"
a054a811
RK
362 " b secondary_start_kernel"
363 :
32d39a93 364 : "r" (task_stack_page(current) + THREAD_SIZE - 8));
a054a811
RK
365}
366#endif /* CONFIG_HOTPLUG_CPU */
367
05c74a6c
RK
368/*
369 * Called by both boot and secondaries to move global data into
370 * per-processor storage.
371 */
8bd26e3a 372static void smp_store_cpu_info(unsigned int cpuid)
05c74a6c
RK
373{
374 struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
375
376 cpu_info->loops_per_jiffy = loops_per_jiffy;
e8d432c9 377 cpu_info->cpuid = read_cpuid_id();
c9018aab
VG
378
379 store_cpu_topology(cpuid);
05c74a6c
RK
380}
381
e65f38ed
RK
382/*
383 * This is the secondary CPU boot entry. We're using this CPUs
384 * idle thread stack, but a set of temporary page tables.
385 */
8bd26e3a 386asmlinkage void secondary_start_kernel(void)
e65f38ed
RK
387{
388 struct mm_struct *mm = &init_mm;
5f40b909
WD
389 unsigned int cpu;
390
383fb3ee
RK
391 secondary_biglittle_init();
392
5f40b909
WD
393 /*
394 * The identity mapping is uncached (strongly ordered), so
395 * switch away from it before attempting any exclusive accesses.
396 */
397 cpu_switch_mm(mm->pgd, mm);
89c7e4b8 398 local_flush_bp_all();
5f40b909
WD
399 enter_lazy_tlb(mm, current);
400 local_flush_tlb_all();
e65f38ed 401
e65f38ed
RK
402 /*
403 * All kernel threads share the same mm context; grab a
404 * reference and switch to it.
405 */
5f40b909 406 cpu = smp_processor_id();
f1f10076 407 mmgrab(mm);
e65f38ed 408 current->active_mm = mm;
56f8ba83 409 cpumask_set_cpu(cpu, mm_cpumask(mm));
e65f38ed 410
14318efb
RH
411 cpu_init();
412
62d1c95d
VM
413#ifndef CONFIG_MMU
414 setup_vectors_base();
415#endif
c68b0274 416 pr_debug("CPU%u: Booted secondary processor\n", cpu);
fde165b2 417
5bfb5d69 418 preempt_disable();
2c0136db 419 trace_hardirqs_off();
e65f38ed
RK
420
421 /*
422 * Give the platform a chance to do its own initialisation.
423 */
0a301110
RK
424 if (smp_ops.smp_secondary_init)
425 smp_ops.smp_secondary_init(cpu);
e65f38ed 426
e545a614 427 notify_cpu_starting(cpu);
a8655e83 428
e65f38ed
RK
429 calibrate_delay();
430
431 smp_store_cpu_info(cpu);
432
433 /*
573619d1
RK
434 * OK, now it's safe to let the boot CPU continue. Wait for
435 * the CPU migration code to notice that the CPU is online
149c2415 436 * before we continue - which happens after __cpu_up returns.
e65f38ed 437 */
e03cdade 438 set_cpu_online(cpu, true);
26602161
RK
439
440 check_other_bugs();
441
149c2415 442 complete(&cpu_running);
eb047454 443
eb047454
TG
444 local_irq_enable();
445 local_fiq_enable();
bbeb9209 446 local_abt_enable();
eb047454 447
e65f38ed
RK
448 /*
449 * OK, it's off to the idle thread for us
450 */
fc6d73d6 451 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
e65f38ed
RK
452}
453
1da177e4
LT
454void __init smp_cpus_done(unsigned int max_cpus)
455{
4bf9636c
PM
456 int cpu;
457 unsigned long bogosum = 0;
458
459 for_each_online_cpu(cpu)
460 bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
461
462 printk(KERN_INFO "SMP: Total of %d processors activated "
463 "(%lu.%02lu BogoMIPS).\n",
464 num_online_cpus(),
465 bogosum / (500000/HZ),
466 (bogosum / (5000/HZ)) % 100);
467
4588c34d 468 hyp_mode_check();
1da177e4
LT
469}
470
471void __init smp_prepare_boot_cpu(void)
472{
14318efb 473 set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
1da177e4
LT
474}
475
05c74a6c 476void __init smp_prepare_cpus(unsigned int max_cpus)
1da177e4 477{
05c74a6c 478 unsigned int ncores = num_possible_cpus();
1da177e4 479
c9018aab
VG
480 init_cpu_topology();
481
05c74a6c 482 smp_store_cpu_info(smp_processor_id());
1da177e4
LT
483
484 /*
05c74a6c 485 * are we trying to boot more cores than exist?
1da177e4 486 */
05c74a6c
RK
487 if (max_cpus > ncores)
488 max_cpus = ncores;
7fa22bd5 489 if (ncores > 1 && max_cpus) {
7fa22bd5
SB
490 /*
491 * Initialise the present map, which describes the set of CPUs
492 * actually populated at the present time. A platform should
0a301110
RK
493 * re-initialize the map in the platforms smp_prepare_cpus()
494 * if present != possible (e.g. physical hotplug).
7fa22bd5 495 */
0b5f9c00 496 init_cpu_present(cpu_possible_mask);
7fa22bd5 497
05c74a6c
RK
498 /*
499 * Initialise the SCU if there are more than one CPU
500 * and let them know where to start.
501 */
0a301110
RK
502 if (smp_ops.smp_prepare_cpus)
503 smp_ops.smp_prepare_cpus(max_cpus);
05c74a6c 504 }
1da177e4
LT
505}
506
365ec7b1 507static void (*__smp_cross_call)(const struct cpumask *, unsigned int);
0f7b332f
RK
508
509void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
510{
365ec7b1
NP
511 if (!__smp_cross_call)
512 __smp_cross_call = fn;
3e459990 513}
3e459990 514
365ec7b1 515static const char *ipi_types[NR_IPI] __tracepoint_string = {
559a5939
SB
516#define S(x,s) [x] = s
517 S(IPI_WAKEUP, "CPU wakeup interrupts"),
4a88abd7
RK
518 S(IPI_TIMER, "Timer broadcast interrupts"),
519 S(IPI_RESCHEDULE, "Rescheduling interrupts"),
520 S(IPI_CALL_FUNC, "Function call interrupts"),
4a88abd7 521 S(IPI_CPU_STOP, "CPU stop interrupts"),
bf18525f 522 S(IPI_IRQ_WORK, "IRQ work interrupts"),
5135d875 523 S(IPI_COMPLETION, "completion interrupts"),
4a88abd7
RK
524};
525
365ec7b1
NP
526static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
527{
7c64cc05 528 trace_ipi_raise_rcuidle(target, ipi_types[ipinr]);
365ec7b1
NP
529 __smp_cross_call(target, ipinr);
530}
531
f13cd417 532void show_ipi_list(struct seq_file *p, int prec)
1da177e4 533{
4a88abd7 534 unsigned int cpu, i;
1da177e4 535
4a88abd7
RK
536 for (i = 0; i < NR_IPI; i++) {
537 seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);
1da177e4 538
026b7c6b 539 for_each_online_cpu(cpu)
4a88abd7
RK
540 seq_printf(p, "%10u ",
541 __get_irq_stat(cpu, ipi_irqs[i]));
1da177e4 542
4a88abd7
RK
543 seq_printf(p, " %s\n", ipi_types[i]);
544 }
1da177e4
LT
545}
546
b54992fe 547u64 smp_irq_stat_cpu(unsigned int cpu)
37ee16ae 548{
b54992fe
RK
549 u64 sum = 0;
550 int i;
37ee16ae 551
b54992fe
RK
552 for (i = 0; i < NR_IPI; i++)
553 sum += __get_irq_stat(cpu, ipi_irqs[i]);
37ee16ae 554
b54992fe 555 return sum;
37ee16ae
RK
556}
557
365ec7b1
NP
558void arch_send_call_function_ipi_mask(const struct cpumask *mask)
559{
560 smp_cross_call(mask, IPI_CALL_FUNC);
561}
562
563void arch_send_wakeup_ipi_mask(const struct cpumask *mask)
564{
565 smp_cross_call(mask, IPI_WAKEUP);
566}
567
568void arch_send_call_function_single_ipi(int cpu)
569{
89d798b7 570 smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC);
365ec7b1
NP
571}
572
573#ifdef CONFIG_IRQ_WORK
574void arch_irq_work_raise(void)
575{
09f6edd4 576 if (arch_irq_work_has_interrupt())
365ec7b1
NP
577 smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
578}
579#endif
580
bc28248e 581#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
3d06770e 582void tick_broadcast(const struct cpumask *mask)
bc28248e 583{
e3fbb087 584 smp_cross_call(mask, IPI_TIMER);
bc28248e 585}
5388a6b2 586#endif
bc28248e 587
bd31b859 588static DEFINE_RAW_SPINLOCK(stop_lock);
1da177e4
LT
589
590/*
591 * ipi_cpu_stop - handle IPI from smp_send_stop()
592 */
593static void ipi_cpu_stop(unsigned int cpu)
594{
5976a669 595 if (system_state <= SYSTEM_RUNNING) {
bd31b859 596 raw_spin_lock(&stop_lock);
4ed89f22 597 pr_crit("CPU%u: stopping\n", cpu);
3d3f78d7 598 dump_stack();
bd31b859 599 raw_spin_unlock(&stop_lock);
3d3f78d7 600 }
1da177e4 601
e03cdade 602 set_cpu_online(cpu, false);
1da177e4
LT
603
604 local_fiq_disable();
605 local_irq_disable();
606
607 while (1)
608 cpu_relax();
609}
610
5135d875
NP
611static DEFINE_PER_CPU(struct completion *, cpu_completion);
612
613int register_ipi_completion(struct completion *completion, int cpu)
614{
615 per_cpu(cpu_completion, cpu) = completion;
616 return IPI_COMPLETION;
617}
618
619static void ipi_complete(unsigned int cpu)
620{
621 complete(per_cpu(cpu_completion, cpu));
622}
623
1da177e4
LT
624/*
625 * Main handler for inter-processor interrupts
1da177e4 626 */
4073723a 627asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs)
0b5a1b95
SG
628{
629 handle_IPI(ipinr, regs);
630}
631
632void handle_IPI(int ipinr, struct pt_regs *regs)
1da177e4
LT
633{
634 unsigned int cpu = smp_processor_id();
c97d4869 635 struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 636
365ec7b1 637 if ((unsigned)ipinr < NR_IPI) {
398f7456 638 trace_ipi_entry_rcuidle(ipi_types[ipinr]);
559a5939 639 __inc_irq_stat(cpu, ipi_irqs[ipinr]);
365ec7b1 640 }
1da177e4 641
24480d98 642 switch (ipinr) {
559a5939
SB
643 case IPI_WAKEUP:
644 break;
645
e2c50119 646#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
24480d98 647 case IPI_TIMER:
7deabca0 648 irq_enter();
e2c50119 649 tick_receive_broadcast();
7deabca0 650 irq_exit();
24480d98 651 break;
e2c50119 652#endif
1da177e4 653
24480d98 654 case IPI_RESCHEDULE:
184748cc 655 scheduler_ipi();
24480d98 656 break;
1da177e4 657
24480d98 658 case IPI_CALL_FUNC:
7deabca0 659 irq_enter();
24480d98 660 generic_smp_call_function_interrupt();
7deabca0 661 irq_exit();
24480d98 662 break;
1da177e4 663
24480d98 664 case IPI_CPU_STOP:
7deabca0 665 irq_enter();
24480d98 666 ipi_cpu_stop(cpu);
7deabca0 667 irq_exit();
24480d98 668 break;
1da177e4 669
bf18525f
SB
670#ifdef CONFIG_IRQ_WORK
671 case IPI_IRQ_WORK:
672 irq_enter();
673 irq_work_run();
674 irq_exit();
675 break;
676#endif
677
5135d875
NP
678 case IPI_COMPLETION:
679 irq_enter();
680 ipi_complete(cpu);
681 irq_exit();
682 break;
683
96f0e003 684 case IPI_CPU_BACKTRACE:
42a0bb3f 685 printk_nmi_enter();
96f0e003
RK
686 irq_enter();
687 nmi_cpu_backtrace(regs);
688 irq_exit();
42a0bb3f 689 printk_nmi_exit();
96f0e003
RK
690 break;
691
24480d98 692 default:
4ed89f22
RK
693 pr_crit("CPU%u: Unknown IPI message 0x%x\n",
694 cpu, ipinr);
24480d98 695 break;
1da177e4 696 }
365ec7b1
NP
697
698 if ((unsigned)ipinr < NR_IPI)
398f7456 699 trace_ipi_exit_rcuidle(ipi_types[ipinr]);
c97d4869 700 set_irq_regs(old_regs);
1da177e4
LT
701}
702
703void smp_send_reschedule(int cpu)
704{
e3fbb087 705 smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
1da177e4
LT
706}
707
1da177e4
LT
708void smp_send_stop(void)
709{
28e18293 710 unsigned long timeout;
6fa99b7f 711 struct cpumask mask;
1da177e4 712
6fa99b7f
WD
713 cpumask_copy(&mask, cpu_online_mask);
714 cpumask_clear_cpu(smp_processor_id(), &mask);
c5dff4ff
JMC
715 if (!cpumask_empty(&mask))
716 smp_cross_call(&mask, IPI_CPU_STOP);
4b0ef3b1 717
28e18293
RK
718 /* Wait up to one second for other CPUs to stop */
719 timeout = USEC_PER_SEC;
720 while (num_online_cpus() > 1 && timeout--)
721 udelay(1);
4b0ef3b1 722
28e18293 723 if (num_online_cpus() > 1)
8b521cb2 724 pr_warn("SMP: failed to stop secondary CPUs\n");
4b0ef3b1
RK
725}
726
82c08c3e
YW
727/* In case panic() and panic() called at the same time on CPU1 and CPU2,
728 * and CPU 1 calls panic_smp_self_stop() before crash_smp_send_stop()
729 * CPU1 can't receive the ipi irqs from CPU2, CPU1 will be always online,
730 * kdump fails. So split out the panic_smp_self_stop() and add
731 * set_cpu_online(smp_processor_id(), false).
732 */
733void panic_smp_self_stop(void)
734{
735 pr_debug("CPU %u will stop doing anything useful since another CPU has paniced\n",
736 smp_processor_id());
737 set_cpu_online(smp_processor_id(), false);
738 while (1)
739 cpu_relax();
740}
741
4b0ef3b1 742/*
1da177e4 743 * not supported here
4b0ef3b1 744 */
5048bcba 745int setup_profiling_timer(unsigned int multiplier)
4b0ef3b1 746{
1da177e4 747 return -EINVAL;
4b0ef3b1 748}
ec971ea5
RZ
749
750#ifdef CONFIG_CPU_FREQ
751
752static DEFINE_PER_CPU(unsigned long, l_p_j_ref);
753static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq);
754static unsigned long global_l_p_j_ref;
755static unsigned long global_l_p_j_ref_freq;
756
757static int cpufreq_callback(struct notifier_block *nb,
758 unsigned long val, void *data)
759{
760 struct cpufreq_freqs *freq = data;
761 int cpu = freq->cpu;
762
763 if (freq->flags & CPUFREQ_CONST_LOOPS)
764 return NOTIFY_OK;
765
766 if (!per_cpu(l_p_j_ref, cpu)) {
767 per_cpu(l_p_j_ref, cpu) =
768 per_cpu(cpu_data, cpu).loops_per_jiffy;
769 per_cpu(l_p_j_ref_freq, cpu) = freq->old;
770 if (!global_l_p_j_ref) {
771 global_l_p_j_ref = loops_per_jiffy;
772 global_l_p_j_ref_freq = freq->old;
773 }
774 }
775
776 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
0b443ead 777 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
ec971ea5
RZ
778 loops_per_jiffy = cpufreq_scale(global_l_p_j_ref,
779 global_l_p_j_ref_freq,
780 freq->new);
781 per_cpu(cpu_data, cpu).loops_per_jiffy =
782 cpufreq_scale(per_cpu(l_p_j_ref, cpu),
783 per_cpu(l_p_j_ref_freq, cpu),
784 freq->new);
785 }
786 return NOTIFY_OK;
787}
788
789static struct notifier_block cpufreq_notifier = {
790 .notifier_call = cpufreq_callback,
791};
792
793static int __init register_cpufreq_notifier(void)
794{
795 return cpufreq_register_notifier(&cpufreq_notifier,
796 CPUFREQ_TRANSITION_NOTIFIER);
797}
798core_initcall(register_cpufreq_notifier);
799
800#endif
96f0e003
RK
801
802static void raise_nmi(cpumask_t *mask)
803{
804 smp_cross_call(mask, IPI_CPU_BACKTRACE);
805}
806
9a01c3ed 807void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
96f0e003 808{
9a01c3ed 809 nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_nmi);
96f0e003 810}