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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * arch/arm/mach-ixp4xx/ixdp425-setup.c | |
4 | * | |
9bf4d676 | 5 | * IXDP425/IXCDP1100 board-setup |
1da177e4 LT |
6 | * |
7 | * Copyright (C) 2003-2005 MontaVista Software, Inc. | |
8 | * | |
9 | * Author: Deepak Saxena <dsaxena@plexity.net> | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/serial.h> | |
16 | #include <linux/tty.h> | |
17 | #include <linux/serial_8250.h> | |
5a4a2387 | 18 | #include <linux/i2c-gpio.h> |
4ad48b4b VB |
19 | #include <linux/io.h> |
20 | #include <linux/mtd/mtd.h> | |
d4092d76 | 21 | #include <linux/mtd/rawnand.h> |
4ad48b4b | 22 | #include <linux/mtd/partitions.h> |
8029db12 | 23 | #include <linux/delay.h> |
8040dd09 | 24 | #include <linux/gpio.h> |
1da177e4 LT |
25 | #include <asm/types.h> |
26 | #include <asm/setup.h> | |
27 | #include <asm/memory.h> | |
a09e64fb | 28 | #include <mach/hardware.h> |
1da177e4 LT |
29 | #include <asm/mach-types.h> |
30 | #include <asm/irq.h> | |
31 | #include <asm/mach/arch.h> | |
32 | #include <asm/mach/flash.h> | |
33 | ||
9bf4d676 KH |
34 | #define IXDP425_SDA_PIN 7 |
35 | #define IXDP425_SCL_PIN 6 | |
36 | ||
37 | /* NAND Flash pins */ | |
38 | #define IXDP425_NAND_NCE_PIN 12 | |
39 | ||
40 | #define IXDP425_NAND_CMD_BYTE 0x01 | |
41 | #define IXDP425_NAND_ADDR_BYTE 0x02 | |
42 | ||
1da177e4 LT |
43 | static struct flash_platform_data ixdp425_flash_data = { |
44 | .map_name = "cfi_probe", | |
45 | .width = 2, | |
46 | }; | |
47 | ||
48 | static struct resource ixdp425_flash_resource = { | |
1da177e4 LT |
49 | .flags = IORESOURCE_MEM, |
50 | }; | |
51 | ||
52 | static struct platform_device ixdp425_flash = { | |
53 | .name = "IXP4XX-Flash", | |
54 | .id = 0, | |
55 | .dev = { | |
56 | .platform_data = &ixdp425_flash_data, | |
57 | }, | |
58 | .num_resources = 1, | |
59 | .resource = &ixdp425_flash_resource, | |
60 | }; | |
61 | ||
4ad48b4b VB |
62 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
63 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
64 | ||
4ad48b4b VB |
65 | static struct mtd_partition ixdp425_partitions[] = { |
66 | { | |
67 | .name = "ixp400 NAND FS 0", | |
68 | .offset = 0, | |
69 | .size = SZ_8M | |
70 | }, { | |
71 | .name = "ixp400 NAND FS 1", | |
72 | .offset = MTDPART_OFS_APPEND, | |
73 | .size = MTDPART_SIZ_FULL | |
74 | }, | |
75 | }; | |
4ad48b4b VB |
76 | |
77 | static void | |
78 | ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
79 | { | |
c993e095 | 80 | struct nand_chip *this = mtd_to_nand(mtd); |
d9dccc68 | 81 | int offset = (int)nand_get_controller_data(this); |
4ad48b4b VB |
82 | |
83 | if (ctrl & NAND_CTRL_CHANGE) { | |
84 | if (ctrl & NAND_NCE) { | |
8040dd09 | 85 | gpio_set_value(IXDP425_NAND_NCE_PIN, 0); |
4ad48b4b VB |
86 | udelay(5); |
87 | } else | |
8040dd09 | 88 | gpio_set_value(IXDP425_NAND_NCE_PIN, 1); |
4ad48b4b VB |
89 | |
90 | offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0; | |
91 | offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0; | |
d9dccc68 | 92 | nand_set_controller_data(this, (void *)offset); |
4ad48b4b VB |
93 | } |
94 | ||
95 | if (cmd != NAND_CMD_NONE) | |
96 | writeb(cmd, this->IO_ADDR_W + offset); | |
97 | } | |
98 | ||
99 | static struct platform_nand_data ixdp425_flash_nand_data = { | |
100 | .chip = { | |
ef077179 | 101 | .nr_chips = 1, |
4ad48b4b | 102 | .chip_delay = 30, |
4ad48b4b VB |
103 | .partitions = ixdp425_partitions, |
104 | .nr_partitions = ARRAY_SIZE(ixdp425_partitions), | |
4ad48b4b VB |
105 | }, |
106 | .ctrl = { | |
107 | .cmd_ctrl = ixdp425_flash_nand_cmd_ctrl | |
108 | } | |
109 | }; | |
110 | ||
111 | static struct resource ixdp425_flash_nand_resource = { | |
112 | .flags = IORESOURCE_MEM, | |
113 | }; | |
114 | ||
115 | static struct platform_device ixdp425_flash_nand = { | |
116 | .name = "gen_nand", | |
117 | .id = -1, | |
118 | .dev = { | |
119 | .platform_data = &ixdp425_flash_nand_data, | |
120 | }, | |
121 | .num_resources = 1, | |
122 | .resource = &ixdp425_flash_nand_resource, | |
123 | }; | |
124 | #endif /* CONFIG_MTD_NAND_PLATFORM */ | |
125 | ||
5a4a2387 | 126 | static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = { |
1da177e4 LT |
127 | .sda_pin = IXDP425_SDA_PIN, |
128 | .scl_pin = IXDP425_SCL_PIN, | |
129 | }; | |
130 | ||
5a4a2387 MLJ |
131 | static struct platform_device ixdp425_i2c_gpio = { |
132 | .name = "i2c-gpio", | |
1da177e4 | 133 | .id = 0, |
5a4a2387 MLJ |
134 | .dev = { |
135 | .platform_data = &ixdp425_i2c_gpio_data, | |
1da177e4 | 136 | }, |
1da177e4 LT |
137 | }; |
138 | ||
139 | static struct resource ixdp425_uart_resources[] = { | |
140 | { | |
141 | .start = IXP4XX_UART1_BASE_PHYS, | |
142 | .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, | |
143 | .flags = IORESOURCE_MEM | |
144 | }, | |
145 | { | |
146 | .start = IXP4XX_UART2_BASE_PHYS, | |
147 | .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, | |
148 | .flags = IORESOURCE_MEM | |
149 | } | |
150 | }; | |
151 | ||
152 | static struct plat_serial8250_port ixdp425_uart_data[] = { | |
153 | { | |
154 | .mapbase = IXP4XX_UART1_BASE_PHYS, | |
155 | .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, | |
156 | .irq = IRQ_IXP4XX_UART1, | |
8c741ed7 | 157 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
1da177e4 LT |
158 | .iotype = UPIO_MEM, |
159 | .regshift = 2, | |
160 | .uartclk = IXP4XX_UART_XTAL, | |
161 | }, | |
162 | { | |
163 | .mapbase = IXP4XX_UART2_BASE_PHYS, | |
164 | .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, | |
a35d6c91 | 165 | .irq = IRQ_IXP4XX_UART2, |
8c741ed7 | 166 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
1da177e4 LT |
167 | .iotype = UPIO_MEM, |
168 | .regshift = 2, | |
169 | .uartclk = IXP4XX_UART_XTAL, | |
bcaafbe4 SS |
170 | }, |
171 | { }, | |
1da177e4 LT |
172 | }; |
173 | ||
174 | static struct platform_device ixdp425_uart = { | |
175 | .name = "serial8250", | |
6df29deb | 176 | .id = PLAT8250_DEV_PLATFORM, |
1da177e4 LT |
177 | .dev.platform_data = ixdp425_uart_data, |
178 | .num_resources = 2, | |
179 | .resource = ixdp425_uart_resources | |
180 | }; | |
181 | ||
78225913 RW |
182 | /* Built-in 10/100 Ethernet MAC interfaces */ |
183 | static struct eth_plat_info ixdp425_plat_eth[] = { | |
184 | { | |
185 | .phy = 0, | |
186 | .rxq = 3, | |
187 | .txreadyq = 20, | |
188 | }, { | |
189 | .phy = 1, | |
190 | .rxq = 4, | |
191 | .txreadyq = 21, | |
192 | } | |
193 | }; | |
194 | ||
195 | static struct platform_device ixdp425_eth[] = { | |
196 | { | |
197 | .name = "ixp4xx_eth", | |
198 | .id = IXP4XX_ETH_NPEB, | |
199 | .dev.platform_data = ixdp425_plat_eth, | |
200 | }, { | |
201 | .name = "ixp4xx_eth", | |
202 | .id = IXP4XX_ETH_NPEC, | |
203 | .dev.platform_data = ixdp425_plat_eth + 1, | |
204 | } | |
205 | }; | |
206 | ||
1da177e4 | 207 | static struct platform_device *ixdp425_devices[] __initdata = { |
5a4a2387 | 208 | &ixdp425_i2c_gpio, |
1da177e4 | 209 | &ixdp425_flash, |
4ad48b4b VB |
210 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
211 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
212 | &ixdp425_flash_nand, | |
213 | #endif | |
78225913 RW |
214 | &ixdp425_uart, |
215 | &ixdp425_eth[0], | |
216 | &ixdp425_eth[1], | |
1da177e4 LT |
217 | }; |
218 | ||
1da177e4 LT |
219 | static void __init ixdp425_init(void) |
220 | { | |
221 | ixp4xx_sys_init(); | |
222 | ||
54e269ea DS |
223 | ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); |
224 | ixdp425_flash_resource.end = | |
225 | IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; | |
1da177e4 | 226 | |
4ad48b4b VB |
227 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
228 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
229 | ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3), | |
230 | ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1; | |
231 | ||
8040dd09 LW |
232 | gpio_request(IXDP425_NAND_NCE_PIN, "NAND NCE pin"); |
233 | gpio_direction_output(IXDP425_NAND_NCE_PIN, 0); | |
4ad48b4b VB |
234 | |
235 | /* Configure expansion bus for NAND Flash */ | |
236 | *IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN | | |
237 | IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */ | |
238 | IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */ | |
239 | IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/ | |
240 | IXP4XX_EXP_BUS_WR_EN | | |
241 | IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */ | |
242 | #endif | |
243 | ||
45fba084 RS |
244 | if (cpu_is_ixp43x()) { |
245 | ixdp425_uart.num_resources = 1; | |
246 | ixdp425_uart_data[1].flags = 0; | |
247 | } | |
248 | ||
1da177e4 LT |
249 | platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices)); |
250 | } | |
251 | ||
b38708fc | 252 | #ifdef CONFIG_ARCH_IXDP425 |
1da177e4 | 253 | MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") |
e9dea0c6 | 254 | /* Maintainer: MontaVista Software, Inc. */ |
e605ecd7 | 255 | .map_io = ixp4xx_map_io, |
f449588c | 256 | .init_early = ixp4xx_init_early, |
e9dea0c6 | 257 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 258 | .init_time = ixp4xx_timer_init, |
e022c729 | 259 | .atag_offset = 0x100, |
e9dea0c6 | 260 | .init_machine = ixdp425_init, |
7553ee77 NP |
261 | #if defined(CONFIG_PCI) |
262 | .dma_zone_size = SZ_64M, | |
263 | #endif | |
d1b860fb | 264 | .restart = ixp4xx_restart, |
1da177e4 | 265 | MACHINE_END |
e0a20089 | 266 | #endif |
1da177e4 | 267 | |
e0a20089 | 268 | #ifdef CONFIG_MACH_IXDP465 |
1da177e4 | 269 | MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") |
e9dea0c6 | 270 | /* Maintainer: MontaVista Software, Inc. */ |
e605ecd7 | 271 | .map_io = ixp4xx_map_io, |
f449588c | 272 | .init_early = ixp4xx_init_early, |
e9dea0c6 | 273 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 274 | .init_time = ixp4xx_timer_init, |
e022c729 | 275 | .atag_offset = 0x100, |
e9dea0c6 | 276 | .init_machine = ixdp425_init, |
7553ee77 NP |
277 | #if defined(CONFIG_PCI) |
278 | .dma_zone_size = SZ_64M, | |
279 | #endif | |
1da177e4 | 280 | MACHINE_END |
e0a20089 | 281 | #endif |
1da177e4 | 282 | |
e0a20089 | 283 | #ifdef CONFIG_ARCH_PRPMC1100 |
1da177e4 | 284 | MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") |
e9dea0c6 | 285 | /* Maintainer: MontaVista Software, Inc. */ |
e605ecd7 | 286 | .map_io = ixp4xx_map_io, |
f449588c | 287 | .init_early = ixp4xx_init_early, |
e9dea0c6 | 288 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 289 | .init_time = ixp4xx_timer_init, |
e022c729 | 290 | .atag_offset = 0x100, |
e9dea0c6 | 291 | .init_machine = ixdp425_init, |
7553ee77 NP |
292 | #if defined(CONFIG_PCI) |
293 | .dma_zone_size = SZ_64M, | |
294 | #endif | |
1da177e4 | 295 | MACHINE_END |
e0a20089 | 296 | #endif |
45fba084 RS |
297 | |
298 | #ifdef CONFIG_MACH_KIXRP435 | |
299 | MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform") | |
300 | /* Maintainer: MontaVista Software, Inc. */ | |
45fba084 | 301 | .map_io = ixp4xx_map_io, |
f449588c | 302 | .init_early = ixp4xx_init_early, |
45fba084 | 303 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 304 | .init_time = ixp4xx_timer_init, |
e022c729 | 305 | .atag_offset = 0x100, |
45fba084 | 306 | .init_machine = ixdp425_init, |
7553ee77 NP |
307 | #if defined(CONFIG_PCI) |
308 | .dma_zone_size = SZ_64M, | |
309 | #endif | |
45fba084 RS |
310 | MACHINE_END |
311 | #endif |