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Commit | Line | Data |
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4bbbc1ad JY |
1 | /* |
2 | * GPMC support functions | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * Author: Juha Yrjola | |
7 | * | |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
10 | * | |
4bbbc1ad JY |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
fd1dc87d PW |
15 | #undef DEBUG |
16 | ||
db97eb7d | 17 | #include <linux/irq.h> |
4bbbc1ad JY |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/clk.h> | |
f37e4580 ID |
22 | #include <linux/ioport.h> |
23 | #include <linux/spinlock.h> | |
fced80c7 | 24 | #include <linux/io.h> |
fd1dc87d | 25 | #include <linux/module.h> |
db97eb7d | 26 | #include <linux/interrupt.h> |
da496873 | 27 | #include <linux/platform_device.h> |
bc6b1e7b | 28 | #include <linux/of.h> |
cdd6928c | 29 | #include <linux/of_address.h> |
bc6b1e7b DM |
30 | #include <linux/of_mtd.h> |
31 | #include <linux/of_device.h> | |
32 | #include <linux/mtd/nand.h> | |
4bbbc1ad | 33 | |
bc3668ea | 34 | #include <linux/platform_data/mtd-nand-omap2.h> |
4bbbc1ad | 35 | |
7f245162 | 36 | #include <asm/mach-types.h> |
72d0f1c3 | 37 | |
dbc04161 | 38 | #include "soc.h" |
7d7e1eba | 39 | #include "common.h" |
25c7d49e | 40 | #include "omap_device.h" |
3ef5d007 | 41 | #include "gpmc.h" |
bc6b1e7b | 42 | #include "gpmc-nand.h" |
75d3625e | 43 | #include "gpmc-onenand.h" |
7d7e1eba | 44 | |
4be48fd5 AM |
45 | #define DEVICE_NAME "omap-gpmc" |
46 | ||
fd1dc87d | 47 | /* GPMC register offsets */ |
4bbbc1ad JY |
48 | #define GPMC_REVISION 0x00 |
49 | #define GPMC_SYSCONFIG 0x10 | |
50 | #define GPMC_SYSSTATUS 0x14 | |
51 | #define GPMC_IRQSTATUS 0x18 | |
52 | #define GPMC_IRQENABLE 0x1c | |
53 | #define GPMC_TIMEOUT_CONTROL 0x40 | |
54 | #define GPMC_ERR_ADDRESS 0x44 | |
55 | #define GPMC_ERR_TYPE 0x48 | |
56 | #define GPMC_CONFIG 0x50 | |
57 | #define GPMC_STATUS 0x54 | |
58 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | |
59 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | |
15e02a3b | 60 | #define GPMC_PREFETCH_CONTROL 0x1ec |
4bbbc1ad JY |
61 | #define GPMC_PREFETCH_STATUS 0x1f0 |
62 | #define GPMC_ECC_CONFIG 0x1f4 | |
63 | #define GPMC_ECC_CONTROL 0x1f8 | |
64 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | |
948d38e7 | 65 | #define GPMC_ECC1_RESULT 0x200 |
8d602cf5 | 66 | #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ |
2fdf0c98 AM |
67 | #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ |
68 | #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ | |
69 | #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ | |
4bbbc1ad | 70 | |
2c65e744 YY |
71 | /* GPMC ECC control settings */ |
72 | #define GPMC_ECC_CTRL_ECCCLEAR 0x100 | |
73 | #define GPMC_ECC_CTRL_ECCDISABLE 0x000 | |
74 | #define GPMC_ECC_CTRL_ECCREG1 0x001 | |
75 | #define GPMC_ECC_CTRL_ECCREG2 0x002 | |
76 | #define GPMC_ECC_CTRL_ECCREG3 0x003 | |
77 | #define GPMC_ECC_CTRL_ECCREG4 0x004 | |
78 | #define GPMC_ECC_CTRL_ECCREG5 0x005 | |
79 | #define GPMC_ECC_CTRL_ECCREG6 0x006 | |
80 | #define GPMC_ECC_CTRL_ECCREG7 0x007 | |
81 | #define GPMC_ECC_CTRL_ECCREG8 0x008 | |
82 | #define GPMC_ECC_CTRL_ECCREG9 0x009 | |
83 | ||
559d94b0 AM |
84 | #define GPMC_CONFIG2_CSEXTRADELAY BIT(7) |
85 | #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) | |
86 | #define GPMC_CONFIG4_OEEXTRADELAY BIT(7) | |
87 | #define GPMC_CONFIG4_WEEXTRADELAY BIT(23) | |
88 | #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6) | |
89 | #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7) | |
90 | ||
948d38e7 | 91 | #define GPMC_CS0_OFFSET 0x60 |
4bbbc1ad | 92 | #define GPMC_CS_SIZE 0x30 |
2fdf0c98 | 93 | #define GPMC_BCH_SIZE 0x10 |
4bbbc1ad | 94 | |
f37e4580 ID |
95 | #define GPMC_MEM_START 0x00000000 |
96 | #define GPMC_MEM_END 0x3FFFFFFF | |
97 | #define BOOT_ROM_SPACE 0x100000 /* 1MB */ | |
98 | ||
99 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ | |
100 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ | |
101 | ||
59e9c5ae | 102 | #define CS_NUM_SHIFT 24 |
103 | #define ENABLE_PREFETCH (0x1 << 7) | |
104 | #define DMA_MPU_MODE 2 | |
105 | ||
da496873 AM |
106 | #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) |
107 | #define GPMC_REVISION_MINOR(l) (l & 0xf) | |
108 | ||
109 | #define GPMC_HAS_WR_ACCESS 0x1 | |
110 | #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 | |
aa8d4767 | 111 | #define GPMC_HAS_MUX_AAD 0x4 |
da496873 | 112 | |
9f833156 JH |
113 | #define GPMC_NR_WAITPINS 4 |
114 | ||
6b6c32fc AM |
115 | /* XXX: Only NAND irq has been considered,currently these are the only ones used |
116 | */ | |
117 | #define GPMC_NR_IRQ 2 | |
118 | ||
119 | struct gpmc_client_irq { | |
120 | unsigned irq; | |
121 | u32 bitmask; | |
122 | }; | |
123 | ||
a2d3e7ba RN |
124 | /* Structure to save gpmc cs context */ |
125 | struct gpmc_cs_config { | |
126 | u32 config1; | |
127 | u32 config2; | |
128 | u32 config3; | |
129 | u32 config4; | |
130 | u32 config5; | |
131 | u32 config6; | |
132 | u32 config7; | |
133 | int is_valid; | |
134 | }; | |
135 | ||
136 | /* | |
137 | * Structure to save/restore gpmc context | |
138 | * to support core off on OMAP3 | |
139 | */ | |
140 | struct omap3_gpmc_regs { | |
141 | u32 sysconfig; | |
142 | u32 irqenable; | |
143 | u32 timeout_ctrl; | |
144 | u32 config; | |
145 | u32 prefetch_config1; | |
146 | u32 prefetch_config2; | |
147 | u32 prefetch_control; | |
148 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | |
149 | }; | |
150 | ||
6b6c32fc AM |
151 | static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; |
152 | static struct irq_chip gpmc_irq_chip; | |
153 | static unsigned gpmc_irq_start; | |
154 | ||
f37e4580 ID |
155 | static struct resource gpmc_mem_root; |
156 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | |
87b247c4 | 157 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
6797b4fe JH |
158 | /* Define chip-selects as reserved by default until probe completes */ |
159 | static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); | |
9f833156 | 160 | static unsigned int gpmc_nr_waitpins; |
da496873 AM |
161 | static struct device *gpmc_dev; |
162 | static int gpmc_irq; | |
163 | static resource_size_t phys_base, mem_size; | |
164 | static unsigned gpmc_capability; | |
fd1dc87d | 165 | static void __iomem *gpmc_base; |
4bbbc1ad | 166 | |
fd1dc87d | 167 | static struct clk *gpmc_l3_clk; |
4bbbc1ad | 168 | |
db97eb7d SG |
169 | static irqreturn_t gpmc_handle_irq(int irq, void *dev); |
170 | ||
4bbbc1ad JY |
171 | static void gpmc_write_reg(int idx, u32 val) |
172 | { | |
173 | __raw_writel(val, gpmc_base + idx); | |
174 | } | |
175 | ||
176 | static u32 gpmc_read_reg(int idx) | |
177 | { | |
178 | return __raw_readl(gpmc_base + idx); | |
179 | } | |
180 | ||
181 | void gpmc_cs_write_reg(int cs, int idx, u32 val) | |
182 | { | |
183 | void __iomem *reg_addr; | |
184 | ||
948d38e7 | 185 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
4bbbc1ad JY |
186 | __raw_writel(val, reg_addr); |
187 | } | |
188 | ||
3fc089e7 | 189 | static u32 gpmc_cs_read_reg(int cs, int idx) |
4bbbc1ad | 190 | { |
fd1dc87d PW |
191 | void __iomem *reg_addr; |
192 | ||
948d38e7 | 193 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
fd1dc87d | 194 | return __raw_readl(reg_addr); |
4bbbc1ad JY |
195 | } |
196 | ||
fd1dc87d | 197 | /* TODO: Add support for gpmc_fck to clock framework and use it */ |
3fc089e7 | 198 | static unsigned long gpmc_get_fclk_period(void) |
4bbbc1ad | 199 | { |
fd1dc87d PW |
200 | unsigned long rate = clk_get_rate(gpmc_l3_clk); |
201 | ||
202 | if (rate == 0) { | |
203 | printk(KERN_WARNING "gpmc_l3_clk not enabled\n"); | |
204 | return 0; | |
205 | } | |
206 | ||
207 | rate /= 1000; | |
208 | rate = 1000000000 / rate; /* In picoseconds */ | |
209 | ||
210 | return rate; | |
4bbbc1ad JY |
211 | } |
212 | ||
3fc089e7 | 213 | static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) |
4bbbc1ad JY |
214 | { |
215 | unsigned long tick_ps; | |
216 | ||
217 | /* Calculate in picosecs to yield more exact results */ | |
218 | tick_ps = gpmc_get_fclk_period(); | |
219 | ||
220 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | |
221 | } | |
222 | ||
3fc089e7 | 223 | static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) |
a3551f5b AH |
224 | { |
225 | unsigned long tick_ps; | |
226 | ||
227 | /* Calculate in picosecs to yield more exact results */ | |
228 | tick_ps = gpmc_get_fclk_period(); | |
229 | ||
230 | return (time_ps + tick_ps - 1) / tick_ps; | |
231 | } | |
232 | ||
fd1dc87d PW |
233 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) |
234 | { | |
235 | return ticks * gpmc_get_fclk_period() / 1000; | |
236 | } | |
237 | ||
246da26d AM |
238 | static unsigned int gpmc_ticks_to_ps(unsigned int ticks) |
239 | { | |
240 | return ticks * gpmc_get_fclk_period(); | |
241 | } | |
242 | ||
243 | static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps) | |
244 | { | |
245 | unsigned long ticks = gpmc_ps_to_ticks(time_ps); | |
246 | ||
247 | return ticks * gpmc_get_fclk_period(); | |
248 | } | |
249 | ||
559d94b0 AM |
250 | static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) |
251 | { | |
252 | u32 l; | |
253 | ||
254 | l = gpmc_cs_read_reg(cs, reg); | |
255 | if (value) | |
256 | l |= mask; | |
257 | else | |
258 | l &= ~mask; | |
259 | gpmc_cs_write_reg(cs, reg, l); | |
260 | } | |
261 | ||
262 | static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) | |
263 | { | |
264 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, | |
265 | GPMC_CONFIG1_TIME_PARA_GRAN, | |
266 | p->time_para_granularity); | |
267 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, | |
268 | GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); | |
269 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, | |
270 | GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); | |
271 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | |
272 | GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); | |
273 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | |
274 | GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay); | |
275 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, | |
276 | GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, | |
277 | p->cycle2cyclesamecsen); | |
278 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, | |
279 | GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, | |
280 | p->cycle2cyclediffcsen); | |
281 | } | |
282 | ||
4bbbc1ad JY |
283 | #ifdef DEBUG |
284 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
2aab6468 | 285 | int time, const char *name) |
4bbbc1ad JY |
286 | #else |
287 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
288 | int time) | |
289 | #endif | |
290 | { | |
291 | u32 l; | |
292 | int ticks, mask, nr_bits; | |
293 | ||
294 | if (time == 0) | |
295 | ticks = 0; | |
296 | else | |
297 | ticks = gpmc_ns_to_ticks(time); | |
298 | nr_bits = end_bit - st_bit + 1; | |
1c22cc13 DB |
299 | if (ticks >= 1 << nr_bits) { |
300 | #ifdef DEBUG | |
301 | printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n", | |
302 | cs, name, time, ticks, 1 << nr_bits); | |
303 | #endif | |
4bbbc1ad | 304 | return -1; |
1c22cc13 | 305 | } |
4bbbc1ad JY |
306 | |
307 | mask = (1 << nr_bits) - 1; | |
308 | l = gpmc_cs_read_reg(cs, reg); | |
309 | #ifdef DEBUG | |
1c22cc13 DB |
310 | printk(KERN_INFO |
311 | "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", | |
2aab6468 | 312 | cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000, |
1c22cc13 | 313 | (l >> st_bit) & mask, time); |
4bbbc1ad JY |
314 | #endif |
315 | l &= ~(mask << st_bit); | |
316 | l |= ticks << st_bit; | |
317 | gpmc_cs_write_reg(cs, reg, l); | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
322 | #ifdef DEBUG | |
323 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
324 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ | |
325 | t->field, #field) < 0) \ | |
326 | return -1 | |
327 | #else | |
328 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
329 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \ | |
330 | return -1 | |
331 | #endif | |
332 | ||
1b47ca1a | 333 | int gpmc_calc_divider(unsigned int sync_clk) |
4bbbc1ad JY |
334 | { |
335 | int div; | |
336 | u32 l; | |
337 | ||
a3551f5b | 338 | l = sync_clk + (gpmc_get_fclk_period() - 1); |
4bbbc1ad JY |
339 | div = l / gpmc_get_fclk_period(); |
340 | if (div > 4) | |
341 | return -1; | |
1c22cc13 | 342 | if (div <= 0) |
4bbbc1ad JY |
343 | div = 1; |
344 | ||
345 | return div; | |
346 | } | |
347 | ||
348 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) | |
349 | { | |
350 | int div; | |
351 | u32 l; | |
352 | ||
1b47ca1a | 353 | div = gpmc_calc_divider(t->sync_clk); |
4bbbc1ad | 354 | if (div < 0) |
a032d33b | 355 | return div; |
4bbbc1ad JY |
356 | |
357 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); | |
358 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | |
359 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | |
360 | ||
361 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | |
362 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | |
363 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | |
364 | ||
365 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | |
366 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | |
367 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); | |
368 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | |
369 | ||
370 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | |
371 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | |
372 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | |
373 | ||
374 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | |
375 | ||
559d94b0 AM |
376 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround); |
377 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay); | |
378 | ||
379 | GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring); | |
380 | GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation); | |
381 | ||
da496873 | 382 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) |
cc26b3b0 | 383 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); |
da496873 | 384 | if (gpmc_capability & GPMC_HAS_WR_ACCESS) |
cc26b3b0 | 385 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); |
cc26b3b0 | 386 | |
1c22cc13 DB |
387 | /* caller is expected to have initialized CONFIG1 to cover |
388 | * at least sync vs async | |
389 | */ | |
390 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
391 | if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { | |
4bbbc1ad | 392 | #ifdef DEBUG |
1c22cc13 DB |
393 | printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", |
394 | cs, (div * gpmc_get_fclk_period()) / 1000, div); | |
4bbbc1ad | 395 | #endif |
1c22cc13 DB |
396 | l &= ~0x03; |
397 | l |= (div - 1); | |
398 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); | |
399 | } | |
4bbbc1ad | 400 | |
559d94b0 AM |
401 | gpmc_cs_bool_timings(cs, &t->bool_timings); |
402 | ||
4bbbc1ad JY |
403 | return 0; |
404 | } | |
405 | ||
c71f8e9b | 406 | static int gpmc_cs_enable_mem(int cs, u32 base, u32 size) |
f37e4580 ID |
407 | { |
408 | u32 l; | |
409 | u32 mask; | |
410 | ||
c71f8e9b JH |
411 | /* |
412 | * Ensure that base address is aligned on a | |
413 | * boundary equal to or greater than size. | |
414 | */ | |
415 | if (base & (size - 1)) | |
416 | return -EINVAL; | |
417 | ||
f37e4580 ID |
418 | mask = (1 << GPMC_SECTION_SHIFT) - size; |
419 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
420 | l &= ~0x3f; | |
421 | l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; | |
422 | l &= ~(0x0f << 8); | |
423 | l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; | |
a2d3e7ba | 424 | l |= GPMC_CONFIG7_CSVALID; |
f37e4580 | 425 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
c71f8e9b JH |
426 | |
427 | return 0; | |
f37e4580 ID |
428 | } |
429 | ||
430 | static void gpmc_cs_disable_mem(int cs) | |
431 | { | |
432 | u32 l; | |
433 | ||
434 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 435 | l &= ~GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
436 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
437 | } | |
438 | ||
439 | static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) | |
440 | { | |
441 | u32 l; | |
442 | u32 mask; | |
443 | ||
444 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
445 | *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; | |
446 | mask = (l >> 8) & 0x0f; | |
447 | *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); | |
448 | } | |
449 | ||
450 | static int gpmc_cs_mem_enabled(int cs) | |
451 | { | |
452 | u32 l; | |
453 | ||
454 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 455 | return l & GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
456 | } |
457 | ||
f5d8edaf | 458 | static void gpmc_cs_set_reserved(int cs, int reserved) |
4bbbc1ad | 459 | { |
f37e4580 ID |
460 | gpmc_cs_map &= ~(1 << cs); |
461 | gpmc_cs_map |= (reserved ? 1 : 0) << cs; | |
462 | } | |
463 | ||
ae9d908a | 464 | static bool gpmc_cs_reserved(int cs) |
f37e4580 ID |
465 | { |
466 | return gpmc_cs_map & (1 << cs); | |
467 | } | |
468 | ||
469 | static unsigned long gpmc_mem_align(unsigned long size) | |
470 | { | |
471 | int order; | |
472 | ||
473 | size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); | |
474 | order = GPMC_CHUNK_SHIFT - 1; | |
475 | do { | |
476 | size >>= 1; | |
477 | order++; | |
478 | } while (size); | |
479 | size = 1 << order; | |
480 | return size; | |
481 | } | |
482 | ||
483 | static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) | |
484 | { | |
485 | struct resource *res = &gpmc_cs_mem[cs]; | |
486 | int r; | |
487 | ||
488 | size = gpmc_mem_align(size); | |
489 | spin_lock(&gpmc_mem_lock); | |
490 | res->start = base; | |
491 | res->end = base + size - 1; | |
492 | r = request_resource(&gpmc_mem_root, res); | |
493 | spin_unlock(&gpmc_mem_lock); | |
494 | ||
495 | return r; | |
496 | } | |
497 | ||
da496873 AM |
498 | static int gpmc_cs_delete_mem(int cs) |
499 | { | |
500 | struct resource *res = &gpmc_cs_mem[cs]; | |
501 | int r; | |
502 | ||
503 | spin_lock(&gpmc_mem_lock); | |
504 | r = release_resource(&gpmc_cs_mem[cs]); | |
505 | res->start = 0; | |
506 | res->end = 0; | |
507 | spin_unlock(&gpmc_mem_lock); | |
508 | ||
509 | return r; | |
510 | } | |
511 | ||
cdd6928c JH |
512 | /** |
513 | * gpmc_cs_remap - remaps a chip-select physical base address | |
514 | * @cs: chip-select to remap | |
515 | * @base: physical base address to re-map chip-select to | |
516 | * | |
517 | * Re-maps a chip-select to a new physical base address specified by | |
518 | * "base". Returns 0 on success and appropriate negative error code | |
519 | * on failure. | |
520 | */ | |
521 | static int gpmc_cs_remap(int cs, u32 base) | |
522 | { | |
523 | int ret; | |
524 | u32 old_base, size; | |
525 | ||
526 | if (cs > GPMC_CS_NUM) | |
527 | return -ENODEV; | |
528 | gpmc_cs_get_memconf(cs, &old_base, &size); | |
529 | if (base == old_base) | |
530 | return 0; | |
531 | gpmc_cs_disable_mem(cs); | |
532 | ret = gpmc_cs_delete_mem(cs); | |
533 | if (ret < 0) | |
534 | return ret; | |
535 | ret = gpmc_cs_insert_mem(cs, base, size); | |
536 | if (ret < 0) | |
537 | return ret; | |
c71f8e9b JH |
538 | ret = gpmc_cs_enable_mem(cs, base, size); |
539 | if (ret < 0) | |
540 | return ret; | |
cdd6928c JH |
541 | |
542 | return 0; | |
543 | } | |
544 | ||
f37e4580 ID |
545 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) |
546 | { | |
547 | struct resource *res = &gpmc_cs_mem[cs]; | |
548 | int r = -1; | |
549 | ||
550 | if (cs > GPMC_CS_NUM) | |
551 | return -ENODEV; | |
552 | ||
553 | size = gpmc_mem_align(size); | |
554 | if (size > (1 << GPMC_SECTION_SHIFT)) | |
555 | return -ENOMEM; | |
556 | ||
557 | spin_lock(&gpmc_mem_lock); | |
558 | if (gpmc_cs_reserved(cs)) { | |
559 | r = -EBUSY; | |
560 | goto out; | |
561 | } | |
562 | if (gpmc_cs_mem_enabled(cs)) | |
563 | r = adjust_resource(res, res->start & ~(size - 1), size); | |
564 | if (r < 0) | |
565 | r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, | |
566 | size, NULL, NULL); | |
567 | if (r < 0) | |
568 | goto out; | |
569 | ||
c71f8e9b JH |
570 | r = gpmc_cs_enable_mem(cs, res->start, resource_size(res)); |
571 | if (r < 0) { | |
572 | release_resource(res); | |
573 | goto out; | |
574 | } | |
575 | ||
f37e4580 ID |
576 | *base = res->start; |
577 | gpmc_cs_set_reserved(cs, 1); | |
578 | out: | |
579 | spin_unlock(&gpmc_mem_lock); | |
580 | return r; | |
581 | } | |
fd1dc87d | 582 | EXPORT_SYMBOL(gpmc_cs_request); |
f37e4580 ID |
583 | |
584 | void gpmc_cs_free(int cs) | |
585 | { | |
586 | spin_lock(&gpmc_mem_lock); | |
e7fdc605 | 587 | if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) { |
f37e4580 ID |
588 | printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); |
589 | BUG(); | |
590 | spin_unlock(&gpmc_mem_lock); | |
591 | return; | |
592 | } | |
593 | gpmc_cs_disable_mem(cs); | |
594 | release_resource(&gpmc_cs_mem[cs]); | |
595 | gpmc_cs_set_reserved(cs, 0); | |
596 | spin_unlock(&gpmc_mem_lock); | |
597 | } | |
fd1dc87d | 598 | EXPORT_SYMBOL(gpmc_cs_free); |
f37e4580 | 599 | |
948d38e7 | 600 | /** |
3a544354 | 601 | * gpmc_configure - write request to configure gpmc |
948d38e7 SG |
602 | * @cmd: command type |
603 | * @wval: value to write | |
604 | * @return status of the operation | |
605 | */ | |
3a544354 | 606 | int gpmc_configure(int cmd, int wval) |
948d38e7 | 607 | { |
3a544354 | 608 | u32 regval; |
948d38e7 SG |
609 | |
610 | switch (cmd) { | |
db97eb7d SG |
611 | case GPMC_ENABLE_IRQ: |
612 | gpmc_write_reg(GPMC_IRQENABLE, wval); | |
613 | break; | |
614 | ||
948d38e7 SG |
615 | case GPMC_SET_IRQ_STATUS: |
616 | gpmc_write_reg(GPMC_IRQSTATUS, wval); | |
617 | break; | |
618 | ||
619 | case GPMC_CONFIG_WP: | |
620 | regval = gpmc_read_reg(GPMC_CONFIG); | |
621 | if (wval) | |
622 | regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ | |
623 | else | |
624 | regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ | |
625 | gpmc_write_reg(GPMC_CONFIG, regval); | |
626 | break; | |
627 | ||
948d38e7 | 628 | default: |
3a544354 JH |
629 | pr_err("%s: command not supported\n", __func__); |
630 | return -EINVAL; | |
948d38e7 SG |
631 | } |
632 | ||
3a544354 | 633 | return 0; |
948d38e7 | 634 | } |
3a544354 | 635 | EXPORT_SYMBOL(gpmc_configure); |
948d38e7 | 636 | |
52bd138d AM |
637 | void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) |
638 | { | |
2fdf0c98 AM |
639 | int i; |
640 | ||
52bd138d AM |
641 | reg->gpmc_status = gpmc_base + GPMC_STATUS; |
642 | reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + | |
643 | GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; | |
644 | reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + | |
645 | GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; | |
646 | reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + | |
647 | GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; | |
648 | reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; | |
649 | reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; | |
650 | reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; | |
651 | reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; | |
652 | reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; | |
653 | reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; | |
654 | reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; | |
655 | reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; | |
2fdf0c98 AM |
656 | |
657 | for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { | |
658 | reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + | |
659 | GPMC_BCH_SIZE * i; | |
660 | reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + | |
661 | GPMC_BCH_SIZE * i; | |
662 | reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + | |
663 | GPMC_BCH_SIZE * i; | |
664 | reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + | |
665 | GPMC_BCH_SIZE * i; | |
666 | } | |
52bd138d AM |
667 | } |
668 | ||
6b6c32fc AM |
669 | int gpmc_get_client_irq(unsigned irq_config) |
670 | { | |
671 | int i; | |
672 | ||
673 | if (hweight32(irq_config) > 1) | |
674 | return 0; | |
675 | ||
676 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
677 | if (gpmc_client_irq[i].bitmask & irq_config) | |
678 | return gpmc_client_irq[i].irq; | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
683 | static int gpmc_irq_endis(unsigned irq, bool endis) | |
684 | { | |
685 | int i; | |
686 | u32 regval; | |
687 | ||
688 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
689 | if (irq == gpmc_client_irq[i].irq) { | |
690 | regval = gpmc_read_reg(GPMC_IRQENABLE); | |
691 | if (endis) | |
692 | regval |= gpmc_client_irq[i].bitmask; | |
693 | else | |
694 | regval &= ~gpmc_client_irq[i].bitmask; | |
695 | gpmc_write_reg(GPMC_IRQENABLE, regval); | |
696 | break; | |
697 | } | |
698 | ||
699 | return 0; | |
700 | } | |
701 | ||
702 | static void gpmc_irq_disable(struct irq_data *p) | |
703 | { | |
704 | gpmc_irq_endis(p->irq, false); | |
705 | } | |
706 | ||
707 | static void gpmc_irq_enable(struct irq_data *p) | |
708 | { | |
709 | gpmc_irq_endis(p->irq, true); | |
710 | } | |
711 | ||
712 | static void gpmc_irq_noop(struct irq_data *data) { } | |
713 | ||
714 | static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } | |
715 | ||
da496873 | 716 | static int gpmc_setup_irq(void) |
6b6c32fc AM |
717 | { |
718 | int i; | |
719 | u32 regval; | |
720 | ||
721 | if (!gpmc_irq) | |
722 | return -EINVAL; | |
723 | ||
724 | gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); | |
71856843 | 725 | if (gpmc_irq_start < 0) { |
6b6c32fc AM |
726 | pr_err("irq_alloc_descs failed\n"); |
727 | return gpmc_irq_start; | |
728 | } | |
729 | ||
730 | gpmc_irq_chip.name = "gpmc"; | |
731 | gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret; | |
732 | gpmc_irq_chip.irq_enable = gpmc_irq_enable; | |
733 | gpmc_irq_chip.irq_disable = gpmc_irq_disable; | |
734 | gpmc_irq_chip.irq_shutdown = gpmc_irq_noop; | |
735 | gpmc_irq_chip.irq_ack = gpmc_irq_noop; | |
736 | gpmc_irq_chip.irq_mask = gpmc_irq_noop; | |
737 | gpmc_irq_chip.irq_unmask = gpmc_irq_noop; | |
738 | ||
739 | gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE; | |
740 | gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT; | |
741 | ||
742 | for (i = 0; i < GPMC_NR_IRQ; i++) { | |
743 | gpmc_client_irq[i].irq = gpmc_irq_start + i; | |
744 | irq_set_chip_and_handler(gpmc_client_irq[i].irq, | |
745 | &gpmc_irq_chip, handle_simple_irq); | |
746 | set_irq_flags(gpmc_client_irq[i].irq, | |
747 | IRQF_VALID | IRQF_NOAUTOEN); | |
748 | } | |
749 | ||
750 | /* Disable interrupts */ | |
751 | gpmc_write_reg(GPMC_IRQENABLE, 0); | |
752 | ||
753 | /* clear interrupts */ | |
754 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
755 | gpmc_write_reg(GPMC_IRQSTATUS, regval); | |
756 | ||
757 | return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); | |
758 | } | |
759 | ||
351a102d | 760 | static int gpmc_free_irq(void) |
da496873 AM |
761 | { |
762 | int i; | |
763 | ||
764 | if (gpmc_irq) | |
765 | free_irq(gpmc_irq, NULL); | |
766 | ||
767 | for (i = 0; i < GPMC_NR_IRQ; i++) { | |
768 | irq_set_handler(gpmc_client_irq[i].irq, NULL); | |
769 | irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip); | |
770 | irq_modify_status(gpmc_client_irq[i].irq, 0, 0); | |
771 | } | |
772 | ||
773 | irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
351a102d | 778 | static void gpmc_mem_exit(void) |
da496873 AM |
779 | { |
780 | int cs; | |
781 | ||
782 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | |
783 | if (!gpmc_cs_mem_enabled(cs)) | |
784 | continue; | |
785 | gpmc_cs_delete_mem(cs); | |
786 | } | |
787 | ||
788 | } | |
789 | ||
351a102d | 790 | static int gpmc_mem_init(void) |
f37e4580 | 791 | { |
8119024e | 792 | int cs, rc; |
f37e4580 ID |
793 | unsigned long boot_rom_space = 0; |
794 | ||
7f245162 KP |
795 | /* never allocate the first page, to facilitate bug detection; |
796 | * even if we didn't boot from ROM. | |
797 | */ | |
798 | boot_rom_space = BOOT_ROM_SPACE; | |
f37e4580 ID |
799 | gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space; |
800 | gpmc_mem_root.end = GPMC_MEM_END; | |
801 | ||
802 | /* Reserve all regions that has been set up by bootloader */ | |
803 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | |
804 | u32 base, size; | |
805 | ||
806 | if (!gpmc_cs_mem_enabled(cs)) | |
807 | continue; | |
808 | gpmc_cs_get_memconf(cs, &base, &size); | |
8119024e | 809 | rc = gpmc_cs_insert_mem(cs, base, size); |
71856843 | 810 | if (rc < 0) { |
8119024e JH |
811 | while (--cs >= 0) |
812 | if (gpmc_cs_mem_enabled(cs)) | |
813 | gpmc_cs_delete_mem(cs); | |
814 | return rc; | |
815 | } | |
f37e4580 | 816 | } |
8119024e JH |
817 | |
818 | return 0; | |
4bbbc1ad JY |
819 | } |
820 | ||
246da26d AM |
821 | static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) |
822 | { | |
823 | u32 temp; | |
824 | int div; | |
825 | ||
826 | div = gpmc_calc_divider(sync_clk); | |
827 | temp = gpmc_ps_to_ticks(time_ps); | |
828 | temp = (temp + div - 1) / div; | |
829 | return gpmc_ticks_to_ps(temp * div); | |
830 | } | |
831 | ||
832 | /* XXX: can the cycles be avoided ? */ | |
833 | static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
834 | struct gpmc_device_timings *dev_t, |
835 | bool mux) | |
246da26d | 836 | { |
246da26d AM |
837 | u32 temp; |
838 | ||
839 | /* adv_rd_off */ | |
840 | temp = dev_t->t_avdp_r; | |
841 | /* XXX: mux check required ? */ | |
842 | if (mux) { | |
843 | /* XXX: t_avdp not to be required for sync, only added for tusb | |
844 | * this indirectly necessitates requirement of t_avdp_r and | |
845 | * t_avdp_w instead of having a single t_avdp | |
846 | */ | |
847 | temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh); | |
848 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
849 | } | |
850 | gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); | |
851 | ||
852 | /* oe_on */ | |
853 | temp = dev_t->t_oeasu; /* XXX: remove this ? */ | |
854 | if (mux) { | |
855 | temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach); | |
856 | temp = max_t(u32, temp, gpmc_t->adv_rd_off + | |
857 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe)); | |
858 | } | |
859 | gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); | |
860 | ||
861 | /* access */ | |
862 | /* XXX: any scope for improvement ?, by combining oe_on | |
863 | * and clk_activation, need to check whether | |
864 | * access = clk_activation + round to sync clk ? | |
865 | */ | |
866 | temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk); | |
867 | temp += gpmc_t->clk_activation; | |
868 | if (dev_t->cyc_oe) | |
869 | temp = max_t(u32, temp, gpmc_t->oe_on + | |
870 | gpmc_ticks_to_ps(dev_t->cyc_oe)); | |
871 | gpmc_t->access = gpmc_round_ps_to_ticks(temp); | |
872 | ||
873 | gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); | |
874 | gpmc_t->cs_rd_off = gpmc_t->oe_off; | |
875 | ||
876 | /* rd_cycle */ | |
877 | temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez); | |
878 | temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) + | |
879 | gpmc_t->access; | |
880 | /* XXX: barter t_ce_rdyz with t_cez_r ? */ | |
881 | if (dev_t->t_ce_rdyz) | |
882 | temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz); | |
883 | gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
888 | static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
889 | struct gpmc_device_timings *dev_t, |
890 | bool mux) | |
246da26d | 891 | { |
246da26d AM |
892 | u32 temp; |
893 | ||
894 | /* adv_wr_off */ | |
895 | temp = dev_t->t_avdp_w; | |
896 | if (mux) { | |
897 | temp = max_t(u32, temp, | |
898 | gpmc_t->clk_activation + dev_t->t_avdh); | |
899 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
900 | } | |
901 | gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); | |
902 | ||
903 | /* wr_data_mux_bus */ | |
904 | temp = max_t(u32, dev_t->t_weasu, | |
905 | gpmc_t->clk_activation + dev_t->t_rdyo); | |
906 | /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?, | |
907 | * and in that case remember to handle we_on properly | |
908 | */ | |
909 | if (mux) { | |
910 | temp = max_t(u32, temp, | |
911 | gpmc_t->adv_wr_off + dev_t->t_aavdh); | |
912 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + | |
913 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); | |
914 | } | |
915 | gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); | |
916 | ||
917 | /* we_on */ | |
918 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) | |
919 | gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); | |
920 | else | |
921 | gpmc_t->we_on = gpmc_t->wr_data_mux_bus; | |
922 | ||
923 | /* wr_access */ | |
924 | /* XXX: gpmc_capability check reqd ? , even if not, will not harm */ | |
925 | gpmc_t->wr_access = gpmc_t->access; | |
926 | ||
927 | /* we_off */ | |
928 | temp = gpmc_t->we_on + dev_t->t_wpl; | |
929 | temp = max_t(u32, temp, | |
930 | gpmc_t->wr_access + gpmc_ticks_to_ps(1)); | |
931 | temp = max_t(u32, temp, | |
932 | gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl)); | |
933 | gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); | |
934 | ||
935 | gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + | |
936 | dev_t->t_wph); | |
937 | ||
938 | /* wr_cycle */ | |
939 | temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk); | |
940 | temp += gpmc_t->wr_access; | |
941 | /* XXX: barter t_ce_rdyz with t_cez_w ? */ | |
942 | if (dev_t->t_ce_rdyz) | |
943 | temp = max_t(u32, temp, | |
944 | gpmc_t->cs_wr_off + dev_t->t_ce_rdyz); | |
945 | gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); | |
946 | ||
947 | return 0; | |
948 | } | |
949 | ||
950 | static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
951 | struct gpmc_device_timings *dev_t, |
952 | bool mux) | |
246da26d | 953 | { |
246da26d AM |
954 | u32 temp; |
955 | ||
956 | /* adv_rd_off */ | |
957 | temp = dev_t->t_avdp_r; | |
958 | if (mux) | |
959 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
960 | gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); | |
961 | ||
962 | /* oe_on */ | |
963 | temp = dev_t->t_oeasu; | |
964 | if (mux) | |
965 | temp = max_t(u32, temp, | |
966 | gpmc_t->adv_rd_off + dev_t->t_aavdh); | |
967 | gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); | |
968 | ||
969 | /* access */ | |
970 | temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ | |
971 | gpmc_t->oe_on + dev_t->t_oe); | |
972 | temp = max_t(u32, temp, | |
973 | gpmc_t->cs_on + dev_t->t_ce); | |
974 | temp = max_t(u32, temp, | |
975 | gpmc_t->adv_on + dev_t->t_aa); | |
976 | gpmc_t->access = gpmc_round_ps_to_ticks(temp); | |
977 | ||
978 | gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); | |
979 | gpmc_t->cs_rd_off = gpmc_t->oe_off; | |
980 | ||
981 | /* rd_cycle */ | |
982 | temp = max_t(u32, dev_t->t_rd_cycle, | |
983 | gpmc_t->cs_rd_off + dev_t->t_cez_r); | |
984 | temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez); | |
985 | gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
990 | static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
991 | struct gpmc_device_timings *dev_t, |
992 | bool mux) | |
246da26d | 993 | { |
246da26d AM |
994 | u32 temp; |
995 | ||
996 | /* adv_wr_off */ | |
997 | temp = dev_t->t_avdp_w; | |
998 | if (mux) | |
999 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1000 | gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); | |
1001 | ||
1002 | /* wr_data_mux_bus */ | |
1003 | temp = dev_t->t_weasu; | |
1004 | if (mux) { | |
1005 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh); | |
1006 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + | |
1007 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); | |
1008 | } | |
1009 | gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); | |
1010 | ||
1011 | /* we_on */ | |
1012 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) | |
1013 | gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); | |
1014 | else | |
1015 | gpmc_t->we_on = gpmc_t->wr_data_mux_bus; | |
1016 | ||
1017 | /* we_off */ | |
1018 | temp = gpmc_t->we_on + dev_t->t_wpl; | |
1019 | gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); | |
1020 | ||
1021 | gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + | |
1022 | dev_t->t_wph); | |
1023 | ||
1024 | /* wr_cycle */ | |
1025 | temp = max_t(u32, dev_t->t_wr_cycle, | |
1026 | gpmc_t->cs_wr_off + dev_t->t_cez_w); | |
1027 | gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); | |
1028 | ||
1029 | return 0; | |
1030 | } | |
1031 | ||
1032 | static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, | |
1033 | struct gpmc_device_timings *dev_t) | |
1034 | { | |
1035 | u32 temp; | |
1036 | ||
1037 | gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) * | |
1038 | gpmc_get_fclk_period(); | |
1039 | ||
1040 | gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk( | |
1041 | dev_t->t_bacc, | |
1042 | gpmc_t->sync_clk); | |
1043 | ||
1044 | temp = max_t(u32, dev_t->t_ces, dev_t->t_avds); | |
1045 | gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp); | |
1046 | ||
1047 | if (gpmc_calc_divider(gpmc_t->sync_clk) != 1) | |
1048 | return 0; | |
1049 | ||
1050 | if (dev_t->ce_xdelay) | |
1051 | gpmc_t->bool_timings.cs_extra_delay = true; | |
1052 | if (dev_t->avd_xdelay) | |
1053 | gpmc_t->bool_timings.adv_extra_delay = true; | |
1054 | if (dev_t->oe_xdelay) | |
1055 | gpmc_t->bool_timings.oe_extra_delay = true; | |
1056 | if (dev_t->we_xdelay) | |
1057 | gpmc_t->bool_timings.we_extra_delay = true; | |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1063 | struct gpmc_device_timings *dev_t, |
1064 | bool sync) | |
246da26d AM |
1065 | { |
1066 | u32 temp; | |
1067 | ||
1068 | /* cs_on */ | |
1069 | gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu); | |
1070 | ||
1071 | /* adv_on */ | |
1072 | temp = dev_t->t_avdasu; | |
1073 | if (dev_t->t_ce_avd) | |
1074 | temp = max_t(u32, temp, | |
1075 | gpmc_t->cs_on + dev_t->t_ce_avd); | |
1076 | gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); | |
1077 | ||
c3be5b45 | 1078 | if (sync) |
246da26d AM |
1079 | gpmc_calc_sync_common_timings(gpmc_t, dev_t); |
1080 | ||
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | /* TODO: remove this function once all peripherals are confirmed to | |
1085 | * work with generic timing. Simultaneously gpmc_cs_set_timings() | |
1086 | * has to be modified to handle timings in ps instead of ns | |
1087 | */ | |
1088 | static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) | |
1089 | { | |
1090 | t->cs_on /= 1000; | |
1091 | t->cs_rd_off /= 1000; | |
1092 | t->cs_wr_off /= 1000; | |
1093 | t->adv_on /= 1000; | |
1094 | t->adv_rd_off /= 1000; | |
1095 | t->adv_wr_off /= 1000; | |
1096 | t->we_on /= 1000; | |
1097 | t->we_off /= 1000; | |
1098 | t->oe_on /= 1000; | |
1099 | t->oe_off /= 1000; | |
1100 | t->page_burst_access /= 1000; | |
1101 | t->access /= 1000; | |
1102 | t->rd_cycle /= 1000; | |
1103 | t->wr_cycle /= 1000; | |
1104 | t->bus_turnaround /= 1000; | |
1105 | t->cycle2cycle_delay /= 1000; | |
1106 | t->wait_monitoring /= 1000; | |
1107 | t->clk_activation /= 1000; | |
1108 | t->wr_access /= 1000; | |
1109 | t->wr_data_mux_bus /= 1000; | |
1110 | } | |
1111 | ||
1112 | int gpmc_calc_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1113 | struct gpmc_settings *gpmc_s, |
1114 | struct gpmc_device_timings *dev_t) | |
246da26d | 1115 | { |
c3be5b45 JH |
1116 | bool mux = false, sync = false; |
1117 | ||
1118 | if (gpmc_s) { | |
1119 | mux = gpmc_s->mux_add_data ? true : false; | |
1120 | sync = (gpmc_s->sync_read || gpmc_s->sync_write); | |
1121 | } | |
1122 | ||
246da26d AM |
1123 | memset(gpmc_t, 0, sizeof(*gpmc_t)); |
1124 | ||
c3be5b45 | 1125 | gpmc_calc_common_timings(gpmc_t, dev_t, sync); |
246da26d | 1126 | |
c3be5b45 JH |
1127 | if (gpmc_s && gpmc_s->sync_read) |
1128 | gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); | |
246da26d | 1129 | else |
c3be5b45 | 1130 | gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); |
246da26d | 1131 | |
c3be5b45 JH |
1132 | if (gpmc_s && gpmc_s->sync_write) |
1133 | gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); | |
246da26d | 1134 | else |
c3be5b45 | 1135 | gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); |
246da26d AM |
1136 | |
1137 | /* TODO: remove, see function definition */ | |
1138 | gpmc_convert_ps_to_ns(gpmc_t); | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
aa8d4767 JH |
1143 | /** |
1144 | * gpmc_cs_program_settings - programs non-timing related settings | |
1145 | * @cs: GPMC chip-select to program | |
1146 | * @p: pointer to GPMC settings structure | |
1147 | * | |
1148 | * Programs non-timing related settings for a GPMC chip-select, such as | |
1149 | * bus-width, burst configuration, etc. Function should be called once | |
1150 | * for each chip-select that is being used and must be called before | |
1151 | * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1 | |
1152 | * register will be initialised to zero by this function. Returns 0 on | |
1153 | * success and appropriate negative error code on failure. | |
1154 | */ | |
1155 | int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) | |
1156 | { | |
1157 | u32 config1; | |
1158 | ||
1159 | if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { | |
1160 | pr_err("%s: invalid width %d!", __func__, p->device_width); | |
1161 | return -EINVAL; | |
1162 | } | |
1163 | ||
1164 | /* Address-data multiplexing not supported for NAND devices */ | |
1165 | if (p->device_nand && p->mux_add_data) { | |
1166 | pr_err("%s: invalid configuration!\n", __func__); | |
1167 | return -EINVAL; | |
1168 | } | |
1169 | ||
1170 | if ((p->mux_add_data > GPMC_MUX_AD) || | |
1171 | ((p->mux_add_data == GPMC_MUX_AAD) && | |
1172 | !(gpmc_capability & GPMC_HAS_MUX_AAD))) { | |
1173 | pr_err("%s: invalid multiplex configuration!\n", __func__); | |
1174 | return -EINVAL; | |
1175 | } | |
1176 | ||
1177 | /* Page/burst mode supports lengths of 4, 8 and 16 bytes */ | |
1178 | if (p->burst_read || p->burst_write) { | |
1179 | switch (p->burst_len) { | |
1180 | case GPMC_BURST_4: | |
1181 | case GPMC_BURST_8: | |
1182 | case GPMC_BURST_16: | |
1183 | break; | |
1184 | default: | |
1185 | pr_err("%s: invalid page/burst-length (%d)\n", | |
1186 | __func__, p->burst_len); | |
1187 | return -EINVAL; | |
1188 | } | |
1189 | } | |
1190 | ||
1191 | if ((p->wait_on_read || p->wait_on_write) && | |
1192 | (p->wait_pin > gpmc_nr_waitpins)) { | |
1193 | pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); | |
1194 | return -EINVAL; | |
1195 | } | |
1196 | ||
1197 | config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); | |
1198 | ||
1199 | if (p->sync_read) | |
1200 | config1 |= GPMC_CONFIG1_READTYPE_SYNC; | |
1201 | if (p->sync_write) | |
1202 | config1 |= GPMC_CONFIG1_WRITETYPE_SYNC; | |
1203 | if (p->wait_on_read) | |
1204 | config1 |= GPMC_CONFIG1_WAIT_READ_MON; | |
1205 | if (p->wait_on_write) | |
1206 | config1 |= GPMC_CONFIG1_WAIT_WRITE_MON; | |
1207 | if (p->wait_on_read || p->wait_on_write) | |
1208 | config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); | |
1209 | if (p->device_nand) | |
1210 | config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND); | |
1211 | if (p->mux_add_data) | |
1212 | config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); | |
1213 | if (p->burst_read) | |
1214 | config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP; | |
1215 | if (p->burst_write) | |
1216 | config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP; | |
1217 | if (p->burst_read || p->burst_write) { | |
1218 | config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); | |
1219 | config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; | |
1220 | } | |
1221 | ||
1222 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); | |
1223 | ||
1224 | return 0; | |
1225 | } | |
1226 | ||
bc6b1e7b DM |
1227 | #ifdef CONFIG_OF |
1228 | static struct of_device_id gpmc_dt_ids[] = { | |
1229 | { .compatible = "ti,omap2420-gpmc" }, | |
1230 | { .compatible = "ti,omap2430-gpmc" }, | |
1231 | { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ | |
1232 | { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */ | |
1233 | { .compatible = "ti,am3352-gpmc" }, /* am335x devices */ | |
1234 | { } | |
1235 | }; | |
1236 | MODULE_DEVICE_TABLE(of, gpmc_dt_ids); | |
1237 | ||
8c8a7771 JH |
1238 | /** |
1239 | * gpmc_read_settings_dt - read gpmc settings from device-tree | |
1240 | * @np: pointer to device-tree node for a gpmc child device | |
1241 | * @p: pointer to gpmc settings structure | |
1242 | * | |
1243 | * Reads the GPMC settings for a GPMC child device from device-tree and | |
1244 | * stores them in the GPMC settings structure passed. The GPMC settings | |
1245 | * structure is initialised to zero by this function and so any | |
1246 | * previously stored settings will be cleared. | |
1247 | */ | |
1248 | void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) | |
1249 | { | |
1250 | memset(p, 0, sizeof(struct gpmc_settings)); | |
1251 | ||
1252 | p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); | |
1253 | p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); | |
1254 | p->device_nand = of_property_read_bool(np, "gpmc,device-nand"); | |
1255 | of_property_read_u32(np, "gpmc,device-width", &p->device_width); | |
1256 | of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); | |
1257 | ||
1258 | if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { | |
1259 | p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); | |
1260 | p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); | |
1261 | p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); | |
1262 | if (!p->burst_read && !p->burst_write) | |
1263 | pr_warn("%s: page/burst-length set but not used!\n", | |
1264 | __func__); | |
1265 | } | |
1266 | ||
1267 | if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { | |
1268 | p->wait_on_read = of_property_read_bool(np, | |
1269 | "gpmc,wait-on-read"); | |
1270 | p->wait_on_write = of_property_read_bool(np, | |
1271 | "gpmc,wait-on-write"); | |
1272 | if (!p->wait_on_read && !p->wait_on_write) | |
1273 | pr_warn("%s: read/write wait monitoring not enabled!\n", | |
1274 | __func__); | |
1275 | } | |
1276 | } | |
1277 | ||
bc6b1e7b DM |
1278 | static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, |
1279 | struct gpmc_timings *gpmc_t) | |
1280 | { | |
d36b4cd4 JH |
1281 | struct gpmc_bool_timings *p; |
1282 | ||
1283 | if (!np || !gpmc_t) | |
1284 | return; | |
bc6b1e7b DM |
1285 | |
1286 | memset(gpmc_t, 0, sizeof(*gpmc_t)); | |
1287 | ||
1288 | /* minimum clock period for syncronous mode */ | |
d36b4cd4 | 1289 | of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); |
bc6b1e7b DM |
1290 | |
1291 | /* chip select timtings */ | |
d36b4cd4 JH |
1292 | of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); |
1293 | of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); | |
1294 | of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); | |
bc6b1e7b DM |
1295 | |
1296 | /* ADV signal timings */ | |
d36b4cd4 JH |
1297 | of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); |
1298 | of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); | |
1299 | of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); | |
bc6b1e7b DM |
1300 | |
1301 | /* WE signal timings */ | |
d36b4cd4 JH |
1302 | of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); |
1303 | of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); | |
bc6b1e7b DM |
1304 | |
1305 | /* OE signal timings */ | |
d36b4cd4 JH |
1306 | of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); |
1307 | of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); | |
bc6b1e7b DM |
1308 | |
1309 | /* access and cycle timings */ | |
d36b4cd4 JH |
1310 | of_property_read_u32(np, "gpmc,page-burst-access-ns", |
1311 | &gpmc_t->page_burst_access); | |
1312 | of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); | |
1313 | of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); | |
1314 | of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); | |
1315 | of_property_read_u32(np, "gpmc,bus-turnaround-ns", | |
1316 | &gpmc_t->bus_turnaround); | |
1317 | of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", | |
1318 | &gpmc_t->cycle2cycle_delay); | |
1319 | of_property_read_u32(np, "gpmc,wait-monitoring-ns", | |
1320 | &gpmc_t->wait_monitoring); | |
1321 | of_property_read_u32(np, "gpmc,clk-activation-ns", | |
1322 | &gpmc_t->clk_activation); | |
1323 | ||
1324 | /* only applicable to OMAP3+ */ | |
1325 | of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); | |
1326 | of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", | |
1327 | &gpmc_t->wr_data_mux_bus); | |
1328 | ||
1329 | /* bool timing parameters */ | |
1330 | p = &gpmc_t->bool_timings; | |
1331 | ||
1332 | p->cycle2cyclediffcsen = | |
1333 | of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); | |
1334 | p->cycle2cyclesamecsen = | |
1335 | of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); | |
1336 | p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); | |
1337 | p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); | |
1338 | p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); | |
1339 | p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); | |
1340 | p->time_para_granularity = | |
1341 | of_property_read_bool(np, "gpmc,time-para-granularity"); | |
bc6b1e7b DM |
1342 | } |
1343 | ||
1344 | #ifdef CONFIG_MTD_NAND | |
1345 | ||
1346 | static const char * const nand_ecc_opts[] = { | |
1347 | [OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw", | |
1348 | [OMAP_ECC_HAMMING_CODE_HW] = "hw", | |
1349 | [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode", | |
1350 | [OMAP_ECC_BCH4_CODE_HW] = "bch4", | |
1351 | [OMAP_ECC_BCH8_CODE_HW] = "bch8", | |
1352 | }; | |
1353 | ||
1354 | static int gpmc_probe_nand_child(struct platform_device *pdev, | |
1355 | struct device_node *child) | |
1356 | { | |
1357 | u32 val; | |
1358 | const char *s; | |
1359 | struct gpmc_timings gpmc_t; | |
1360 | struct omap_nand_platform_data *gpmc_nand_data; | |
1361 | ||
1362 | if (of_property_read_u32(child, "reg", &val) < 0) { | |
1363 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1364 | child->full_name); | |
1365 | return -ENODEV; | |
1366 | } | |
1367 | ||
1368 | gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data), | |
1369 | GFP_KERNEL); | |
1370 | if (!gpmc_nand_data) | |
1371 | return -ENOMEM; | |
1372 | ||
1373 | gpmc_nand_data->cs = val; | |
1374 | gpmc_nand_data->of_node = child; | |
1375 | ||
1376 | if (!of_property_read_string(child, "ti,nand-ecc-opt", &s)) | |
1377 | for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++) | |
1378 | if (!strcasecmp(s, nand_ecc_opts[val])) { | |
1379 | gpmc_nand_data->ecc_opt = val; | |
1380 | break; | |
1381 | } | |
1382 | ||
1383 | val = of_get_nand_bus_width(child); | |
1384 | if (val == 16) | |
1385 | gpmc_nand_data->devsize = NAND_BUSWIDTH_16; | |
1386 | ||
1387 | gpmc_read_timings_dt(child, &gpmc_t); | |
1388 | gpmc_nand_init(gpmc_nand_data, &gpmc_t); | |
1389 | ||
1390 | return 0; | |
1391 | } | |
1392 | #else | |
1393 | static int gpmc_probe_nand_child(struct platform_device *pdev, | |
1394 | struct device_node *child) | |
1395 | { | |
1396 | return 0; | |
1397 | } | |
1398 | #endif | |
1399 | ||
75d3625e EG |
1400 | #ifdef CONFIG_MTD_ONENAND |
1401 | static int gpmc_probe_onenand_child(struct platform_device *pdev, | |
1402 | struct device_node *child) | |
1403 | { | |
1404 | u32 val; | |
1405 | struct omap_onenand_platform_data *gpmc_onenand_data; | |
1406 | ||
1407 | if (of_property_read_u32(child, "reg", &val) < 0) { | |
1408 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1409 | child->full_name); | |
1410 | return -ENODEV; | |
1411 | } | |
1412 | ||
1413 | gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data), | |
1414 | GFP_KERNEL); | |
1415 | if (!gpmc_onenand_data) | |
1416 | return -ENOMEM; | |
1417 | ||
1418 | gpmc_onenand_data->cs = val; | |
1419 | gpmc_onenand_data->of_node = child; | |
1420 | gpmc_onenand_data->dma_channel = -1; | |
1421 | ||
1422 | if (!of_property_read_u32(child, "dma-channel", &val)) | |
1423 | gpmc_onenand_data->dma_channel = val; | |
1424 | ||
1425 | gpmc_onenand_init(gpmc_onenand_data); | |
1426 | ||
1427 | return 0; | |
1428 | } | |
1429 | #else | |
1430 | static int gpmc_probe_onenand_child(struct platform_device *pdev, | |
1431 | struct device_node *child) | |
1432 | { | |
1433 | return 0; | |
1434 | } | |
1435 | #endif | |
1436 | ||
cdd6928c JH |
1437 | /** |
1438 | * gpmc_probe_nor_child - configures the gpmc for a nor device | |
1439 | * @pdev: pointer to gpmc platform device | |
1440 | * @child: pointer to device-tree node for nor device | |
1441 | * | |
1442 | * Allocates and configures a GPMC chip-select for a NOR flash device. | |
1443 | * Returns 0 on success and appropriate negative error code on failure. | |
1444 | */ | |
1445 | static int gpmc_probe_nor_child(struct platform_device *pdev, | |
1446 | struct device_node *child) | |
1447 | { | |
1448 | struct gpmc_settings gpmc_s; | |
1449 | struct gpmc_timings gpmc_t; | |
1450 | struct resource res; | |
1451 | unsigned long base; | |
1452 | int ret, cs; | |
1453 | ||
1454 | if (of_property_read_u32(child, "reg", &cs) < 0) { | |
1455 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1456 | child->full_name); | |
1457 | return -ENODEV; | |
1458 | } | |
1459 | ||
1460 | if (of_address_to_resource(child, 0, &res) < 0) { | |
1461 | dev_err(&pdev->dev, "%s has malformed 'reg' property\n", | |
1462 | child->full_name); | |
1463 | return -ENODEV; | |
1464 | } | |
1465 | ||
1466 | ret = gpmc_cs_request(cs, resource_size(&res), &base); | |
1467 | if (ret < 0) { | |
1468 | dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); | |
1469 | return ret; | |
1470 | } | |
1471 | ||
1472 | /* | |
1473 | * FIXME: gpmc_cs_request() will map the CS to an arbitary | |
1474 | * location in the gpmc address space. When booting with | |
1475 | * device-tree we want the NOR flash to be mapped to the | |
1476 | * location specified in the device-tree blob. So remap the | |
1477 | * CS to this location. Once DT migration is complete should | |
1478 | * just make gpmc_cs_request() map a specific address. | |
1479 | */ | |
1480 | ret = gpmc_cs_remap(cs, res.start); | |
1481 | if (ret < 0) { | |
1482 | dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n", | |
1483 | cs, res.start); | |
1484 | goto err; | |
1485 | } | |
1486 | ||
1487 | gpmc_read_settings_dt(child, &gpmc_s); | |
1488 | ||
1489 | ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width); | |
1490 | if (ret < 0) | |
1491 | goto err; | |
1492 | ||
1493 | ret = gpmc_cs_program_settings(cs, &gpmc_s); | |
1494 | if (ret < 0) | |
1495 | goto err; | |
1496 | ||
1497 | gpmc_read_timings_dt(child, &gpmc_t); | |
1498 | gpmc_cs_set_timings(cs, &gpmc_t); | |
1499 | ||
1500 | if (of_platform_device_create(child, NULL, &pdev->dev)) | |
1501 | return 0; | |
1502 | ||
1503 | dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name); | |
1504 | ||
1505 | err: | |
1506 | gpmc_cs_free(cs); | |
1507 | ||
1508 | return ret; | |
1509 | } | |
1510 | ||
bc6b1e7b DM |
1511 | static int gpmc_probe_dt(struct platform_device *pdev) |
1512 | { | |
1513 | int ret; | |
1514 | struct device_node *child; | |
1515 | const struct of_device_id *of_id = | |
1516 | of_match_device(gpmc_dt_ids, &pdev->dev); | |
1517 | ||
1518 | if (!of_id) | |
1519 | return 0; | |
1520 | ||
9f833156 JH |
1521 | ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", |
1522 | &gpmc_nr_waitpins); | |
1523 | if (ret < 0) { | |
1524 | pr_err("%s: number of wait pins not found!\n", __func__); | |
1525 | return ret; | |
1526 | } | |
1527 | ||
bc6b1e7b DM |
1528 | for_each_node_by_name(child, "nand") { |
1529 | ret = gpmc_probe_nand_child(pdev, child); | |
a1672370 EG |
1530 | if (ret < 0) { |
1531 | of_node_put(child); | |
bc6b1e7b | 1532 | return ret; |
a1672370 | 1533 | } |
bc6b1e7b DM |
1534 | } |
1535 | ||
75d3625e EG |
1536 | for_each_node_by_name(child, "onenand") { |
1537 | ret = gpmc_probe_onenand_child(pdev, child); | |
1538 | if (ret < 0) { | |
1539 | of_node_put(child); | |
1540 | return ret; | |
1541 | } | |
1542 | } | |
cdd6928c JH |
1543 | |
1544 | for_each_node_by_name(child, "nor") { | |
1545 | ret = gpmc_probe_nor_child(pdev, child); | |
1546 | if (ret < 0) { | |
1547 | of_node_put(child); | |
1548 | return ret; | |
1549 | } | |
1550 | } | |
1551 | ||
bc6b1e7b DM |
1552 | return 0; |
1553 | } | |
1554 | #else | |
1555 | static int gpmc_probe_dt(struct platform_device *pdev) | |
1556 | { | |
1557 | return 0; | |
1558 | } | |
1559 | #endif | |
1560 | ||
351a102d | 1561 | static int gpmc_probe(struct platform_device *pdev) |
4bbbc1ad | 1562 | { |
8119024e | 1563 | int rc; |
6b6c32fc | 1564 | u32 l; |
da496873 | 1565 | struct resource *res; |
4bbbc1ad | 1566 | |
da496873 AM |
1567 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1568 | if (res == NULL) | |
1569 | return -ENOENT; | |
8d08436d | 1570 | |
da496873 AM |
1571 | phys_base = res->start; |
1572 | mem_size = resource_size(res); | |
fd1dc87d | 1573 | |
5857bd98 TR |
1574 | gpmc_base = devm_ioremap_resource(&pdev->dev, res); |
1575 | if (IS_ERR(gpmc_base)) | |
1576 | return PTR_ERR(gpmc_base); | |
da496873 AM |
1577 | |
1578 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1579 | if (res == NULL) | |
1580 | dev_warn(&pdev->dev, "Failed to get resource: irq\n"); | |
1581 | else | |
1582 | gpmc_irq = res->start; | |
1583 | ||
1584 | gpmc_l3_clk = clk_get(&pdev->dev, "fck"); | |
1585 | if (IS_ERR(gpmc_l3_clk)) { | |
1586 | dev_err(&pdev->dev, "error: clk_get\n"); | |
1587 | gpmc_irq = 0; | |
1588 | return PTR_ERR(gpmc_l3_clk); | |
fd1dc87d PW |
1589 | } |
1590 | ||
4d7cb45e | 1591 | clk_prepare_enable(gpmc_l3_clk); |
1daa8c1d | 1592 | |
da496873 AM |
1593 | gpmc_dev = &pdev->dev; |
1594 | ||
4bbbc1ad | 1595 | l = gpmc_read_reg(GPMC_REVISION); |
aa8d4767 JH |
1596 | |
1597 | /* | |
1598 | * FIXME: Once device-tree migration is complete the below flags | |
1599 | * should be populated based upon the device-tree compatible | |
1600 | * string. For now just use the IP revision. OMAP3+ devices have | |
1601 | * the wr_access and wr_data_mux_bus register fields. OMAP4+ | |
1602 | * devices support the addr-addr-data multiplex protocol. | |
1603 | * | |
1604 | * GPMC IP revisions: | |
1605 | * - OMAP24xx = 2.0 | |
1606 | * - OMAP3xxx = 5.0 | |
1607 | * - OMAP44xx/54xx/AM335x = 6.0 | |
1608 | */ | |
da496873 AM |
1609 | if (GPMC_REVISION_MAJOR(l) > 0x4) |
1610 | gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; | |
aa8d4767 JH |
1611 | if (GPMC_REVISION_MAJOR(l) > 0x5) |
1612 | gpmc_capability |= GPMC_HAS_MUX_AAD; | |
da496873 AM |
1613 | dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), |
1614 | GPMC_REVISION_MINOR(l)); | |
1615 | ||
8119024e | 1616 | rc = gpmc_mem_init(); |
71856843 | 1617 | if (rc < 0) { |
8119024e JH |
1618 | clk_disable_unprepare(gpmc_l3_clk); |
1619 | clk_put(gpmc_l3_clk); | |
1620 | dev_err(gpmc_dev, "failed to reserve memory\n"); | |
1621 | return rc; | |
1622 | } | |
db97eb7d | 1623 | |
71856843 | 1624 | if (gpmc_setup_irq() < 0) |
da496873 AM |
1625 | dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); |
1626 | ||
31d9adca JH |
1627 | /* Now the GPMC is initialised, unreserve the chip-selects */ |
1628 | gpmc_cs_map = 0; | |
1629 | ||
9f833156 JH |
1630 | if (!pdev->dev.of_node) |
1631 | gpmc_nr_waitpins = GPMC_NR_WAITPINS; | |
1632 | ||
bc6b1e7b DM |
1633 | rc = gpmc_probe_dt(pdev); |
1634 | if (rc < 0) { | |
1635 | clk_disable_unprepare(gpmc_l3_clk); | |
1636 | clk_put(gpmc_l3_clk); | |
1637 | dev_err(gpmc_dev, "failed to probe DT parameters\n"); | |
1638 | return rc; | |
1639 | } | |
1640 | ||
da496873 AM |
1641 | return 0; |
1642 | } | |
1643 | ||
351a102d | 1644 | static int gpmc_remove(struct platform_device *pdev) |
da496873 AM |
1645 | { |
1646 | gpmc_free_irq(); | |
1647 | gpmc_mem_exit(); | |
1648 | gpmc_dev = NULL; | |
1649 | return 0; | |
1650 | } | |
1651 | ||
1652 | static struct platform_driver gpmc_driver = { | |
1653 | .probe = gpmc_probe, | |
351a102d | 1654 | .remove = gpmc_remove, |
da496873 AM |
1655 | .driver = { |
1656 | .name = DEVICE_NAME, | |
1657 | .owner = THIS_MODULE, | |
bc6b1e7b | 1658 | .of_match_table = of_match_ptr(gpmc_dt_ids), |
da496873 AM |
1659 | }, |
1660 | }; | |
1661 | ||
1662 | static __init int gpmc_init(void) | |
1663 | { | |
1664 | return platform_driver_register(&gpmc_driver); | |
1665 | } | |
1666 | ||
1667 | static __exit void gpmc_exit(void) | |
1668 | { | |
1669 | platform_driver_unregister(&gpmc_driver); | |
1670 | ||
db97eb7d | 1671 | } |
da496873 | 1672 | |
b76c8b19 | 1673 | omap_postcore_initcall(gpmc_init); |
da496873 | 1674 | module_exit(gpmc_exit); |
db97eb7d | 1675 | |
4be48fd5 AM |
1676 | static int __init omap_gpmc_init(void) |
1677 | { | |
1678 | struct omap_hwmod *oh; | |
1679 | struct platform_device *pdev; | |
1680 | char *oh_name = "gpmc"; | |
1681 | ||
2f98ca89 DM |
1682 | /* |
1683 | * if the board boots up with a populated DT, do not | |
1684 | * manually add the device from this initcall | |
1685 | */ | |
1686 | if (of_have_populated_dt()) | |
1687 | return -ENODEV; | |
1688 | ||
4be48fd5 AM |
1689 | oh = omap_hwmod_lookup(oh_name); |
1690 | if (!oh) { | |
1691 | pr_err("Could not look up %s\n", oh_name); | |
1692 | return -ENODEV; | |
1693 | } | |
1694 | ||
c1d1cd59 | 1695 | pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0); |
4be48fd5 AM |
1696 | WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); |
1697 | ||
1698 | return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; | |
1699 | } | |
b76c8b19 | 1700 | omap_postcore_initcall(omap_gpmc_init); |
4be48fd5 | 1701 | |
db97eb7d SG |
1702 | static irqreturn_t gpmc_handle_irq(int irq, void *dev) |
1703 | { | |
6b6c32fc AM |
1704 | int i; |
1705 | u32 regval; | |
1706 | ||
1707 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
1708 | ||
1709 | if (!regval) | |
1710 | return IRQ_NONE; | |
1711 | ||
1712 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
1713 | if (regval & gpmc_client_irq[i].bitmask) | |
1714 | generic_handle_irq(gpmc_client_irq[i].irq); | |
db97eb7d | 1715 | |
6b6c32fc | 1716 | gpmc_write_reg(GPMC_IRQSTATUS, regval); |
db97eb7d SG |
1717 | |
1718 | return IRQ_HANDLED; | |
4bbbc1ad | 1719 | } |
a2d3e7ba RN |
1720 | |
1721 | #ifdef CONFIG_ARCH_OMAP3 | |
1722 | static struct omap3_gpmc_regs gpmc_context; | |
1723 | ||
b2fa3b7c | 1724 | void omap3_gpmc_save_context(void) |
a2d3e7ba RN |
1725 | { |
1726 | int i; | |
b2fa3b7c | 1727 | |
a2d3e7ba RN |
1728 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); |
1729 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | |
1730 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | |
1731 | gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); | |
1732 | gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
1733 | gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); | |
1734 | gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); | |
1735 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
1736 | gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); | |
1737 | if (gpmc_context.cs_context[i].is_valid) { | |
1738 | gpmc_context.cs_context[i].config1 = | |
1739 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); | |
1740 | gpmc_context.cs_context[i].config2 = | |
1741 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); | |
1742 | gpmc_context.cs_context[i].config3 = | |
1743 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); | |
1744 | gpmc_context.cs_context[i].config4 = | |
1745 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); | |
1746 | gpmc_context.cs_context[i].config5 = | |
1747 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); | |
1748 | gpmc_context.cs_context[i].config6 = | |
1749 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); | |
1750 | gpmc_context.cs_context[i].config7 = | |
1751 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); | |
1752 | } | |
1753 | } | |
1754 | } | |
1755 | ||
b2fa3b7c | 1756 | void omap3_gpmc_restore_context(void) |
a2d3e7ba RN |
1757 | { |
1758 | int i; | |
b2fa3b7c | 1759 | |
a2d3e7ba RN |
1760 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); |
1761 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | |
1762 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | |
1763 | gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); | |
1764 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); | |
1765 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); | |
1766 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); | |
1767 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
1768 | if (gpmc_context.cs_context[i].is_valid) { | |
1769 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, | |
1770 | gpmc_context.cs_context[i].config1); | |
1771 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, | |
1772 | gpmc_context.cs_context[i].config2); | |
1773 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, | |
1774 | gpmc_context.cs_context[i].config3); | |
1775 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, | |
1776 | gpmc_context.cs_context[i].config4); | |
1777 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, | |
1778 | gpmc_context.cs_context[i].config5); | |
1779 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, | |
1780 | gpmc_context.cs_context[i].config6); | |
1781 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, | |
1782 | gpmc_context.cs_context[i].config7); | |
1783 | } | |
1784 | } | |
1785 | } | |
1786 | #endif /* CONFIG_ARCH_OMAP3 */ |