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Commit | Line | Data |
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4bbbc1ad JY |
1 | /* |
2 | * GPMC support functions | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * Author: Juha Yrjola | |
7 | * | |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
10 | * | |
4bbbc1ad JY |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
fd1dc87d PW |
15 | #undef DEBUG |
16 | ||
db97eb7d | 17 | #include <linux/irq.h> |
4bbbc1ad JY |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/clk.h> | |
f37e4580 ID |
22 | #include <linux/ioport.h> |
23 | #include <linux/spinlock.h> | |
fced80c7 | 24 | #include <linux/io.h> |
fd1dc87d | 25 | #include <linux/module.h> |
db97eb7d | 26 | #include <linux/interrupt.h> |
da496873 | 27 | #include <linux/platform_device.h> |
bc6b1e7b | 28 | #include <linux/of.h> |
cdd6928c | 29 | #include <linux/of_address.h> |
bc6b1e7b DM |
30 | #include <linux/of_mtd.h> |
31 | #include <linux/of_device.h> | |
32 | #include <linux/mtd/nand.h> | |
b3f5525c | 33 | #include <linux/pm_runtime.h> |
4bbbc1ad | 34 | |
bc3668ea | 35 | #include <linux/platform_data/mtd-nand-omap2.h> |
4bbbc1ad | 36 | |
7f245162 | 37 | #include <asm/mach-types.h> |
72d0f1c3 | 38 | |
dbc04161 | 39 | #include "soc.h" |
7d7e1eba | 40 | #include "common.h" |
25c7d49e | 41 | #include "omap_device.h" |
3ef5d007 | 42 | #include "gpmc.h" |
bc6b1e7b | 43 | #include "gpmc-nand.h" |
75d3625e | 44 | #include "gpmc-onenand.h" |
7d7e1eba | 45 | |
4be48fd5 AM |
46 | #define DEVICE_NAME "omap-gpmc" |
47 | ||
fd1dc87d | 48 | /* GPMC register offsets */ |
4bbbc1ad JY |
49 | #define GPMC_REVISION 0x00 |
50 | #define GPMC_SYSCONFIG 0x10 | |
51 | #define GPMC_SYSSTATUS 0x14 | |
52 | #define GPMC_IRQSTATUS 0x18 | |
53 | #define GPMC_IRQENABLE 0x1c | |
54 | #define GPMC_TIMEOUT_CONTROL 0x40 | |
55 | #define GPMC_ERR_ADDRESS 0x44 | |
56 | #define GPMC_ERR_TYPE 0x48 | |
57 | #define GPMC_CONFIG 0x50 | |
58 | #define GPMC_STATUS 0x54 | |
59 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | |
60 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | |
15e02a3b | 61 | #define GPMC_PREFETCH_CONTROL 0x1ec |
4bbbc1ad JY |
62 | #define GPMC_PREFETCH_STATUS 0x1f0 |
63 | #define GPMC_ECC_CONFIG 0x1f4 | |
64 | #define GPMC_ECC_CONTROL 0x1f8 | |
65 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | |
948d38e7 | 66 | #define GPMC_ECC1_RESULT 0x200 |
8d602cf5 | 67 | #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ |
2fdf0c98 AM |
68 | #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ |
69 | #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ | |
70 | #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ | |
27c9fd60 | 71 | #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */ |
72 | #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */ | |
73 | #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */ | |
4bbbc1ad | 74 | |
2c65e744 YY |
75 | /* GPMC ECC control settings */ |
76 | #define GPMC_ECC_CTRL_ECCCLEAR 0x100 | |
77 | #define GPMC_ECC_CTRL_ECCDISABLE 0x000 | |
78 | #define GPMC_ECC_CTRL_ECCREG1 0x001 | |
79 | #define GPMC_ECC_CTRL_ECCREG2 0x002 | |
80 | #define GPMC_ECC_CTRL_ECCREG3 0x003 | |
81 | #define GPMC_ECC_CTRL_ECCREG4 0x004 | |
82 | #define GPMC_ECC_CTRL_ECCREG5 0x005 | |
83 | #define GPMC_ECC_CTRL_ECCREG6 0x006 | |
84 | #define GPMC_ECC_CTRL_ECCREG7 0x007 | |
85 | #define GPMC_ECC_CTRL_ECCREG8 0x008 | |
86 | #define GPMC_ECC_CTRL_ECCREG9 0x009 | |
87 | ||
e378d22b RQ |
88 | #define GPMC_CONFIG_LIMITEDADDRESS BIT(1) |
89 | ||
559d94b0 AM |
90 | #define GPMC_CONFIG2_CSEXTRADELAY BIT(7) |
91 | #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) | |
92 | #define GPMC_CONFIG4_OEEXTRADELAY BIT(7) | |
93 | #define GPMC_CONFIG4_WEEXTRADELAY BIT(23) | |
94 | #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6) | |
95 | #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7) | |
96 | ||
948d38e7 | 97 | #define GPMC_CS0_OFFSET 0x60 |
4bbbc1ad | 98 | #define GPMC_CS_SIZE 0x30 |
2fdf0c98 | 99 | #define GPMC_BCH_SIZE 0x10 |
4bbbc1ad | 100 | |
f37e4580 | 101 | #define GPMC_MEM_END 0x3FFFFFFF |
f37e4580 ID |
102 | |
103 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ | |
104 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ | |
105 | ||
59e9c5ae | 106 | #define CS_NUM_SHIFT 24 |
107 | #define ENABLE_PREFETCH (0x1 << 7) | |
108 | #define DMA_MPU_MODE 2 | |
109 | ||
da496873 AM |
110 | #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) |
111 | #define GPMC_REVISION_MINOR(l) (l & 0xf) | |
112 | ||
113 | #define GPMC_HAS_WR_ACCESS 0x1 | |
114 | #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 | |
aa8d4767 | 115 | #define GPMC_HAS_MUX_AAD 0x4 |
da496873 | 116 | |
9f833156 JH |
117 | #define GPMC_NR_WAITPINS 4 |
118 | ||
6b6c32fc AM |
119 | /* XXX: Only NAND irq has been considered,currently these are the only ones used |
120 | */ | |
121 | #define GPMC_NR_IRQ 2 | |
122 | ||
123 | struct gpmc_client_irq { | |
124 | unsigned irq; | |
125 | u32 bitmask; | |
126 | }; | |
127 | ||
a2d3e7ba RN |
128 | /* Structure to save gpmc cs context */ |
129 | struct gpmc_cs_config { | |
130 | u32 config1; | |
131 | u32 config2; | |
132 | u32 config3; | |
133 | u32 config4; | |
134 | u32 config5; | |
135 | u32 config6; | |
136 | u32 config7; | |
137 | int is_valid; | |
138 | }; | |
139 | ||
140 | /* | |
141 | * Structure to save/restore gpmc context | |
142 | * to support core off on OMAP3 | |
143 | */ | |
144 | struct omap3_gpmc_regs { | |
145 | u32 sysconfig; | |
146 | u32 irqenable; | |
147 | u32 timeout_ctrl; | |
148 | u32 config; | |
149 | u32 prefetch_config1; | |
150 | u32 prefetch_config2; | |
151 | u32 prefetch_control; | |
152 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | |
153 | }; | |
154 | ||
6b6c32fc AM |
155 | static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; |
156 | static struct irq_chip gpmc_irq_chip; | |
af072196 | 157 | static int gpmc_irq_start; |
6b6c32fc | 158 | |
f37e4580 ID |
159 | static struct resource gpmc_mem_root; |
160 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | |
87b247c4 | 161 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
6797b4fe JH |
162 | /* Define chip-selects as reserved by default until probe completes */ |
163 | static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); | |
f34f3716 | 164 | static unsigned int gpmc_cs_num = GPMC_CS_NUM; |
9f833156 | 165 | static unsigned int gpmc_nr_waitpins; |
da496873 AM |
166 | static struct device *gpmc_dev; |
167 | static int gpmc_irq; | |
168 | static resource_size_t phys_base, mem_size; | |
169 | static unsigned gpmc_capability; | |
fd1dc87d | 170 | static void __iomem *gpmc_base; |
4bbbc1ad | 171 | |
fd1dc87d | 172 | static struct clk *gpmc_l3_clk; |
4bbbc1ad | 173 | |
db97eb7d SG |
174 | static irqreturn_t gpmc_handle_irq(int irq, void *dev); |
175 | ||
4bbbc1ad JY |
176 | static void gpmc_write_reg(int idx, u32 val) |
177 | { | |
edfaf05c | 178 | writel_relaxed(val, gpmc_base + idx); |
4bbbc1ad JY |
179 | } |
180 | ||
181 | static u32 gpmc_read_reg(int idx) | |
182 | { | |
edfaf05c | 183 | return readl_relaxed(gpmc_base + idx); |
4bbbc1ad JY |
184 | } |
185 | ||
186 | void gpmc_cs_write_reg(int cs, int idx, u32 val) | |
187 | { | |
188 | void __iomem *reg_addr; | |
189 | ||
948d38e7 | 190 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
edfaf05c | 191 | writel_relaxed(val, reg_addr); |
4bbbc1ad JY |
192 | } |
193 | ||
3fc089e7 | 194 | static u32 gpmc_cs_read_reg(int cs, int idx) |
4bbbc1ad | 195 | { |
fd1dc87d PW |
196 | void __iomem *reg_addr; |
197 | ||
948d38e7 | 198 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
edfaf05c | 199 | return readl_relaxed(reg_addr); |
4bbbc1ad JY |
200 | } |
201 | ||
fd1dc87d | 202 | /* TODO: Add support for gpmc_fck to clock framework and use it */ |
3fc089e7 | 203 | static unsigned long gpmc_get_fclk_period(void) |
4bbbc1ad | 204 | { |
fd1dc87d PW |
205 | unsigned long rate = clk_get_rate(gpmc_l3_clk); |
206 | ||
207 | if (rate == 0) { | |
208 | printk(KERN_WARNING "gpmc_l3_clk not enabled\n"); | |
209 | return 0; | |
210 | } | |
211 | ||
212 | rate /= 1000; | |
213 | rate = 1000000000 / rate; /* In picoseconds */ | |
214 | ||
215 | return rate; | |
4bbbc1ad JY |
216 | } |
217 | ||
3fc089e7 | 218 | static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) |
4bbbc1ad JY |
219 | { |
220 | unsigned long tick_ps; | |
221 | ||
222 | /* Calculate in picosecs to yield more exact results */ | |
223 | tick_ps = gpmc_get_fclk_period(); | |
224 | ||
225 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | |
226 | } | |
227 | ||
3fc089e7 | 228 | static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) |
a3551f5b AH |
229 | { |
230 | unsigned long tick_ps; | |
231 | ||
232 | /* Calculate in picosecs to yield more exact results */ | |
233 | tick_ps = gpmc_get_fclk_period(); | |
234 | ||
235 | return (time_ps + tick_ps - 1) / tick_ps; | |
236 | } | |
237 | ||
fd1dc87d PW |
238 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) |
239 | { | |
240 | return ticks * gpmc_get_fclk_period() / 1000; | |
241 | } | |
242 | ||
246da26d AM |
243 | static unsigned int gpmc_ticks_to_ps(unsigned int ticks) |
244 | { | |
245 | return ticks * gpmc_get_fclk_period(); | |
246 | } | |
247 | ||
248 | static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps) | |
249 | { | |
250 | unsigned long ticks = gpmc_ps_to_ticks(time_ps); | |
251 | ||
252 | return ticks * gpmc_get_fclk_period(); | |
253 | } | |
254 | ||
559d94b0 AM |
255 | static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) |
256 | { | |
257 | u32 l; | |
258 | ||
259 | l = gpmc_cs_read_reg(cs, reg); | |
260 | if (value) | |
261 | l |= mask; | |
262 | else | |
263 | l &= ~mask; | |
264 | gpmc_cs_write_reg(cs, reg, l); | |
265 | } | |
266 | ||
267 | static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) | |
268 | { | |
269 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, | |
270 | GPMC_CONFIG1_TIME_PARA_GRAN, | |
271 | p->time_para_granularity); | |
272 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, | |
273 | GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); | |
274 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, | |
275 | GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); | |
276 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | |
277 | GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); | |
278 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | |
279 | GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay); | |
280 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, | |
281 | GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, | |
282 | p->cycle2cyclesamecsen); | |
283 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, | |
284 | GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, | |
285 | p->cycle2cyclediffcsen); | |
286 | } | |
287 | ||
4bbbc1ad | 288 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, |
2aab6468 | 289 | int time, const char *name) |
4bbbc1ad JY |
290 | { |
291 | u32 l; | |
292 | int ticks, mask, nr_bits; | |
293 | ||
294 | if (time == 0) | |
295 | ticks = 0; | |
296 | else | |
297 | ticks = gpmc_ns_to_ticks(time); | |
298 | nr_bits = end_bit - st_bit + 1; | |
80323742 RQ |
299 | mask = (1 << nr_bits) - 1; |
300 | ||
301 | if (ticks > mask) { | |
302 | pr_err("%s: GPMC error! CS%d: %s: %d ns, %d ticks > %d\n", | |
303 | __func__, cs, name, time, ticks, mask); | |
304 | ||
4bbbc1ad | 305 | return -1; |
1c22cc13 | 306 | } |
4bbbc1ad | 307 | |
4bbbc1ad JY |
308 | l = gpmc_cs_read_reg(cs, reg); |
309 | #ifdef DEBUG | |
1c22cc13 DB |
310 | printk(KERN_INFO |
311 | "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", | |
2aab6468 | 312 | cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000, |
1c22cc13 | 313 | (l >> st_bit) & mask, time); |
4bbbc1ad JY |
314 | #endif |
315 | l &= ~(mask << st_bit); | |
316 | l |= ticks << st_bit; | |
317 | gpmc_cs_write_reg(cs, reg, l); | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
4bbbc1ad JY |
322 | #define GPMC_SET_ONE(reg, st, end, field) \ |
323 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ | |
324 | t->field, #field) < 0) \ | |
325 | return -1 | |
4bbbc1ad | 326 | |
1b47ca1a | 327 | int gpmc_calc_divider(unsigned int sync_clk) |
4bbbc1ad JY |
328 | { |
329 | int div; | |
330 | u32 l; | |
331 | ||
a3551f5b | 332 | l = sync_clk + (gpmc_get_fclk_period() - 1); |
4bbbc1ad JY |
333 | div = l / gpmc_get_fclk_period(); |
334 | if (div > 4) | |
335 | return -1; | |
1c22cc13 | 336 | if (div <= 0) |
4bbbc1ad JY |
337 | div = 1; |
338 | ||
339 | return div; | |
340 | } | |
341 | ||
342 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) | |
343 | { | |
344 | int div; | |
345 | u32 l; | |
346 | ||
1b47ca1a | 347 | div = gpmc_calc_divider(t->sync_clk); |
4bbbc1ad | 348 | if (div < 0) |
a032d33b | 349 | return div; |
4bbbc1ad JY |
350 | |
351 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); | |
352 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | |
353 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | |
354 | ||
355 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | |
356 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | |
357 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | |
358 | ||
359 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | |
360 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | |
361 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); | |
362 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | |
363 | ||
364 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | |
365 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | |
366 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | |
367 | ||
368 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | |
369 | ||
559d94b0 AM |
370 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround); |
371 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay); | |
372 | ||
373 | GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring); | |
374 | GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation); | |
375 | ||
da496873 | 376 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) |
cc26b3b0 | 377 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); |
da496873 | 378 | if (gpmc_capability & GPMC_HAS_WR_ACCESS) |
cc26b3b0 | 379 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); |
cc26b3b0 | 380 | |
1c22cc13 DB |
381 | /* caller is expected to have initialized CONFIG1 to cover |
382 | * at least sync vs async | |
383 | */ | |
384 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
385 | if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { | |
4bbbc1ad | 386 | #ifdef DEBUG |
1c22cc13 DB |
387 | printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", |
388 | cs, (div * gpmc_get_fclk_period()) / 1000, div); | |
4bbbc1ad | 389 | #endif |
1c22cc13 DB |
390 | l &= ~0x03; |
391 | l |= (div - 1); | |
392 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); | |
393 | } | |
4bbbc1ad | 394 | |
559d94b0 AM |
395 | gpmc_cs_bool_timings(cs, &t->bool_timings); |
396 | ||
4bbbc1ad JY |
397 | return 0; |
398 | } | |
399 | ||
c71f8e9b | 400 | static int gpmc_cs_enable_mem(int cs, u32 base, u32 size) |
f37e4580 ID |
401 | { |
402 | u32 l; | |
403 | u32 mask; | |
404 | ||
c71f8e9b JH |
405 | /* |
406 | * Ensure that base address is aligned on a | |
407 | * boundary equal to or greater than size. | |
408 | */ | |
409 | if (base & (size - 1)) | |
410 | return -EINVAL; | |
411 | ||
f37e4580 ID |
412 | mask = (1 << GPMC_SECTION_SHIFT) - size; |
413 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
414 | l &= ~0x3f; | |
415 | l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; | |
416 | l &= ~(0x0f << 8); | |
417 | l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; | |
a2d3e7ba | 418 | l |= GPMC_CONFIG7_CSVALID; |
f37e4580 | 419 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
c71f8e9b JH |
420 | |
421 | return 0; | |
f37e4580 ID |
422 | } |
423 | ||
424 | static void gpmc_cs_disable_mem(int cs) | |
425 | { | |
426 | u32 l; | |
427 | ||
428 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 429 | l &= ~GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
430 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
431 | } | |
432 | ||
433 | static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) | |
434 | { | |
435 | u32 l; | |
436 | u32 mask; | |
437 | ||
438 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
439 | *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; | |
440 | mask = (l >> 8) & 0x0f; | |
441 | *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); | |
442 | } | |
443 | ||
444 | static int gpmc_cs_mem_enabled(int cs) | |
445 | { | |
446 | u32 l; | |
447 | ||
448 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 449 | return l & GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
450 | } |
451 | ||
f5d8edaf | 452 | static void gpmc_cs_set_reserved(int cs, int reserved) |
4bbbc1ad | 453 | { |
f37e4580 ID |
454 | gpmc_cs_map &= ~(1 << cs); |
455 | gpmc_cs_map |= (reserved ? 1 : 0) << cs; | |
456 | } | |
457 | ||
ae9d908a | 458 | static bool gpmc_cs_reserved(int cs) |
f37e4580 ID |
459 | { |
460 | return gpmc_cs_map & (1 << cs); | |
461 | } | |
462 | ||
463 | static unsigned long gpmc_mem_align(unsigned long size) | |
464 | { | |
465 | int order; | |
466 | ||
467 | size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); | |
468 | order = GPMC_CHUNK_SHIFT - 1; | |
469 | do { | |
470 | size >>= 1; | |
471 | order++; | |
472 | } while (size); | |
473 | size = 1 << order; | |
474 | return size; | |
475 | } | |
476 | ||
477 | static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) | |
478 | { | |
479 | struct resource *res = &gpmc_cs_mem[cs]; | |
480 | int r; | |
481 | ||
482 | size = gpmc_mem_align(size); | |
483 | spin_lock(&gpmc_mem_lock); | |
484 | res->start = base; | |
485 | res->end = base + size - 1; | |
486 | r = request_resource(&gpmc_mem_root, res); | |
487 | spin_unlock(&gpmc_mem_lock); | |
488 | ||
489 | return r; | |
490 | } | |
491 | ||
da496873 AM |
492 | static int gpmc_cs_delete_mem(int cs) |
493 | { | |
494 | struct resource *res = &gpmc_cs_mem[cs]; | |
495 | int r; | |
496 | ||
497 | spin_lock(&gpmc_mem_lock); | |
efe80723 | 498 | r = release_resource(res); |
da496873 AM |
499 | res->start = 0; |
500 | res->end = 0; | |
501 | spin_unlock(&gpmc_mem_lock); | |
502 | ||
503 | return r; | |
504 | } | |
505 | ||
cdd6928c JH |
506 | /** |
507 | * gpmc_cs_remap - remaps a chip-select physical base address | |
508 | * @cs: chip-select to remap | |
509 | * @base: physical base address to re-map chip-select to | |
510 | * | |
511 | * Re-maps a chip-select to a new physical base address specified by | |
512 | * "base". Returns 0 on success and appropriate negative error code | |
513 | * on failure. | |
514 | */ | |
515 | static int gpmc_cs_remap(int cs, u32 base) | |
516 | { | |
517 | int ret; | |
518 | u32 old_base, size; | |
519 | ||
f34f3716 GP |
520 | if (cs > gpmc_cs_num) { |
521 | pr_err("%s: requested chip-select is disabled\n", __func__); | |
cdd6928c | 522 | return -ENODEV; |
f34f3716 | 523 | } |
fb677ef7 TL |
524 | |
525 | /* | |
526 | * Make sure we ignore any device offsets from the GPMC partition | |
527 | * allocated for the chip select and that the new base confirms | |
528 | * to the GPMC 16MB minimum granularity. | |
529 | */ | |
530 | base &= ~(SZ_16M - 1); | |
531 | ||
cdd6928c JH |
532 | gpmc_cs_get_memconf(cs, &old_base, &size); |
533 | if (base == old_base) | |
534 | return 0; | |
535 | gpmc_cs_disable_mem(cs); | |
536 | ret = gpmc_cs_delete_mem(cs); | |
537 | if (ret < 0) | |
538 | return ret; | |
539 | ret = gpmc_cs_insert_mem(cs, base, size); | |
540 | if (ret < 0) | |
541 | return ret; | |
c71f8e9b JH |
542 | ret = gpmc_cs_enable_mem(cs, base, size); |
543 | if (ret < 0) | |
544 | return ret; | |
cdd6928c JH |
545 | |
546 | return 0; | |
547 | } | |
548 | ||
f37e4580 ID |
549 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) |
550 | { | |
551 | struct resource *res = &gpmc_cs_mem[cs]; | |
552 | int r = -1; | |
553 | ||
f34f3716 GP |
554 | if (cs > gpmc_cs_num) { |
555 | pr_err("%s: requested chip-select is disabled\n", __func__); | |
f37e4580 | 556 | return -ENODEV; |
f34f3716 | 557 | } |
f37e4580 ID |
558 | size = gpmc_mem_align(size); |
559 | if (size > (1 << GPMC_SECTION_SHIFT)) | |
560 | return -ENOMEM; | |
561 | ||
562 | spin_lock(&gpmc_mem_lock); | |
563 | if (gpmc_cs_reserved(cs)) { | |
564 | r = -EBUSY; | |
565 | goto out; | |
566 | } | |
567 | if (gpmc_cs_mem_enabled(cs)) | |
568 | r = adjust_resource(res, res->start & ~(size - 1), size); | |
569 | if (r < 0) | |
570 | r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, | |
571 | size, NULL, NULL); | |
572 | if (r < 0) | |
573 | goto out; | |
574 | ||
c71f8e9b JH |
575 | r = gpmc_cs_enable_mem(cs, res->start, resource_size(res)); |
576 | if (r < 0) { | |
577 | release_resource(res); | |
578 | goto out; | |
579 | } | |
580 | ||
f37e4580 ID |
581 | *base = res->start; |
582 | gpmc_cs_set_reserved(cs, 1); | |
583 | out: | |
584 | spin_unlock(&gpmc_mem_lock); | |
585 | return r; | |
586 | } | |
fd1dc87d | 587 | EXPORT_SYMBOL(gpmc_cs_request); |
f37e4580 ID |
588 | |
589 | void gpmc_cs_free(int cs) | |
590 | { | |
efe80723 TL |
591 | struct resource *res = &gpmc_cs_mem[cs]; |
592 | ||
f37e4580 | 593 | spin_lock(&gpmc_mem_lock); |
f34f3716 | 594 | if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { |
f37e4580 ID |
595 | printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); |
596 | BUG(); | |
597 | spin_unlock(&gpmc_mem_lock); | |
598 | return; | |
599 | } | |
600 | gpmc_cs_disable_mem(cs); | |
efe80723 TL |
601 | if (res->flags) |
602 | release_resource(res); | |
f37e4580 ID |
603 | gpmc_cs_set_reserved(cs, 0); |
604 | spin_unlock(&gpmc_mem_lock); | |
605 | } | |
fd1dc87d | 606 | EXPORT_SYMBOL(gpmc_cs_free); |
f37e4580 | 607 | |
948d38e7 | 608 | /** |
3a544354 | 609 | * gpmc_configure - write request to configure gpmc |
948d38e7 SG |
610 | * @cmd: command type |
611 | * @wval: value to write | |
612 | * @return status of the operation | |
613 | */ | |
3a544354 | 614 | int gpmc_configure(int cmd, int wval) |
948d38e7 | 615 | { |
3a544354 | 616 | u32 regval; |
948d38e7 SG |
617 | |
618 | switch (cmd) { | |
db97eb7d SG |
619 | case GPMC_ENABLE_IRQ: |
620 | gpmc_write_reg(GPMC_IRQENABLE, wval); | |
621 | break; | |
622 | ||
948d38e7 SG |
623 | case GPMC_SET_IRQ_STATUS: |
624 | gpmc_write_reg(GPMC_IRQSTATUS, wval); | |
625 | break; | |
626 | ||
627 | case GPMC_CONFIG_WP: | |
628 | regval = gpmc_read_reg(GPMC_CONFIG); | |
629 | if (wval) | |
630 | regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ | |
631 | else | |
632 | regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ | |
633 | gpmc_write_reg(GPMC_CONFIG, regval); | |
634 | break; | |
635 | ||
948d38e7 | 636 | default: |
3a544354 JH |
637 | pr_err("%s: command not supported\n", __func__); |
638 | return -EINVAL; | |
948d38e7 SG |
639 | } |
640 | ||
3a544354 | 641 | return 0; |
948d38e7 | 642 | } |
3a544354 | 643 | EXPORT_SYMBOL(gpmc_configure); |
948d38e7 | 644 | |
52bd138d AM |
645 | void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) |
646 | { | |
2fdf0c98 AM |
647 | int i; |
648 | ||
52bd138d AM |
649 | reg->gpmc_status = gpmc_base + GPMC_STATUS; |
650 | reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + | |
651 | GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; | |
652 | reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + | |
653 | GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; | |
654 | reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + | |
655 | GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; | |
656 | reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; | |
657 | reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; | |
658 | reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; | |
659 | reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; | |
660 | reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; | |
661 | reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; | |
662 | reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; | |
663 | reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; | |
2fdf0c98 AM |
664 | |
665 | for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { | |
666 | reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + | |
667 | GPMC_BCH_SIZE * i; | |
668 | reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + | |
669 | GPMC_BCH_SIZE * i; | |
670 | reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + | |
671 | GPMC_BCH_SIZE * i; | |
672 | reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + | |
673 | GPMC_BCH_SIZE * i; | |
27c9fd60 | 674 | reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 + |
675 | i * GPMC_BCH_SIZE; | |
676 | reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 + | |
677 | i * GPMC_BCH_SIZE; | |
678 | reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 + | |
679 | i * GPMC_BCH_SIZE; | |
2fdf0c98 | 680 | } |
52bd138d AM |
681 | } |
682 | ||
6b6c32fc AM |
683 | int gpmc_get_client_irq(unsigned irq_config) |
684 | { | |
685 | int i; | |
686 | ||
687 | if (hweight32(irq_config) > 1) | |
688 | return 0; | |
689 | ||
690 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
691 | if (gpmc_client_irq[i].bitmask & irq_config) | |
692 | return gpmc_client_irq[i].irq; | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
697 | static int gpmc_irq_endis(unsigned irq, bool endis) | |
698 | { | |
699 | int i; | |
700 | u32 regval; | |
701 | ||
702 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
703 | if (irq == gpmc_client_irq[i].irq) { | |
704 | regval = gpmc_read_reg(GPMC_IRQENABLE); | |
705 | if (endis) | |
706 | regval |= gpmc_client_irq[i].bitmask; | |
707 | else | |
708 | regval &= ~gpmc_client_irq[i].bitmask; | |
709 | gpmc_write_reg(GPMC_IRQENABLE, regval); | |
710 | break; | |
711 | } | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
716 | static void gpmc_irq_disable(struct irq_data *p) | |
717 | { | |
718 | gpmc_irq_endis(p->irq, false); | |
719 | } | |
720 | ||
721 | static void gpmc_irq_enable(struct irq_data *p) | |
722 | { | |
723 | gpmc_irq_endis(p->irq, true); | |
724 | } | |
725 | ||
726 | static void gpmc_irq_noop(struct irq_data *data) { } | |
727 | ||
728 | static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } | |
729 | ||
da496873 | 730 | static int gpmc_setup_irq(void) |
6b6c32fc AM |
731 | { |
732 | int i; | |
733 | u32 regval; | |
734 | ||
735 | if (!gpmc_irq) | |
736 | return -EINVAL; | |
737 | ||
738 | gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); | |
71856843 | 739 | if (gpmc_irq_start < 0) { |
6b6c32fc AM |
740 | pr_err("irq_alloc_descs failed\n"); |
741 | return gpmc_irq_start; | |
742 | } | |
743 | ||
744 | gpmc_irq_chip.name = "gpmc"; | |
745 | gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret; | |
746 | gpmc_irq_chip.irq_enable = gpmc_irq_enable; | |
747 | gpmc_irq_chip.irq_disable = gpmc_irq_disable; | |
748 | gpmc_irq_chip.irq_shutdown = gpmc_irq_noop; | |
749 | gpmc_irq_chip.irq_ack = gpmc_irq_noop; | |
750 | gpmc_irq_chip.irq_mask = gpmc_irq_noop; | |
751 | gpmc_irq_chip.irq_unmask = gpmc_irq_noop; | |
752 | ||
753 | gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE; | |
754 | gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT; | |
755 | ||
756 | for (i = 0; i < GPMC_NR_IRQ; i++) { | |
757 | gpmc_client_irq[i].irq = gpmc_irq_start + i; | |
758 | irq_set_chip_and_handler(gpmc_client_irq[i].irq, | |
759 | &gpmc_irq_chip, handle_simple_irq); | |
760 | set_irq_flags(gpmc_client_irq[i].irq, | |
761 | IRQF_VALID | IRQF_NOAUTOEN); | |
762 | } | |
763 | ||
764 | /* Disable interrupts */ | |
765 | gpmc_write_reg(GPMC_IRQENABLE, 0); | |
766 | ||
767 | /* clear interrupts */ | |
768 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
769 | gpmc_write_reg(GPMC_IRQSTATUS, regval); | |
770 | ||
771 | return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); | |
772 | } | |
773 | ||
351a102d | 774 | static int gpmc_free_irq(void) |
da496873 AM |
775 | { |
776 | int i; | |
777 | ||
778 | if (gpmc_irq) | |
779 | free_irq(gpmc_irq, NULL); | |
780 | ||
781 | for (i = 0; i < GPMC_NR_IRQ; i++) { | |
782 | irq_set_handler(gpmc_client_irq[i].irq, NULL); | |
783 | irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip); | |
784 | irq_modify_status(gpmc_client_irq[i].irq, 0, 0); | |
785 | } | |
786 | ||
787 | irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ); | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
351a102d | 792 | static void gpmc_mem_exit(void) |
da496873 AM |
793 | { |
794 | int cs; | |
795 | ||
f34f3716 | 796 | for (cs = 0; cs < gpmc_cs_num; cs++) { |
da496873 AM |
797 | if (!gpmc_cs_mem_enabled(cs)) |
798 | continue; | |
799 | gpmc_cs_delete_mem(cs); | |
800 | } | |
801 | ||
802 | } | |
803 | ||
84b00f0e | 804 | static void gpmc_mem_init(void) |
f37e4580 | 805 | { |
84b00f0e | 806 | int cs; |
f37e4580 | 807 | |
bf234397 JH |
808 | /* |
809 | * The first 1MB of GPMC address space is typically mapped to | |
810 | * the internal ROM. Never allocate the first page, to | |
811 | * facilitate bug detection; even if we didn't boot from ROM. | |
7f245162 | 812 | */ |
bf234397 | 813 | gpmc_mem_root.start = SZ_1M; |
f37e4580 ID |
814 | gpmc_mem_root.end = GPMC_MEM_END; |
815 | ||
816 | /* Reserve all regions that has been set up by bootloader */ | |
f34f3716 | 817 | for (cs = 0; cs < gpmc_cs_num; cs++) { |
f37e4580 ID |
818 | u32 base, size; |
819 | ||
820 | if (!gpmc_cs_mem_enabled(cs)) | |
821 | continue; | |
822 | gpmc_cs_get_memconf(cs, &base, &size); | |
84b00f0e JH |
823 | if (gpmc_cs_insert_mem(cs, base, size)) { |
824 | pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", | |
825 | __func__, cs, base, base + size); | |
826 | gpmc_cs_disable_mem(cs); | |
8119024e | 827 | } |
f37e4580 | 828 | } |
4bbbc1ad JY |
829 | } |
830 | ||
246da26d AM |
831 | static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) |
832 | { | |
833 | u32 temp; | |
834 | int div; | |
835 | ||
836 | div = gpmc_calc_divider(sync_clk); | |
837 | temp = gpmc_ps_to_ticks(time_ps); | |
838 | temp = (temp + div - 1) / div; | |
839 | return gpmc_ticks_to_ps(temp * div); | |
840 | } | |
841 | ||
842 | /* XXX: can the cycles be avoided ? */ | |
843 | static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
844 | struct gpmc_device_timings *dev_t, |
845 | bool mux) | |
246da26d | 846 | { |
246da26d AM |
847 | u32 temp; |
848 | ||
849 | /* adv_rd_off */ | |
850 | temp = dev_t->t_avdp_r; | |
851 | /* XXX: mux check required ? */ | |
852 | if (mux) { | |
853 | /* XXX: t_avdp not to be required for sync, only added for tusb | |
854 | * this indirectly necessitates requirement of t_avdp_r and | |
855 | * t_avdp_w instead of having a single t_avdp | |
856 | */ | |
857 | temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh); | |
858 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
859 | } | |
860 | gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); | |
861 | ||
862 | /* oe_on */ | |
863 | temp = dev_t->t_oeasu; /* XXX: remove this ? */ | |
864 | if (mux) { | |
865 | temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach); | |
866 | temp = max_t(u32, temp, gpmc_t->adv_rd_off + | |
867 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe)); | |
868 | } | |
869 | gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); | |
870 | ||
871 | /* access */ | |
872 | /* XXX: any scope for improvement ?, by combining oe_on | |
873 | * and clk_activation, need to check whether | |
874 | * access = clk_activation + round to sync clk ? | |
875 | */ | |
876 | temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk); | |
877 | temp += gpmc_t->clk_activation; | |
878 | if (dev_t->cyc_oe) | |
879 | temp = max_t(u32, temp, gpmc_t->oe_on + | |
880 | gpmc_ticks_to_ps(dev_t->cyc_oe)); | |
881 | gpmc_t->access = gpmc_round_ps_to_ticks(temp); | |
882 | ||
883 | gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); | |
884 | gpmc_t->cs_rd_off = gpmc_t->oe_off; | |
885 | ||
886 | /* rd_cycle */ | |
887 | temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez); | |
888 | temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) + | |
889 | gpmc_t->access; | |
890 | /* XXX: barter t_ce_rdyz with t_cez_r ? */ | |
891 | if (dev_t->t_ce_rdyz) | |
892 | temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz); | |
893 | gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); | |
894 | ||
895 | return 0; | |
896 | } | |
897 | ||
898 | static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
899 | struct gpmc_device_timings *dev_t, |
900 | bool mux) | |
246da26d | 901 | { |
246da26d AM |
902 | u32 temp; |
903 | ||
904 | /* adv_wr_off */ | |
905 | temp = dev_t->t_avdp_w; | |
906 | if (mux) { | |
907 | temp = max_t(u32, temp, | |
908 | gpmc_t->clk_activation + dev_t->t_avdh); | |
909 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
910 | } | |
911 | gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); | |
912 | ||
913 | /* wr_data_mux_bus */ | |
914 | temp = max_t(u32, dev_t->t_weasu, | |
915 | gpmc_t->clk_activation + dev_t->t_rdyo); | |
916 | /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?, | |
917 | * and in that case remember to handle we_on properly | |
918 | */ | |
919 | if (mux) { | |
920 | temp = max_t(u32, temp, | |
921 | gpmc_t->adv_wr_off + dev_t->t_aavdh); | |
922 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + | |
923 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); | |
924 | } | |
925 | gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); | |
926 | ||
927 | /* we_on */ | |
928 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) | |
929 | gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); | |
930 | else | |
931 | gpmc_t->we_on = gpmc_t->wr_data_mux_bus; | |
932 | ||
933 | /* wr_access */ | |
934 | /* XXX: gpmc_capability check reqd ? , even if not, will not harm */ | |
935 | gpmc_t->wr_access = gpmc_t->access; | |
936 | ||
937 | /* we_off */ | |
938 | temp = gpmc_t->we_on + dev_t->t_wpl; | |
939 | temp = max_t(u32, temp, | |
940 | gpmc_t->wr_access + gpmc_ticks_to_ps(1)); | |
941 | temp = max_t(u32, temp, | |
942 | gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl)); | |
943 | gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); | |
944 | ||
945 | gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + | |
946 | dev_t->t_wph); | |
947 | ||
948 | /* wr_cycle */ | |
949 | temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk); | |
950 | temp += gpmc_t->wr_access; | |
951 | /* XXX: barter t_ce_rdyz with t_cez_w ? */ | |
952 | if (dev_t->t_ce_rdyz) | |
953 | temp = max_t(u32, temp, | |
954 | gpmc_t->cs_wr_off + dev_t->t_ce_rdyz); | |
955 | gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); | |
956 | ||
957 | return 0; | |
958 | } | |
959 | ||
960 | static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
961 | struct gpmc_device_timings *dev_t, |
962 | bool mux) | |
246da26d | 963 | { |
246da26d AM |
964 | u32 temp; |
965 | ||
966 | /* adv_rd_off */ | |
967 | temp = dev_t->t_avdp_r; | |
968 | if (mux) | |
969 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
970 | gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); | |
971 | ||
972 | /* oe_on */ | |
973 | temp = dev_t->t_oeasu; | |
974 | if (mux) | |
975 | temp = max_t(u32, temp, | |
976 | gpmc_t->adv_rd_off + dev_t->t_aavdh); | |
977 | gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); | |
978 | ||
979 | /* access */ | |
980 | temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ | |
981 | gpmc_t->oe_on + dev_t->t_oe); | |
982 | temp = max_t(u32, temp, | |
983 | gpmc_t->cs_on + dev_t->t_ce); | |
984 | temp = max_t(u32, temp, | |
985 | gpmc_t->adv_on + dev_t->t_aa); | |
986 | gpmc_t->access = gpmc_round_ps_to_ticks(temp); | |
987 | ||
988 | gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); | |
989 | gpmc_t->cs_rd_off = gpmc_t->oe_off; | |
990 | ||
991 | /* rd_cycle */ | |
992 | temp = max_t(u32, dev_t->t_rd_cycle, | |
993 | gpmc_t->cs_rd_off + dev_t->t_cez_r); | |
994 | temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez); | |
995 | gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); | |
996 | ||
997 | return 0; | |
998 | } | |
999 | ||
1000 | static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1001 | struct gpmc_device_timings *dev_t, |
1002 | bool mux) | |
246da26d | 1003 | { |
246da26d AM |
1004 | u32 temp; |
1005 | ||
1006 | /* adv_wr_off */ | |
1007 | temp = dev_t->t_avdp_w; | |
1008 | if (mux) | |
1009 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1010 | gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); | |
1011 | ||
1012 | /* wr_data_mux_bus */ | |
1013 | temp = dev_t->t_weasu; | |
1014 | if (mux) { | |
1015 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh); | |
1016 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + | |
1017 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); | |
1018 | } | |
1019 | gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); | |
1020 | ||
1021 | /* we_on */ | |
1022 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) | |
1023 | gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); | |
1024 | else | |
1025 | gpmc_t->we_on = gpmc_t->wr_data_mux_bus; | |
1026 | ||
1027 | /* we_off */ | |
1028 | temp = gpmc_t->we_on + dev_t->t_wpl; | |
1029 | gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); | |
1030 | ||
1031 | gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + | |
1032 | dev_t->t_wph); | |
1033 | ||
1034 | /* wr_cycle */ | |
1035 | temp = max_t(u32, dev_t->t_wr_cycle, | |
1036 | gpmc_t->cs_wr_off + dev_t->t_cez_w); | |
1037 | gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); | |
1038 | ||
1039 | return 0; | |
1040 | } | |
1041 | ||
1042 | static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, | |
1043 | struct gpmc_device_timings *dev_t) | |
1044 | { | |
1045 | u32 temp; | |
1046 | ||
1047 | gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) * | |
1048 | gpmc_get_fclk_period(); | |
1049 | ||
1050 | gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk( | |
1051 | dev_t->t_bacc, | |
1052 | gpmc_t->sync_clk); | |
1053 | ||
1054 | temp = max_t(u32, dev_t->t_ces, dev_t->t_avds); | |
1055 | gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp); | |
1056 | ||
1057 | if (gpmc_calc_divider(gpmc_t->sync_clk) != 1) | |
1058 | return 0; | |
1059 | ||
1060 | if (dev_t->ce_xdelay) | |
1061 | gpmc_t->bool_timings.cs_extra_delay = true; | |
1062 | if (dev_t->avd_xdelay) | |
1063 | gpmc_t->bool_timings.adv_extra_delay = true; | |
1064 | if (dev_t->oe_xdelay) | |
1065 | gpmc_t->bool_timings.oe_extra_delay = true; | |
1066 | if (dev_t->we_xdelay) | |
1067 | gpmc_t->bool_timings.we_extra_delay = true; | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
1072 | static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1073 | struct gpmc_device_timings *dev_t, |
1074 | bool sync) | |
246da26d AM |
1075 | { |
1076 | u32 temp; | |
1077 | ||
1078 | /* cs_on */ | |
1079 | gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu); | |
1080 | ||
1081 | /* adv_on */ | |
1082 | temp = dev_t->t_avdasu; | |
1083 | if (dev_t->t_ce_avd) | |
1084 | temp = max_t(u32, temp, | |
1085 | gpmc_t->cs_on + dev_t->t_ce_avd); | |
1086 | gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); | |
1087 | ||
c3be5b45 | 1088 | if (sync) |
246da26d AM |
1089 | gpmc_calc_sync_common_timings(gpmc_t, dev_t); |
1090 | ||
1091 | return 0; | |
1092 | } | |
1093 | ||
1094 | /* TODO: remove this function once all peripherals are confirmed to | |
1095 | * work with generic timing. Simultaneously gpmc_cs_set_timings() | |
1096 | * has to be modified to handle timings in ps instead of ns | |
1097 | */ | |
1098 | static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) | |
1099 | { | |
1100 | t->cs_on /= 1000; | |
1101 | t->cs_rd_off /= 1000; | |
1102 | t->cs_wr_off /= 1000; | |
1103 | t->adv_on /= 1000; | |
1104 | t->adv_rd_off /= 1000; | |
1105 | t->adv_wr_off /= 1000; | |
1106 | t->we_on /= 1000; | |
1107 | t->we_off /= 1000; | |
1108 | t->oe_on /= 1000; | |
1109 | t->oe_off /= 1000; | |
1110 | t->page_burst_access /= 1000; | |
1111 | t->access /= 1000; | |
1112 | t->rd_cycle /= 1000; | |
1113 | t->wr_cycle /= 1000; | |
1114 | t->bus_turnaround /= 1000; | |
1115 | t->cycle2cycle_delay /= 1000; | |
1116 | t->wait_monitoring /= 1000; | |
1117 | t->clk_activation /= 1000; | |
1118 | t->wr_access /= 1000; | |
1119 | t->wr_data_mux_bus /= 1000; | |
1120 | } | |
1121 | ||
1122 | int gpmc_calc_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1123 | struct gpmc_settings *gpmc_s, |
1124 | struct gpmc_device_timings *dev_t) | |
246da26d | 1125 | { |
c3be5b45 JH |
1126 | bool mux = false, sync = false; |
1127 | ||
1128 | if (gpmc_s) { | |
1129 | mux = gpmc_s->mux_add_data ? true : false; | |
1130 | sync = (gpmc_s->sync_read || gpmc_s->sync_write); | |
1131 | } | |
1132 | ||
246da26d AM |
1133 | memset(gpmc_t, 0, sizeof(*gpmc_t)); |
1134 | ||
c3be5b45 | 1135 | gpmc_calc_common_timings(gpmc_t, dev_t, sync); |
246da26d | 1136 | |
c3be5b45 JH |
1137 | if (gpmc_s && gpmc_s->sync_read) |
1138 | gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); | |
246da26d | 1139 | else |
c3be5b45 | 1140 | gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); |
246da26d | 1141 | |
c3be5b45 JH |
1142 | if (gpmc_s && gpmc_s->sync_write) |
1143 | gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); | |
246da26d | 1144 | else |
c3be5b45 | 1145 | gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); |
246da26d AM |
1146 | |
1147 | /* TODO: remove, see function definition */ | |
1148 | gpmc_convert_ps_to_ns(gpmc_t); | |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
aa8d4767 JH |
1153 | /** |
1154 | * gpmc_cs_program_settings - programs non-timing related settings | |
1155 | * @cs: GPMC chip-select to program | |
1156 | * @p: pointer to GPMC settings structure | |
1157 | * | |
1158 | * Programs non-timing related settings for a GPMC chip-select, such as | |
1159 | * bus-width, burst configuration, etc. Function should be called once | |
1160 | * for each chip-select that is being used and must be called before | |
1161 | * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1 | |
1162 | * register will be initialised to zero by this function. Returns 0 on | |
1163 | * success and appropriate negative error code on failure. | |
1164 | */ | |
1165 | int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) | |
1166 | { | |
1167 | u32 config1; | |
1168 | ||
1169 | if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { | |
1170 | pr_err("%s: invalid width %d!", __func__, p->device_width); | |
1171 | return -EINVAL; | |
1172 | } | |
1173 | ||
1174 | /* Address-data multiplexing not supported for NAND devices */ | |
1175 | if (p->device_nand && p->mux_add_data) { | |
1176 | pr_err("%s: invalid configuration!\n", __func__); | |
1177 | return -EINVAL; | |
1178 | } | |
1179 | ||
1180 | if ((p->mux_add_data > GPMC_MUX_AD) || | |
1181 | ((p->mux_add_data == GPMC_MUX_AAD) && | |
1182 | !(gpmc_capability & GPMC_HAS_MUX_AAD))) { | |
1183 | pr_err("%s: invalid multiplex configuration!\n", __func__); | |
1184 | return -EINVAL; | |
1185 | } | |
1186 | ||
1187 | /* Page/burst mode supports lengths of 4, 8 and 16 bytes */ | |
1188 | if (p->burst_read || p->burst_write) { | |
1189 | switch (p->burst_len) { | |
1190 | case GPMC_BURST_4: | |
1191 | case GPMC_BURST_8: | |
1192 | case GPMC_BURST_16: | |
1193 | break; | |
1194 | default: | |
1195 | pr_err("%s: invalid page/burst-length (%d)\n", | |
1196 | __func__, p->burst_len); | |
1197 | return -EINVAL; | |
1198 | } | |
1199 | } | |
1200 | ||
2b54057c | 1201 | if (p->wait_pin > gpmc_nr_waitpins) { |
aa8d4767 JH |
1202 | pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); |
1203 | return -EINVAL; | |
1204 | } | |
1205 | ||
1206 | config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); | |
1207 | ||
1208 | if (p->sync_read) | |
1209 | config1 |= GPMC_CONFIG1_READTYPE_SYNC; | |
1210 | if (p->sync_write) | |
1211 | config1 |= GPMC_CONFIG1_WRITETYPE_SYNC; | |
1212 | if (p->wait_on_read) | |
1213 | config1 |= GPMC_CONFIG1_WAIT_READ_MON; | |
1214 | if (p->wait_on_write) | |
1215 | config1 |= GPMC_CONFIG1_WAIT_WRITE_MON; | |
1216 | if (p->wait_on_read || p->wait_on_write) | |
1217 | config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); | |
1218 | if (p->device_nand) | |
1219 | config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND); | |
1220 | if (p->mux_add_data) | |
1221 | config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); | |
1222 | if (p->burst_read) | |
1223 | config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP; | |
1224 | if (p->burst_write) | |
1225 | config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP; | |
1226 | if (p->burst_read || p->burst_write) { | |
1227 | config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); | |
1228 | config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; | |
1229 | } | |
1230 | ||
1231 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); | |
1232 | ||
1233 | return 0; | |
1234 | } | |
1235 | ||
bc6b1e7b | 1236 | #ifdef CONFIG_OF |
31957609 | 1237 | static const struct of_device_id gpmc_dt_ids[] = { |
bc6b1e7b DM |
1238 | { .compatible = "ti,omap2420-gpmc" }, |
1239 | { .compatible = "ti,omap2430-gpmc" }, | |
1240 | { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ | |
1241 | { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */ | |
1242 | { .compatible = "ti,am3352-gpmc" }, /* am335x devices */ | |
1243 | { } | |
1244 | }; | |
1245 | MODULE_DEVICE_TABLE(of, gpmc_dt_ids); | |
1246 | ||
8c8a7771 JH |
1247 | /** |
1248 | * gpmc_read_settings_dt - read gpmc settings from device-tree | |
1249 | * @np: pointer to device-tree node for a gpmc child device | |
1250 | * @p: pointer to gpmc settings structure | |
1251 | * | |
1252 | * Reads the GPMC settings for a GPMC child device from device-tree and | |
1253 | * stores them in the GPMC settings structure passed. The GPMC settings | |
1254 | * structure is initialised to zero by this function and so any | |
1255 | * previously stored settings will be cleared. | |
1256 | */ | |
1257 | void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) | |
1258 | { | |
1259 | memset(p, 0, sizeof(struct gpmc_settings)); | |
1260 | ||
1261 | p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); | |
1262 | p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); | |
8c8a7771 JH |
1263 | of_property_read_u32(np, "gpmc,device-width", &p->device_width); |
1264 | of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); | |
1265 | ||
1266 | if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { | |
1267 | p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); | |
1268 | p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); | |
1269 | p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); | |
1270 | if (!p->burst_read && !p->burst_write) | |
1271 | pr_warn("%s: page/burst-length set but not used!\n", | |
1272 | __func__); | |
1273 | } | |
1274 | ||
1275 | if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { | |
1276 | p->wait_on_read = of_property_read_bool(np, | |
1277 | "gpmc,wait-on-read"); | |
1278 | p->wait_on_write = of_property_read_bool(np, | |
1279 | "gpmc,wait-on-write"); | |
1280 | if (!p->wait_on_read && !p->wait_on_write) | |
2b54057c RQ |
1281 | pr_debug("%s: rd/wr wait monitoring not enabled!\n", |
1282 | __func__); | |
8c8a7771 JH |
1283 | } |
1284 | } | |
1285 | ||
bc6b1e7b DM |
1286 | static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, |
1287 | struct gpmc_timings *gpmc_t) | |
1288 | { | |
d36b4cd4 JH |
1289 | struct gpmc_bool_timings *p; |
1290 | ||
1291 | if (!np || !gpmc_t) | |
1292 | return; | |
bc6b1e7b DM |
1293 | |
1294 | memset(gpmc_t, 0, sizeof(*gpmc_t)); | |
1295 | ||
1296 | /* minimum clock period for syncronous mode */ | |
d36b4cd4 | 1297 | of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); |
bc6b1e7b DM |
1298 | |
1299 | /* chip select timtings */ | |
d36b4cd4 JH |
1300 | of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); |
1301 | of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); | |
1302 | of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); | |
bc6b1e7b DM |
1303 | |
1304 | /* ADV signal timings */ | |
d36b4cd4 JH |
1305 | of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); |
1306 | of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); | |
1307 | of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); | |
bc6b1e7b DM |
1308 | |
1309 | /* WE signal timings */ | |
d36b4cd4 JH |
1310 | of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); |
1311 | of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); | |
bc6b1e7b DM |
1312 | |
1313 | /* OE signal timings */ | |
d36b4cd4 JH |
1314 | of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); |
1315 | of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); | |
bc6b1e7b DM |
1316 | |
1317 | /* access and cycle timings */ | |
d36b4cd4 JH |
1318 | of_property_read_u32(np, "gpmc,page-burst-access-ns", |
1319 | &gpmc_t->page_burst_access); | |
1320 | of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); | |
1321 | of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); | |
1322 | of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); | |
1323 | of_property_read_u32(np, "gpmc,bus-turnaround-ns", | |
1324 | &gpmc_t->bus_turnaround); | |
1325 | of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", | |
1326 | &gpmc_t->cycle2cycle_delay); | |
1327 | of_property_read_u32(np, "gpmc,wait-monitoring-ns", | |
1328 | &gpmc_t->wait_monitoring); | |
1329 | of_property_read_u32(np, "gpmc,clk-activation-ns", | |
1330 | &gpmc_t->clk_activation); | |
1331 | ||
1332 | /* only applicable to OMAP3+ */ | |
1333 | of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); | |
1334 | of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", | |
1335 | &gpmc_t->wr_data_mux_bus); | |
1336 | ||
1337 | /* bool timing parameters */ | |
1338 | p = &gpmc_t->bool_timings; | |
1339 | ||
1340 | p->cycle2cyclediffcsen = | |
1341 | of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); | |
1342 | p->cycle2cyclesamecsen = | |
1343 | of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); | |
1344 | p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); | |
1345 | p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); | |
1346 | p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); | |
1347 | p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); | |
1348 | p->time_para_granularity = | |
1349 | of_property_read_bool(np, "gpmc,time-para-granularity"); | |
bc6b1e7b DM |
1350 | } |
1351 | ||
6b187b21 | 1352 | #if IS_ENABLED(CONFIG_MTD_NAND) |
bc6b1e7b | 1353 | |
496c8a0b MJ |
1354 | static const char * const nand_xfer_types[] = { |
1355 | [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled", | |
1356 | [NAND_OMAP_POLLED] = "polled", | |
1357 | [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma", | |
1358 | [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq", | |
1359 | }; | |
1360 | ||
bc6b1e7b DM |
1361 | static int gpmc_probe_nand_child(struct platform_device *pdev, |
1362 | struct device_node *child) | |
1363 | { | |
1364 | u32 val; | |
1365 | const char *s; | |
1366 | struct gpmc_timings gpmc_t; | |
1367 | struct omap_nand_platform_data *gpmc_nand_data; | |
1368 | ||
1369 | if (of_property_read_u32(child, "reg", &val) < 0) { | |
1370 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1371 | child->full_name); | |
1372 | return -ENODEV; | |
1373 | } | |
1374 | ||
1375 | gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data), | |
1376 | GFP_KERNEL); | |
1377 | if (!gpmc_nand_data) | |
1378 | return -ENOMEM; | |
1379 | ||
1380 | gpmc_nand_data->cs = val; | |
1381 | gpmc_nand_data->of_node = child; | |
1382 | ||
ac65caf5 PG |
1383 | /* Detect availability of ELM module */ |
1384 | gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0); | |
1385 | if (gpmc_nand_data->elm_of_node == NULL) | |
1386 | gpmc_nand_data->elm_of_node = | |
1387 | of_parse_phandle(child, "elm_id", 0); | |
1388 | if (gpmc_nand_data->elm_of_node == NULL) | |
1389 | pr_warn("%s: ti,elm-id property not found\n", __func__); | |
1390 | ||
1391 | /* select ecc-scheme for NAND */ | |
1392 | if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) { | |
1393 | pr_err("%s: ti,nand-ecc-opt not found\n", __func__); | |
1394 | return -ENODEV; | |
1395 | } | |
a3e83f05 RQ |
1396 | |
1397 | if (!strcmp(s, "sw")) | |
1398 | gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW; | |
1399 | else if (!strcmp(s, "ham1") || | |
1400 | !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) | |
ac65caf5 PG |
1401 | gpmc_nand_data->ecc_opt = |
1402 | OMAP_ECC_HAM1_CODE_HW; | |
1403 | else if (!strcmp(s, "bch4")) | |
1404 | if (gpmc_nand_data->elm_of_node) | |
1405 | gpmc_nand_data->ecc_opt = | |
1406 | OMAP_ECC_BCH4_CODE_HW; | |
1407 | else | |
1408 | gpmc_nand_data->ecc_opt = | |
1409 | OMAP_ECC_BCH4_CODE_HW_DETECTION_SW; | |
1410 | else if (!strcmp(s, "bch8")) | |
1411 | if (gpmc_nand_data->elm_of_node) | |
1412 | gpmc_nand_data->ecc_opt = | |
1413 | OMAP_ECC_BCH8_CODE_HW; | |
1414 | else | |
1415 | gpmc_nand_data->ecc_opt = | |
1416 | OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; | |
27c9fd60 | 1417 | else if (!strcmp(s, "bch16")) |
1418 | if (gpmc_nand_data->elm_of_node) | |
1419 | gpmc_nand_data->ecc_opt = | |
1420 | OMAP_ECC_BCH16_CODE_HW; | |
1421 | else | |
1422 | pr_err("%s: BCH16 requires ELM support\n", __func__); | |
ac65caf5 PG |
1423 | else |
1424 | pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__); | |
bc6b1e7b | 1425 | |
ac65caf5 | 1426 | /* select data transfer mode for NAND controller */ |
496c8a0b MJ |
1427 | if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) |
1428 | for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++) | |
1429 | if (!strcasecmp(s, nand_xfer_types[val])) { | |
1430 | gpmc_nand_data->xfer_type = val; | |
1431 | break; | |
1432 | } | |
1433 | ||
fef775ca EG |
1434 | gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child); |
1435 | ||
bc6b1e7b DM |
1436 | val = of_get_nand_bus_width(child); |
1437 | if (val == 16) | |
1438 | gpmc_nand_data->devsize = NAND_BUSWIDTH_16; | |
1439 | ||
1440 | gpmc_read_timings_dt(child, &gpmc_t); | |
1441 | gpmc_nand_init(gpmc_nand_data, &gpmc_t); | |
1442 | ||
1443 | return 0; | |
1444 | } | |
1445 | #else | |
1446 | static int gpmc_probe_nand_child(struct platform_device *pdev, | |
1447 | struct device_node *child) | |
1448 | { | |
1449 | return 0; | |
1450 | } | |
1451 | #endif | |
1452 | ||
980386d2 | 1453 | #if IS_ENABLED(CONFIG_MTD_ONENAND) |
75d3625e EG |
1454 | static int gpmc_probe_onenand_child(struct platform_device *pdev, |
1455 | struct device_node *child) | |
1456 | { | |
1457 | u32 val; | |
1458 | struct omap_onenand_platform_data *gpmc_onenand_data; | |
1459 | ||
1460 | if (of_property_read_u32(child, "reg", &val) < 0) { | |
1461 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1462 | child->full_name); | |
1463 | return -ENODEV; | |
1464 | } | |
1465 | ||
1466 | gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data), | |
1467 | GFP_KERNEL); | |
1468 | if (!gpmc_onenand_data) | |
1469 | return -ENOMEM; | |
1470 | ||
1471 | gpmc_onenand_data->cs = val; | |
1472 | gpmc_onenand_data->of_node = child; | |
1473 | gpmc_onenand_data->dma_channel = -1; | |
1474 | ||
1475 | if (!of_property_read_u32(child, "dma-channel", &val)) | |
1476 | gpmc_onenand_data->dma_channel = val; | |
1477 | ||
1478 | gpmc_onenand_init(gpmc_onenand_data); | |
1479 | ||
1480 | return 0; | |
1481 | } | |
1482 | #else | |
1483 | static int gpmc_probe_onenand_child(struct platform_device *pdev, | |
1484 | struct device_node *child) | |
1485 | { | |
1486 | return 0; | |
1487 | } | |
1488 | #endif | |
1489 | ||
cdd6928c | 1490 | /** |
3af91cf7 | 1491 | * gpmc_probe_generic_child - configures the gpmc for a child device |
cdd6928c | 1492 | * @pdev: pointer to gpmc platform device |
3af91cf7 | 1493 | * @child: pointer to device-tree node for child device |
cdd6928c | 1494 | * |
3af91cf7 | 1495 | * Allocates and configures a GPMC chip-select for a child device. |
cdd6928c JH |
1496 | * Returns 0 on success and appropriate negative error code on failure. |
1497 | */ | |
3af91cf7 | 1498 | static int gpmc_probe_generic_child(struct platform_device *pdev, |
cdd6928c JH |
1499 | struct device_node *child) |
1500 | { | |
1501 | struct gpmc_settings gpmc_s; | |
1502 | struct gpmc_timings gpmc_t; | |
1503 | struct resource res; | |
1504 | unsigned long base; | |
1505 | int ret, cs; | |
e378d22b | 1506 | u32 val; |
cdd6928c JH |
1507 | |
1508 | if (of_property_read_u32(child, "reg", &cs) < 0) { | |
1509 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1510 | child->full_name); | |
1511 | return -ENODEV; | |
1512 | } | |
1513 | ||
1514 | if (of_address_to_resource(child, 0, &res) < 0) { | |
1515 | dev_err(&pdev->dev, "%s has malformed 'reg' property\n", | |
1516 | child->full_name); | |
1517 | return -ENODEV; | |
1518 | } | |
1519 | ||
1520 | ret = gpmc_cs_request(cs, resource_size(&res), &base); | |
1521 | if (ret < 0) { | |
1522 | dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); | |
1523 | return ret; | |
1524 | } | |
1525 | ||
fd4446f2 TL |
1526 | /* |
1527 | * For some GPMC devices we still need to rely on the bootloader | |
1528 | * timings because the devices can be connected via FPGA. So far | |
1529 | * the list is smc91x on the omap2 SDP boards, and 8250 on zooms. | |
1530 | * REVISIT: Add timing support from slls644g.pdf and from the | |
1531 | * lan91c96 manual. | |
1532 | */ | |
1533 | if (of_device_is_compatible(child, "ns16550a") || | |
1534 | of_device_is_compatible(child, "smsc,lan91c94") || | |
1535 | of_device_is_compatible(child, "smsc,lan91c111")) { | |
1536 | dev_warn(&pdev->dev, | |
1537 | "%s using bootloader timings on CS%d\n", | |
1538 | child->name, cs); | |
1539 | goto no_timings; | |
1540 | } | |
1541 | ||
cdd6928c JH |
1542 | /* |
1543 | * FIXME: gpmc_cs_request() will map the CS to an arbitary | |
1544 | * location in the gpmc address space. When booting with | |
1545 | * device-tree we want the NOR flash to be mapped to the | |
1546 | * location specified in the device-tree blob. So remap the | |
1547 | * CS to this location. Once DT migration is complete should | |
1548 | * just make gpmc_cs_request() map a specific address. | |
1549 | */ | |
1550 | ret = gpmc_cs_remap(cs, res.start); | |
1551 | if (ret < 0) { | |
f70bf2a3 FE |
1552 | dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", |
1553 | cs, &res.start); | |
cdd6928c JH |
1554 | goto err; |
1555 | } | |
1556 | ||
1557 | gpmc_read_settings_dt(child, &gpmc_s); | |
1558 | ||
1559 | ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width); | |
1560 | if (ret < 0) | |
1561 | goto err; | |
1562 | ||
1563 | ret = gpmc_cs_program_settings(cs, &gpmc_s); | |
1564 | if (ret < 0) | |
1565 | goto err; | |
1566 | ||
1567 | gpmc_read_timings_dt(child, &gpmc_t); | |
7604baf3 RQ |
1568 | ret = gpmc_cs_set_timings(cs, &gpmc_t); |
1569 | if (ret) { | |
1570 | dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n", | |
1571 | child->name); | |
1572 | goto err; | |
1573 | } | |
cdd6928c | 1574 | |
e378d22b RQ |
1575 | /* Clear limited address i.e. enable A26-A11 */ |
1576 | val = gpmc_read_reg(GPMC_CONFIG); | |
1577 | val &= ~GPMC_CONFIG_LIMITEDADDRESS; | |
1578 | gpmc_write_reg(GPMC_CONFIG, val); | |
1579 | ||
fd4446f2 | 1580 | no_timings: |
cdd6928c JH |
1581 | if (of_platform_device_create(child, NULL, &pdev->dev)) |
1582 | return 0; | |
1583 | ||
1584 | dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name); | |
e8ffd6fd | 1585 | ret = -ENODEV; |
cdd6928c JH |
1586 | |
1587 | err: | |
1588 | gpmc_cs_free(cs); | |
1589 | ||
1590 | return ret; | |
1591 | } | |
1592 | ||
bc6b1e7b DM |
1593 | static int gpmc_probe_dt(struct platform_device *pdev) |
1594 | { | |
1595 | int ret; | |
1596 | struct device_node *child; | |
1597 | const struct of_device_id *of_id = | |
1598 | of_match_device(gpmc_dt_ids, &pdev->dev); | |
1599 | ||
1600 | if (!of_id) | |
1601 | return 0; | |
1602 | ||
f34f3716 GP |
1603 | ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", |
1604 | &gpmc_cs_num); | |
1605 | if (ret < 0) { | |
1606 | pr_err("%s: number of chip-selects not defined\n", __func__); | |
1607 | return ret; | |
1608 | } else if (gpmc_cs_num < 1) { | |
1609 | pr_err("%s: all chip-selects are disabled\n", __func__); | |
1610 | return -EINVAL; | |
1611 | } else if (gpmc_cs_num > GPMC_CS_NUM) { | |
1612 | pr_err("%s: number of supported chip-selects cannot be > %d\n", | |
1613 | __func__, GPMC_CS_NUM); | |
1614 | return -EINVAL; | |
1615 | } | |
1616 | ||
9f833156 JH |
1617 | ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", |
1618 | &gpmc_nr_waitpins); | |
1619 | if (ret < 0) { | |
1620 | pr_err("%s: number of wait pins not found!\n", __func__); | |
1621 | return ret; | |
1622 | } | |
1623 | ||
68e2eb53 | 1624 | for_each_available_child_of_node(pdev->dev.of_node, child) { |
bc6b1e7b | 1625 | |
f2b09f67 JMC |
1626 | if (!child->name) |
1627 | continue; | |
cdd6928c | 1628 | |
f2b09f67 JMC |
1629 | if (of_node_cmp(child->name, "nand") == 0) |
1630 | ret = gpmc_probe_nand_child(pdev, child); | |
1631 | else if (of_node_cmp(child->name, "onenand") == 0) | |
1632 | ret = gpmc_probe_onenand_child(pdev, child); | |
1633 | else if (of_node_cmp(child->name, "ethernet") == 0 || | |
fd4446f2 TL |
1634 | of_node_cmp(child->name, "nor") == 0 || |
1635 | of_node_cmp(child->name, "uart") == 0) | |
f2b09f67 | 1636 | ret = gpmc_probe_generic_child(pdev, child); |
cdd6928c | 1637 | |
b327b362 JMC |
1638 | if (WARN(ret < 0, "%s: probing gpmc child %s failed\n", |
1639 | __func__, child->full_name)) | |
5330dc16 | 1640 | of_node_put(child); |
5330dc16 JMC |
1641 | } |
1642 | ||
bc6b1e7b DM |
1643 | return 0; |
1644 | } | |
1645 | #else | |
1646 | static int gpmc_probe_dt(struct platform_device *pdev) | |
1647 | { | |
1648 | return 0; | |
1649 | } | |
1650 | #endif | |
1651 | ||
351a102d | 1652 | static int gpmc_probe(struct platform_device *pdev) |
4bbbc1ad | 1653 | { |
8119024e | 1654 | int rc; |
6b6c32fc | 1655 | u32 l; |
da496873 | 1656 | struct resource *res; |
4bbbc1ad | 1657 | |
da496873 AM |
1658 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1659 | if (res == NULL) | |
1660 | return -ENOENT; | |
8d08436d | 1661 | |
da496873 AM |
1662 | phys_base = res->start; |
1663 | mem_size = resource_size(res); | |
fd1dc87d | 1664 | |
5857bd98 TR |
1665 | gpmc_base = devm_ioremap_resource(&pdev->dev, res); |
1666 | if (IS_ERR(gpmc_base)) | |
1667 | return PTR_ERR(gpmc_base); | |
da496873 AM |
1668 | |
1669 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1670 | if (res == NULL) | |
1671 | dev_warn(&pdev->dev, "Failed to get resource: irq\n"); | |
1672 | else | |
1673 | gpmc_irq = res->start; | |
1674 | ||
1675 | gpmc_l3_clk = clk_get(&pdev->dev, "fck"); | |
1676 | if (IS_ERR(gpmc_l3_clk)) { | |
1677 | dev_err(&pdev->dev, "error: clk_get\n"); | |
1678 | gpmc_irq = 0; | |
1679 | return PTR_ERR(gpmc_l3_clk); | |
fd1dc87d PW |
1680 | } |
1681 | ||
b3f5525c | 1682 | pm_runtime_enable(&pdev->dev); |
1683 | pm_runtime_get_sync(&pdev->dev); | |
1daa8c1d | 1684 | |
da496873 AM |
1685 | gpmc_dev = &pdev->dev; |
1686 | ||
4bbbc1ad | 1687 | l = gpmc_read_reg(GPMC_REVISION); |
aa8d4767 JH |
1688 | |
1689 | /* | |
1690 | * FIXME: Once device-tree migration is complete the below flags | |
1691 | * should be populated based upon the device-tree compatible | |
1692 | * string. For now just use the IP revision. OMAP3+ devices have | |
1693 | * the wr_access and wr_data_mux_bus register fields. OMAP4+ | |
1694 | * devices support the addr-addr-data multiplex protocol. | |
1695 | * | |
1696 | * GPMC IP revisions: | |
1697 | * - OMAP24xx = 2.0 | |
1698 | * - OMAP3xxx = 5.0 | |
1699 | * - OMAP44xx/54xx/AM335x = 6.0 | |
1700 | */ | |
da496873 AM |
1701 | if (GPMC_REVISION_MAJOR(l) > 0x4) |
1702 | gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; | |
aa8d4767 JH |
1703 | if (GPMC_REVISION_MAJOR(l) > 0x5) |
1704 | gpmc_capability |= GPMC_HAS_MUX_AAD; | |
da496873 AM |
1705 | dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), |
1706 | GPMC_REVISION_MINOR(l)); | |
1707 | ||
84b00f0e | 1708 | gpmc_mem_init(); |
db97eb7d | 1709 | |
71856843 | 1710 | if (gpmc_setup_irq() < 0) |
da496873 AM |
1711 | dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); |
1712 | ||
31d9adca JH |
1713 | /* Now the GPMC is initialised, unreserve the chip-selects */ |
1714 | gpmc_cs_map = 0; | |
1715 | ||
f34f3716 GP |
1716 | if (!pdev->dev.of_node) { |
1717 | gpmc_cs_num = GPMC_CS_NUM; | |
9f833156 | 1718 | gpmc_nr_waitpins = GPMC_NR_WAITPINS; |
f34f3716 | 1719 | } |
9f833156 | 1720 | |
bc6b1e7b DM |
1721 | rc = gpmc_probe_dt(pdev); |
1722 | if (rc < 0) { | |
b3f5525c | 1723 | pm_runtime_put_sync(&pdev->dev); |
bc6b1e7b DM |
1724 | clk_put(gpmc_l3_clk); |
1725 | dev_err(gpmc_dev, "failed to probe DT parameters\n"); | |
1726 | return rc; | |
1727 | } | |
1728 | ||
da496873 AM |
1729 | return 0; |
1730 | } | |
1731 | ||
351a102d | 1732 | static int gpmc_remove(struct platform_device *pdev) |
da496873 AM |
1733 | { |
1734 | gpmc_free_irq(); | |
1735 | gpmc_mem_exit(); | |
b3f5525c | 1736 | pm_runtime_put_sync(&pdev->dev); |
1737 | pm_runtime_disable(&pdev->dev); | |
da496873 AM |
1738 | gpmc_dev = NULL; |
1739 | return 0; | |
1740 | } | |
1741 | ||
b536dd41 | 1742 | #ifdef CONFIG_PM_SLEEP |
1743 | static int gpmc_suspend(struct device *dev) | |
1744 | { | |
1745 | omap3_gpmc_save_context(); | |
1746 | pm_runtime_put_sync(dev); | |
1747 | return 0; | |
1748 | } | |
1749 | ||
1750 | static int gpmc_resume(struct device *dev) | |
1751 | { | |
1752 | pm_runtime_get_sync(dev); | |
1753 | omap3_gpmc_restore_context(); | |
1754 | return 0; | |
1755 | } | |
1756 | #endif | |
1757 | ||
1758 | static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume); | |
1759 | ||
da496873 AM |
1760 | static struct platform_driver gpmc_driver = { |
1761 | .probe = gpmc_probe, | |
351a102d | 1762 | .remove = gpmc_remove, |
da496873 AM |
1763 | .driver = { |
1764 | .name = DEVICE_NAME, | |
1765 | .owner = THIS_MODULE, | |
bc6b1e7b | 1766 | .of_match_table = of_match_ptr(gpmc_dt_ids), |
b536dd41 | 1767 | .pm = &gpmc_pm_ops, |
da496873 AM |
1768 | }, |
1769 | }; | |
1770 | ||
1771 | static __init int gpmc_init(void) | |
1772 | { | |
1773 | return platform_driver_register(&gpmc_driver); | |
1774 | } | |
1775 | ||
1776 | static __exit void gpmc_exit(void) | |
1777 | { | |
1778 | platform_driver_unregister(&gpmc_driver); | |
1779 | ||
db97eb7d | 1780 | } |
da496873 | 1781 | |
b76c8b19 | 1782 | omap_postcore_initcall(gpmc_init); |
da496873 | 1783 | module_exit(gpmc_exit); |
db97eb7d | 1784 | |
4be48fd5 AM |
1785 | static int __init omap_gpmc_init(void) |
1786 | { | |
1787 | struct omap_hwmod *oh; | |
1788 | struct platform_device *pdev; | |
1789 | char *oh_name = "gpmc"; | |
1790 | ||
2f98ca89 DM |
1791 | /* |
1792 | * if the board boots up with a populated DT, do not | |
1793 | * manually add the device from this initcall | |
1794 | */ | |
1795 | if (of_have_populated_dt()) | |
1796 | return -ENODEV; | |
1797 | ||
4be48fd5 AM |
1798 | oh = omap_hwmod_lookup(oh_name); |
1799 | if (!oh) { | |
1800 | pr_err("Could not look up %s\n", oh_name); | |
1801 | return -ENODEV; | |
1802 | } | |
1803 | ||
c1d1cd59 | 1804 | pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0); |
4be48fd5 AM |
1805 | WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); |
1806 | ||
1261674a | 1807 | return PTR_RET(pdev); |
4be48fd5 | 1808 | } |
b76c8b19 | 1809 | omap_postcore_initcall(omap_gpmc_init); |
4be48fd5 | 1810 | |
db97eb7d SG |
1811 | static irqreturn_t gpmc_handle_irq(int irq, void *dev) |
1812 | { | |
6b6c32fc AM |
1813 | int i; |
1814 | u32 regval; | |
1815 | ||
1816 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
1817 | ||
1818 | if (!regval) | |
1819 | return IRQ_NONE; | |
1820 | ||
1821 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
1822 | if (regval & gpmc_client_irq[i].bitmask) | |
1823 | generic_handle_irq(gpmc_client_irq[i].irq); | |
db97eb7d | 1824 | |
6b6c32fc | 1825 | gpmc_write_reg(GPMC_IRQSTATUS, regval); |
db97eb7d SG |
1826 | |
1827 | return IRQ_HANDLED; | |
4bbbc1ad | 1828 | } |
a2d3e7ba | 1829 | |
a2d3e7ba RN |
1830 | static struct omap3_gpmc_regs gpmc_context; |
1831 | ||
b2fa3b7c | 1832 | void omap3_gpmc_save_context(void) |
a2d3e7ba RN |
1833 | { |
1834 | int i; | |
b2fa3b7c | 1835 | |
a2d3e7ba RN |
1836 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); |
1837 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | |
1838 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | |
1839 | gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); | |
1840 | gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
1841 | gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); | |
1842 | gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); | |
f34f3716 | 1843 | for (i = 0; i < gpmc_cs_num; i++) { |
a2d3e7ba RN |
1844 | gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); |
1845 | if (gpmc_context.cs_context[i].is_valid) { | |
1846 | gpmc_context.cs_context[i].config1 = | |
1847 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); | |
1848 | gpmc_context.cs_context[i].config2 = | |
1849 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); | |
1850 | gpmc_context.cs_context[i].config3 = | |
1851 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); | |
1852 | gpmc_context.cs_context[i].config4 = | |
1853 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); | |
1854 | gpmc_context.cs_context[i].config5 = | |
1855 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); | |
1856 | gpmc_context.cs_context[i].config6 = | |
1857 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); | |
1858 | gpmc_context.cs_context[i].config7 = | |
1859 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); | |
1860 | } | |
1861 | } | |
1862 | } | |
1863 | ||
b2fa3b7c | 1864 | void omap3_gpmc_restore_context(void) |
a2d3e7ba RN |
1865 | { |
1866 | int i; | |
b2fa3b7c | 1867 | |
a2d3e7ba RN |
1868 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); |
1869 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | |
1870 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | |
1871 | gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); | |
1872 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); | |
1873 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); | |
1874 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); | |
f34f3716 | 1875 | for (i = 0; i < gpmc_cs_num; i++) { |
a2d3e7ba RN |
1876 | if (gpmc_context.cs_context[i].is_valid) { |
1877 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, | |
1878 | gpmc_context.cs_context[i].config1); | |
1879 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, | |
1880 | gpmc_context.cs_context[i].config2); | |
1881 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, | |
1882 | gpmc_context.cs_context[i].config3); | |
1883 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, | |
1884 | gpmc_context.cs_context[i].config4); | |
1885 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, | |
1886 | gpmc_context.cs_context[i].config5); | |
1887 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, | |
1888 | gpmc_context.cs_context[i].config6); | |
1889 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, | |
1890 | gpmc_context.cs_context[i].config7); | |
1891 | } | |
1892 | } | |
1893 | } |