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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
89d043c3 BD |
2 | /* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h |
3 | * | |
4 | * Copyright 2008 Openmoko, Inc. | |
5 | * Copyright 2008 Simtec Electronics | |
6 | * Ben Dooks <ben@simtec.co.uk> | |
7 | * http://armlinux.simtec.co.uk/ | |
8 | * | |
9 | * S3C64XX - GPIO register definitions | |
10 | */ | |
11 | ||
12 | #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H | |
13 | #define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__ | |
14 | ||
15 | /* Base addresses for each of the banks */ | |
16 | ||
33305373 BD |
17 | #define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg)) |
18 | ||
19 | #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000) | |
20 | #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020) | |
21 | #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040) | |
22 | #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060) | |
23 | #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080) | |
24 | #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0) | |
25 | #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0) | |
26 | #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0) | |
27 | #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100) | |
28 | #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120) | |
29 | #define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800) | |
30 | #define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810) | |
31 | #define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820) | |
32 | #define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830) | |
33 | #define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140) | |
34 | #define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160) | |
35 | #define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180) | |
36 | ||
e3837071 BD |
37 | /* SPCON */ |
38 | ||
39 | #define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0) | |
40 | ||
2454e524 BD |
41 | #define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30) |
42 | #define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30) | |
43 | #define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30) | |
44 | #define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30) | |
45 | #define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30) | |
46 | #define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30) | |
47 | ||
48 | #define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28) | |
49 | #define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28) | |
50 | #define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28) | |
51 | #define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28) | |
52 | #define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28) | |
53 | #define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28) | |
54 | ||
55 | #define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26) | |
56 | #define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26) | |
57 | #define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26) | |
58 | #define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26) | |
59 | #define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26) | |
60 | #define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26) | |
61 | ||
62 | #define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24) | |
63 | #define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24) | |
64 | #define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24) | |
65 | #define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24) | |
66 | #define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24) | |
67 | #define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24) | |
68 | ||
69 | #define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22) | |
70 | #define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22) | |
71 | #define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22) | |
72 | #define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22) | |
73 | #define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22) | |
74 | #define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22) | |
75 | ||
76 | #define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21) | |
77 | ||
78 | #define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18) | |
79 | #define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18) | |
80 | #define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18) | |
81 | #define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18) | |
82 | #define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18) | |
83 | #define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18) | |
84 | ||
85 | #define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16) | |
86 | #define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16) | |
87 | #define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16) | |
88 | #define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16) | |
89 | #define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16) | |
90 | ||
91 | #define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14) | |
92 | #define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14) | |
93 | #define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14) | |
94 | #define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14) | |
95 | #define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14) | |
96 | ||
97 | #define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12) | |
98 | #define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12) | |
99 | #define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12) | |
100 | #define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12) | |
101 | #define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12) | |
102 | ||
103 | #define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8) | |
104 | #define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8) | |
105 | #define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8) | |
106 | #define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8) | |
107 | #define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8) | |
108 | ||
109 | #define S3C64XX_SPCON_USBH_DMPD (1 << 7) | |
110 | #define S3C64XX_SPCON_USBH_DPPD (1 << 6) | |
111 | #define S3C64XX_SPCON_USBH_PUSW2 (1 << 5) | |
112 | #define S3C64XX_SPCON_USBH_PUSW1 (1 << 4) | |
113 | #define S3C64XX_SPCON_USBH_SUSPND (1 << 3) | |
114 | ||
115 | #define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0) | |
116 | #define S3C64XX_SPCON_LCD_SEL_SHIFT (0) | |
117 | #define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0) | |
118 | #define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0) | |
119 | #define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0) | |
120 | ||
121 | ||
33305373 BD |
122 | /* External interrupt registers */ |
123 | ||
124 | #define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200) | |
125 | #define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204) | |
126 | #define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208) | |
127 | #define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C) | |
128 | #define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210) | |
129 | ||
130 | #define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220) | |
131 | #define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224) | |
132 | #define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228) | |
133 | #define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C) | |
134 | #define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230) | |
135 | ||
136 | #define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240) | |
137 | #define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244) | |
138 | #define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248) | |
139 | #define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C) | |
140 | #define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250) | |
141 | ||
142 | #define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260) | |
143 | #define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264) | |
144 | #define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268) | |
145 | #define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C) | |
146 | #define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270) | |
147 | ||
148 | #define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280) | |
149 | #define S3C64XX_PRIORITY_ARB(x) (1 << (x)) | |
150 | ||
151 | #define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284) | |
152 | #define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288) | |
153 | ||
154 | #define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) | |
155 | #define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) | |
156 | #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) | |
157 | #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) | |
158 | #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) | |
159 | #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) | |
160 | ||
161 | #define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) | |
162 | #define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) | |
89d043c3 | 163 | |
e3837071 BD |
164 | /* GPIO sleep configuration */ |
165 | ||
166 | #define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880) | |
167 | ||
168 | #define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14) | |
169 | #define S3C64XX_SPCONSLP_CKE1INIT (1 << 5) | |
170 | ||
171 | #define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12) | |
172 | #define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12) | |
173 | #define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12) | |
174 | #define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12) | |
175 | ||
176 | #define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0) | |
177 | #define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0) | |
178 | #define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0) | |
179 | #define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0) | |
180 | ||
181 | ||
182 | #define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930) | |
183 | ||
184 | #define S3C64XX_SLPEN_USE_xSLP (1 << 0) | |
185 | #define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1) | |
186 | ||
89d043c3 BD |
187 | #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ |
188 |