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d2bab05a RK |
1 | /* |
2 | * linux/arch/arm/lib/copypage-armv4mc.S | |
3 | * | |
4 | * Copyright (C) 1995-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This handles the mini data cache, as found on SA11x0 and XScale | |
11 | * processors. When we copy a user page page, we map it in such a way | |
12 | * that accesses to this page will not touch the main data cache, but | |
13 | * will be cached in the mini data cache. This prevents us thrashing | |
14 | * the main data cache on page faults. | |
15 | */ | |
16 | #include <linux/init.h> | |
17 | #include <linux/mm.h> | |
063b0a42 | 18 | #include <linux/highmem.h> |
d2bab05a | 19 | |
d2bab05a RK |
20 | #include <asm/pgtable.h> |
21 | #include <asm/tlbflush.h> | |
1c9d3df5 | 22 | #include <asm/cacheflush.h> |
d2bab05a | 23 | |
1b2e2b73 RK |
24 | #include "mm.h" |
25 | ||
d2bab05a | 26 | #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ |
bb30f36f | 27 | L_PTE_MT_MINICACHE) |
d2bab05a | 28 | |
bd31b859 | 29 | static DEFINE_RAW_SPINLOCK(minicache_lock); |
d2bab05a RK |
30 | |
31 | /* | |
063b0a42 | 32 | * ARMv4 mini-dcache optimised copy_user_highpage |
d2bab05a RK |
33 | * |
34 | * We flush the destination cache lines just before we write the data into the | |
35 | * corresponding address. Since the Dcache is read-allocate, this removes the | |
36 | * Dcache aliasing issue. The writes will be forwarded to the write buffer, | |
37 | * and merged as appropriate. | |
38 | * | |
39 | * Note: We rely on all ARMv4 processors implementing the "invalidate D line" | |
40 | * instruction. If your processor does not supply this, you have to write your | |
063b0a42 | 41 | * own copy_user_highpage that does the right thing. |
d2bab05a | 42 | */ |
b99afae1 | 43 | static void mc_copy_user_page(void *from, void *to) |
d2bab05a | 44 | { |
b99afae1 NP |
45 | int tmp; |
46 | ||
47 | asm volatile ("\ | |
d2bab05a RK |
48 | ldmia %0!, {r2, r3, ip, lr} @ 4\n\ |
49 | 1: mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ | |
50 | stmia %1!, {r2, r3, ip, lr} @ 4\n\ | |
51 | ldmia %0!, {r2, r3, ip, lr} @ 4+1\n\ | |
52 | stmia %1!, {r2, r3, ip, lr} @ 4\n\ | |
53 | ldmia %0!, {r2, r3, ip, lr} @ 4\n\ | |
54 | mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ | |
55 | stmia %1!, {r2, r3, ip, lr} @ 4\n\ | |
56 | ldmia %0!, {r2, r3, ip, lr} @ 4\n\ | |
b99afae1 | 57 | subs %2, %2, #1 @ 1\n\ |
d2bab05a RK |
58 | stmia %1!, {r2, r3, ip, lr} @ 4\n\ |
59 | ldmneia %0!, {r2, r3, ip, lr} @ 4\n\ | |
b99afae1 NP |
60 | bne 1b @ " |
61 | : "+&r" (from), "+&r" (to), "=&r" (tmp) | |
62 | : "2" (PAGE_SIZE / 64) | |
63 | : "r2", "r3", "ip", "lr"); | |
d2bab05a RK |
64 | } |
65 | ||
7dd8c4f3 | 66 | void v4_mc_copy_user_highpage(struct page *to, struct page *from, |
f00a75c0 | 67 | unsigned long vaddr, struct vm_area_struct *vma) |
d2bab05a | 68 | { |
5472e862 | 69 | void *kto = kmap_atomic(to); |
1c9d3df5 | 70 | |
c0177800 | 71 | if (!test_and_set_bit(PG_dcache_clean, &from->flags)) |
cb9f753a | 72 | __flush_dcache_page(page_mapping_file(from), from); |
1c9d3df5 | 73 | |
bd31b859 | 74 | raw_spin_lock(&minicache_lock); |
d2bab05a | 75 | |
67ece144 | 76 | set_top_pte(COPYPAGE_MINICACHE, mk_pte(from, minicache_pgprot)); |
d2bab05a | 77 | |
de27c308 | 78 | mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto); |
d2bab05a | 79 | |
bd31b859 | 80 | raw_spin_unlock(&minicache_lock); |
063b0a42 | 81 | |
5472e862 | 82 | kunmap_atomic(kto); |
d2bab05a RK |
83 | } |
84 | ||
85 | /* | |
86 | * ARMv4 optimised clear_user_page | |
87 | */ | |
303c6443 | 88 | void v4_mc_clear_user_highpage(struct page *page, unsigned long vaddr) |
d2bab05a | 89 | { |
5472e862 | 90 | void *ptr, *kaddr = kmap_atomic(page); |
303c6443 | 91 | asm volatile("\ |
43ae286b | 92 | mov r1, %2 @ 1\n\ |
d2bab05a RK |
93 | mov r2, #0 @ 1\n\ |
94 | mov r3, #0 @ 1\n\ | |
95 | mov ip, #0 @ 1\n\ | |
96 | mov lr, #0 @ 1\n\ | |
303c6443 RK |
97 | 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ |
98 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ | |
99 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ | |
100 | mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ | |
101 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ | |
102 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ | |
d2bab05a | 103 | subs r1, r1, #1 @ 1\n\ |
303c6443 | 104 | bne 1b @ 1" |
43ae286b NP |
105 | : "=r" (ptr) |
106 | : "0" (kaddr), "I" (PAGE_SIZE / 64) | |
303c6443 | 107 | : "r1", "r2", "r3", "ip", "lr"); |
5472e862 | 108 | kunmap_atomic(kaddr); |
d2bab05a RK |
109 | } |
110 | ||
111 | struct cpu_user_fns v4_mc_user_fns __initdata = { | |
303c6443 | 112 | .cpu_clear_user_highpage = v4_mc_clear_user_highpage, |
063b0a42 | 113 | .cpu_copy_user_highpage = v4_mc_copy_user_highpage, |
d2bab05a | 114 | }; |