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1config ARM64
2 def_bool y
b6197b93 3 select ACPI_CCA_REQUIRED if ACPI
d8f4f161 4 select ACPI_GENERIC_GSI if ACPI
6933de0c 5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8c2c3df3 6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
2b68f6ca 7 select ARCH_HAS_ELF_RANDOMIZE
957e3fac 8 select ARCH_HAS_GCOV_PROFILE_ALL
308c09f1 9 select ARCH_HAS_SG_CHAIN
1f85008e 10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
c63c8700 11 select ARCH_USE_CMPXCHG_LOCKREF
4badad35 12 select ARCH_SUPPORTS_ATOMIC_RMW
9170100e 13 select ARCH_WANT_OPTIONAL_GPIOLIB
6212a512 14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
b6f35981 15 select ARCH_WANT_FRAME_POINTERS
25c92a37 16 select ARM_AMBA
1aee5d7a 17 select ARM_ARCH_TIMER
c4188edc 18 select ARM_GIC
875cbf3e 19 select AUDIT_ARCH_COMPAT_GENERIC
853a33ce 20 select ARM_GIC_V2M if PCI_MSI
021f6537 21 select ARM_GIC_V3
19812729 22 select ARM_GIC_V3_ITS if PCI_MSI
adace895 23 select BUILDTIME_EXTABLE_SORT
db2789b5 24 select CLONE_BACKWARDS
7ca2ef33 25 select COMMON_CLK
166936ba 26 select CPU_PM if (SUSPEND || CPU_IDLE)
7bc13fd3 27 select DCACHE_WORD_ACCESS
ef37566c 28 select EDAC_SUPPORT
d4932f9e 29 select GENERIC_ALLOCATOR
8c2c3df3 30 select GENERIC_CLOCKEVENTS
4b3dc967 31 select GENERIC_CLOCKEVENTS_BROADCAST
3be1a5c4 32 select GENERIC_CPU_AUTOPROBE
bf4b558e 33 select GENERIC_EARLY_IOREMAP
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34 select GENERIC_IRQ_PROBE
35 select GENERIC_IRQ_SHOW
6544e67b 36 select GENERIC_IRQ_SHOW_LEVEL
cb61f676 37 select GENERIC_PCI_IOMAP
65cd4f6c 38 select GENERIC_SCHED_CLOCK
8c2c3df3 39 select GENERIC_SMP_IDLE_THREAD
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40 select GENERIC_STRNCPY_FROM_USER
41 select GENERIC_STRNLEN_USER
8c2c3df3 42 select GENERIC_TIME_VSYSCALL
a1ddc74a 43 select HANDLE_DOMAIN_IRQ
8c2c3df3 44 select HARDIRQS_SW_RESEND
5284e1b4 45 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
875cbf3e 46 select HAVE_ARCH_AUDITSYSCALL
8e7a4cef 47 select HAVE_ARCH_BITREVERSE
9732cafd 48 select HAVE_ARCH_JUMP_LABEL
9529247d 49 select HAVE_ARCH_KGDB
a1ae65b2 50 select HAVE_ARCH_SECCOMP_FILTER
8c2c3df3 51 select HAVE_ARCH_TRACEHOOK
e54bcde3 52 select HAVE_BPF_JIT
af64d2aa 53 select HAVE_C_RECORDMCOUNT
c0c264ae 54 select HAVE_CC_STACKPROTECTOR
5284e1b4 55 select HAVE_CMPXCHG_DOUBLE
95eff6b2 56 select HAVE_CMPXCHG_LOCAL
9b2a60c4 57 select HAVE_DEBUG_BUGVERBOSE
b69ec42b 58 select HAVE_DEBUG_KMEMLEAK
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59 select HAVE_DMA_API_DEBUG
60 select HAVE_DMA_ATTRS
6ac2104d 61 select HAVE_DMA_CONTIGUOUS
bd7d38db 62 select HAVE_DYNAMIC_FTRACE
50afc33a 63 select HAVE_EFFICIENT_UNALIGNED_ACCESS
af64d2aa 64 select HAVE_FTRACE_MCOUNT_RECORD
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65 select HAVE_FUNCTION_TRACER
66 select HAVE_FUNCTION_GRAPH_TRACER
8c2c3df3 67 select HAVE_GENERIC_DMA_COHERENT
8c2c3df3 68 select HAVE_HW_BREAKPOINT if PERF_EVENTS
8c2c3df3 69 select HAVE_MEMBLOCK
55834a77 70 select HAVE_PATA_PLATFORM
8c2c3df3 71 select HAVE_PERF_EVENTS
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72 select HAVE_PERF_REGS
73 select HAVE_PERF_USER_STACK_DUMP
5e5f6dc1 74 select HAVE_RCU_TABLE_FREE
055b1212 75 select HAVE_SYSCALL_TRACEPOINTS
8c2c3df3 76 select IRQ_DOMAIN
e8557d1f 77 select IRQ_FORCED_THREADING
fea2acaa 78 select MODULES_USE_ELF_RELA
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79 select NO_BOOTMEM
80 select OF
81 select OF_EARLY_FLATTREE
9bf14b7c 82 select OF_RESERVED_MEM
8c2c3df3 83 select PERF_USE_VMALLOC
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84 select POWER_RESET
85 select POWER_SUPPLY
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86 select RTC_LIB
87 select SPARSE_IRQ
7ac57a89 88 select SYSCTL_EXCEPTION_TRACE
6c81fe79 89 select HAVE_CONTEXT_TRACKING
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90 help
91 ARM 64-bit (AArch64) Linux support.
92
93config 64BIT
94 def_bool y
95
96config ARCH_PHYS_ADDR_T_64BIT
97 def_bool y
98
99config MMU
100 def_bool y
101
ce816fa8 102config NO_IOPORT_MAP
d1e6dc91 103 def_bool y if !PCI
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104
105config STACKTRACE_SUPPORT
106 def_bool y
107
108config LOCKDEP_SUPPORT
109 def_bool y
110
111config TRACE_IRQFLAGS_SUPPORT
112 def_bool y
113
c209f799 114config RWSEM_XCHGADD_ALGORITHM
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115 def_bool y
116
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117config GENERIC_BUG
118 def_bool y
119 depends on BUG
120
121config GENERIC_BUG_RELATIVE_POINTERS
122 def_bool y
123 depends on GENERIC_BUG
124
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125config GENERIC_HWEIGHT
126 def_bool y
127
128config GENERIC_CSUM
129 def_bool y
130
131config GENERIC_CALIBRATE_DELAY
132 def_bool y
133
19e7640d 134config ZONE_DMA
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135 def_bool y
136
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137config HAVE_GENERIC_RCU_GUP
138 def_bool y
139
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140config ARCH_DMA_ADDR_T_64BIT
141 def_bool y
142
143config NEED_DMA_MAP_STATE
144 def_bool y
145
146config NEED_SG_DMA_LENGTH
147 def_bool y
148
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149config SMP
150 def_bool y
151
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152config SWIOTLB
153 def_bool y
154
155config IOMMU_HELPER
156 def_bool SWIOTLB
157
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158config KERNEL_MODE_NEON
159 def_bool y
160
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161config FIX_EARLYCON_MEM
162 def_bool y
163
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164config PGTABLE_LEVELS
165 int
166 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
167 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
168 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
169 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
170
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171source "init/Kconfig"
172
173source "kernel/Kconfig.freezer"
174
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175menu "Platform selection"
176
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177config ARCH_EXYNOS
178 bool
179 help
180 This enables support for Samsung Exynos SoC family
181
182config ARCH_EXYNOS7
183 bool "ARMv8 based Samsung Exynos7"
184 select ARCH_EXYNOS
185 select COMMON_CLK_SAMSUNG
186 select HAVE_S3C2410_WATCHDOG if WATCHDOG
187 select HAVE_S3C_RTC if RTC_CLASS
188 select PINCTRL
189 select PINCTRL_EXYNOS
190
191 help
192 This enables support for Samsung Exynos7 SoC family
193
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194config ARCH_FSL_LS2085A
195 bool "Freescale LS2085A SOC"
196 help
197 This enables support for Freescale LS2085A SOC.
198
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199config ARCH_HISI
200 bool "Hisilicon SoC Family"
201 help
202 This enables support for Hisilicon ARMv8 SoC family
203
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204config ARCH_MEDIATEK
205 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
206 select ARM_GIC
0a233cdf 207 select PINCTRL
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208 help
209 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
210
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211config ARCH_QCOM
212 bool "Qualcomm Platforms"
213 select PINCTRL
214 help
215 This enables support for the ARMv8 based Qualcomm chipsets.
216
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217config ARCH_SEATTLE
218 bool "AMD Seattle SoC Family"
219 help
220 This enables support for AMD Seattle SOC Family
221
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222config ARCH_TEGRA
223 bool "NVIDIA Tegra SoC Family"
224 select ARCH_HAS_RESET_CONTROLLER
225 select ARCH_REQUIRE_GPIOLIB
226 select CLKDEV_LOOKUP
227 select CLKSRC_MMIO
228 select CLKSRC_OF
229 select GENERIC_CLOCKEVENTS
230 select HAVE_CLK
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231 select PINCTRL
232 select RESET_CONTROLLER
233 help
234 This enables support for the NVIDIA Tegra SoC family.
235
236config ARCH_TEGRA_132_SOC
237 bool "NVIDIA Tegra132 SoC"
238 depends on ARCH_TEGRA
239 select PINCTRL_TEGRA124
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240 select USB_ULPI if USB_PHY
241 select USB_ULPI_VIEWPORT if USB_PHY
242 help
243 Enable support for NVIDIA Tegra132 SoC, based on the Denver
244 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
245 but contains an NVIDIA Denver CPU complex in place of
246 Tegra124's "4+1" Cortex-A15 CPU complex.
247
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248config ARCH_SPRD
249 bool "Spreadtrum SoC platform"
250 help
251 Support for Spreadtrum ARM based SoCs
252
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253config ARCH_THUNDER
254 bool "Cavium Inc. Thunder SoC Family"
255 help
256 This enables support for Cavium's Thunder Family of SoCs.
257
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258config ARCH_VEXPRESS
259 bool "ARMv8 software model (Versatile Express)"
260 select ARCH_REQUIRE_GPIOLIB
261 select COMMON_CLK_VERSATILE
aa1e8ec1 262 select POWER_RESET_VEXPRESS
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263 select VEXPRESS_CONFIG
264 help
265 This enables support for the ARMv8 software model (Versatile
266 Express).
8c2c3df3 267
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268config ARCH_XGENE
269 bool "AppliedMicro X-Gene SOC Family"
270 help
271 This enables support for AppliedMicro X-Gene SOC Family
272
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273config ARCH_ZYNQMP
274 bool "Xilinx ZynqMP Family"
275 help
276 This enables support for Xilinx ZynqMP Family
277
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278endmenu
279
280menu "Bus support"
281
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282config PCI
283 bool "PCI support"
284 help
285 This feature enables support for PCI bus system. If you say Y
286 here, the kernel will include drivers and infrastructure code
287 to support PCI bus devices.
288
289config PCI_DOMAINS
290 def_bool PCI
291
292config PCI_DOMAINS_GENERIC
293 def_bool PCI
294
295config PCI_SYSCALL
296 def_bool PCI
297
298source "drivers/pci/Kconfig"
299source "drivers/pci/pcie/Kconfig"
300source "drivers/pci/hotplug/Kconfig"
301
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302endmenu
303
304menu "Kernel Features"
305
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306menu "ARM errata workarounds via the alternatives framework"
307
308config ARM64_ERRATUM_826319
309 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
310 default y
311 help
312 This option adds an alternative code sequence to work around ARM
313 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
314 AXI master interface and an L2 cache.
315
316 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
317 and is unable to accept a certain write via this interface, it will
318 not progress on read data presented on the read data channel and the
319 system can deadlock.
320
321 The workaround promotes data cache clean instructions to
322 data cache clean-and-invalidate.
323 Please note that this does not necessarily enable the workaround,
324 as it depends on the alternative framework, which will only patch
325 the kernel if an affected CPU is detected.
326
327 If unsure, say Y.
328
329config ARM64_ERRATUM_827319
330 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
331 default y
332 help
333 This option adds an alternative code sequence to work around ARM
334 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
335 master interface and an L2 cache.
336
337 Under certain conditions this erratum can cause a clean line eviction
338 to occur at the same time as another transaction to the same address
339 on the AMBA 5 CHI interface, which can cause data corruption if the
340 interconnect reorders the two transactions.
341
342 The workaround promotes data cache clean instructions to
343 data cache clean-and-invalidate.
344 Please note that this does not necessarily enable the workaround,
345 as it depends on the alternative framework, which will only patch
346 the kernel if an affected CPU is detected.
347
348 If unsure, say Y.
349
350config ARM64_ERRATUM_824069
351 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
352 default y
353 help
354 This option adds an alternative code sequence to work around ARM
355 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
356 to a coherent interconnect.
357
358 If a Cortex-A53 processor is executing a store or prefetch for
359 write instruction at the same time as a processor in another
360 cluster is executing a cache maintenance operation to the same
361 address, then this erratum might cause a clean cache line to be
362 incorrectly marked as dirty.
363
364 The workaround promotes data cache clean instructions to
365 data cache clean-and-invalidate.
366 Please note that this option does not necessarily enable the
367 workaround, as it depends on the alternative framework, which will
368 only patch the kernel if an affected CPU is detected.
369
370 If unsure, say Y.
371
372config ARM64_ERRATUM_819472
373 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
374 default y
375 help
376 This option adds an alternative code sequence to work around ARM
377 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
378 present when it is connected to a coherent interconnect.
379
380 If the processor is executing a load and store exclusive sequence at
381 the same time as a processor in another cluster is executing a cache
382 maintenance operation to the same address, then this erratum might
383 cause data corruption.
384
385 The workaround promotes data cache clean instructions to
386 data cache clean-and-invalidate.
387 Please note that this does not necessarily enable the workaround,
388 as it depends on the alternative framework, which will only patch
389 the kernel if an affected CPU is detected.
390
391 If unsure, say Y.
392
393config ARM64_ERRATUM_832075
394 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
395 default y
396 help
397 This option adds an alternative code sequence to work around ARM
398 erratum 832075 on Cortex-A57 parts up to r1p2.
399
400 Affected Cortex-A57 parts might deadlock when exclusive load/store
401 instructions to Write-Back memory are mixed with Device loads.
402
403 The workaround is to promote device loads to use Load-Acquire
404 semantics.
405 Please note that this does not necessarily enable the workaround,
406 as it depends on the alternative framework, which will only patch
407 the kernel if an affected CPU is detected.
408
409 If unsure, say Y.
410
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411config ARM64_ERRATUM_845719
412 bool "Cortex-A53: 845719: a load might read incorrect data"
413 depends on COMPAT
414 default y
415 help
416 This option adds an alternative code sequence to work around ARM
417 erratum 845719 on Cortex-A53 parts up to r0p4.
418
419 When running a compat (AArch32) userspace on an affected Cortex-A53
420 part, a load at EL0 from a virtual address that matches the bottom 32
421 bits of the virtual address used by a recent load at (AArch64) EL1
422 might return incorrect data.
423
424 The workaround is to write the contextidr_el1 register on exception
425 return to a 32-bit task.
426 Please note that this does not necessarily enable the workaround,
427 as it depends on the alternative framework, which will only patch
428 the kernel if an affected CPU is detected.
429
430 If unsure, say Y.
431
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432endmenu
433
434
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435choice
436 prompt "Page size"
437 default ARM64_4K_PAGES
438 help
439 Page size (translation granule) configuration.
440
441config ARM64_4K_PAGES
442 bool "4KB"
443 help
444 This feature enables 4KB pages support.
445
8c2c3df3 446config ARM64_64K_PAGES
e41ceed0 447 bool "64KB"
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448 help
449 This feature enables 64KB pages support (4KB by default)
450 allowing only two levels of page tables and faster TLB
451 look-up. AArch32 emulation is not available when this feature
452 is enabled.
453
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454endchoice
455
456choice
457 prompt "Virtual address space size"
458 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
459 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
460 help
461 Allows choosing one of multiple possible virtual address
462 space sizes. The level of translation table is determined by
463 a combination of page size and virtual address space size.
464
465config ARM64_VA_BITS_39
466 bool "39-bit"
467 depends on ARM64_4K_PAGES
468
469config ARM64_VA_BITS_42
470 bool "42-bit"
471 depends on ARM64_64K_PAGES
472
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473config ARM64_VA_BITS_48
474 bool "48-bit"
c79b954b 475
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476endchoice
477
478config ARM64_VA_BITS
479 int
480 default 39 if ARM64_VA_BITS_39
481 default 42 if ARM64_VA_BITS_42
c79b954b 482 default 48 if ARM64_VA_BITS_48
e41ceed0 483
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484config ARM64_HW_AFDBM
485 bool "Support for hardware updates of the Access and Dirty page flags"
486 default y
487 help
488 The ARMv8.1 architecture extensions introduce support for
489 hardware updates of the access and dirty information in page
490 table entries. When enabled in TCR_EL1 (HA and HD bits) on
491 capable processors, accesses to pages with PTE_AF cleared will
492 set this bit instead of raising an access flag fault.
493 Similarly, writes to read-only pages with the DBM bit set will
494 clear the read-only bit (AP[2]) instead of raising a
495 permission fault.
496
497 Kernels built with this configuration option enabled continue
498 to work on pre-ARMv8.1 hardware and the performance impact is
499 minimal. If unsure, say Y.
500
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501config CPU_BIG_ENDIAN
502 bool "Build big-endian kernel"
503 help
504 Say Y if you plan on running a kernel in big-endian mode.
505
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506config SCHED_MC
507 bool "Multi-core scheduler support"
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508 help
509 Multi-core scheduler support improves the CPU scheduler's decision
510 making when dealing with multi-core CPU chips at a cost of slightly
511 increased overhead in some places. If unsure say N here.
512
513config SCHED_SMT
514 bool "SMT scheduler support"
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515 help
516 Improves the CPU scheduler's decision making when dealing with
517 MultiThreading at a cost of slightly increased overhead in some
518 places. If unsure say N here.
519
8c2c3df3 520config NR_CPUS
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521 int "Maximum number of CPUs (2-4096)"
522 range 2 4096
15942853 523 # These have to remain sorted largest to smallest
e3672649 524 default "64"
8c2c3df3 525
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526config HOTPLUG_CPU
527 bool "Support for hot-pluggable CPUs"
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528 help
529 Say Y here to experiment with turning CPUs off and on. CPUs
530 can be controlled through /sys/devices/system/cpu.
531
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532source kernel/Kconfig.preempt
533
534config HZ
535 int
536 default 100
537
538config ARCH_HAS_HOLES_MEMORYMODEL
539 def_bool y if SPARSEMEM
540
541config ARCH_SPARSEMEM_ENABLE
542 def_bool y
543 select SPARSEMEM_VMEMMAP_ENABLE
544
545config ARCH_SPARSEMEM_DEFAULT
546 def_bool ARCH_SPARSEMEM_ENABLE
547
548config ARCH_SELECT_MEMORY_MODEL
549 def_bool ARCH_SPARSEMEM_ENABLE
550
551config HAVE_ARCH_PFN_VALID
552 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
553
554config HW_PERF_EVENTS
555 bool "Enable hardware performance counter support for perf events"
556 depends on PERF_EVENTS
557 default y
558 help
559 Enable hardware performance counter support for perf events. If
560 disabled, perf events will use software events only.
561
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562config SYS_SUPPORTS_HUGETLBFS
563 def_bool y
564
565config ARCH_WANT_GENERAL_HUGETLB
566 def_bool y
567
568config ARCH_WANT_HUGE_PMD_SHARE
569 def_bool y if !ARM64_64K_PAGES
570
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571config HAVE_ARCH_TRANSPARENT_HUGEPAGE
572 def_bool y
573
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574config ARCH_HAS_CACHE_LINE_SIZE
575 def_bool y
576
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577source "mm/Kconfig"
578
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579config SECCOMP
580 bool "Enable seccomp to safely compute untrusted bytecode"
581 ---help---
582 This kernel feature is useful for number crunching applications
583 that may need to compute untrusted bytecode during their
584 execution. By using pipes or other transports made available to
585 the process as file descriptors supporting the read/write
586 syscalls, it's possible to isolate those applications in
587 their own address space using seccomp. Once seccomp is
588 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
589 and the task is only allowed to execute a few safe syscalls
590 defined by each seccomp mode.
591
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592config XEN_DOM0
593 def_bool y
594 depends on XEN
595
596config XEN
c2ba1f7d 597 bool "Xen guest support on ARM64"
aa42aa13 598 depends on ARM64 && OF
83862ccf 599 select SWIOTLB_XEN
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600 help
601 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
602
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603config FORCE_MAX_ZONEORDER
604 int
605 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
606 default "11"
607
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608config ARM64_PAN
609 bool "Enable support for Privileged Access Never (PAN)"
610 default y
611 help
612 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
613 prevents the kernel or hypervisor from accessing user-space (EL0)
614 memory directly.
615
616 Choosing this option will cause any unprotected (not using
617 copy_to_user et al) memory access to fail with a permission fault.
618
619 The feature is detected at runtime, and will remain as a 'nop'
620 instruction if the cpu does not implement the feature.
621
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622config ARM64_LSE_ATOMICS
623 bool "ARMv8.1 atomic instructions"
624 help
625 As part of the Large System Extensions, ARMv8.1 introduces new
626 atomic instructions that are designed specifically to scale in
627 very large systems.
628
629 Say Y here to make use of these instructions for the in-kernel
630 atomic routines. This incurs a small overhead on CPUs that do
631 not support these instructions and requires the kernel to be
632 built with binutils >= 2.25.
633
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634menuconfig ARMV8_DEPRECATED
635 bool "Emulate deprecated/obsolete ARMv8 instructions"
636 depends on COMPAT
637 help
638 Legacy software support may require certain instructions
639 that have been deprecated or obsoleted in the architecture.
640
641 Enable this config to enable selective emulation of these
642 features.
643
644 If unsure, say Y
645
646if ARMV8_DEPRECATED
647
648config SWP_EMULATION
649 bool "Emulate SWP/SWPB instructions"
650 help
651 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
652 they are always undefined. Say Y here to enable software
653 emulation of these instructions for userspace using LDXR/STXR.
654
655 In some older versions of glibc [<=2.8] SWP is used during futex
656 trylock() operations with the assumption that the code will not
657 be preempted. This invalid assumption may be more likely to fail
658 with SWP emulation enabled, leading to deadlock of the user
659 application.
660
661 NOTE: when accessing uncached shared regions, LDXR/STXR rely
662 on an external transaction monitoring block called a global
663 monitor to maintain update atomicity. If your system does not
664 implement a global monitor, this option can cause programs that
665 perform SWP operations to uncached memory to deadlock.
666
667 If unsure, say Y
668
669config CP15_BARRIER_EMULATION
670 bool "Emulate CP15 Barrier instructions"
671 help
672 The CP15 barrier instructions - CP15ISB, CP15DSB, and
673 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
674 strongly recommended to use the ISB, DSB, and DMB
675 instructions instead.
676
677 Say Y here to enable software emulation of these
678 instructions for AArch32 userspace code. When this option is
679 enabled, CP15 barrier usage is traced which can help
680 identify software that needs updating.
681
682 If unsure, say Y
683
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684config SETEND_EMULATION
685 bool "Emulate SETEND instruction"
686 help
687 The SETEND instruction alters the data-endianness of the
688 AArch32 EL0, and is deprecated in ARMv8.
689
690 Say Y here to enable software emulation of the instruction
691 for AArch32 userspace code.
692
693 Note: All the cpus on the system must have mixed endian support at EL0
694 for this feature to be enabled. If a new CPU - which doesn't support mixed
695 endian - is hotplugged in after this feature has been enabled, there could
696 be unexpected results in the applications.
697
698 If unsure, say Y
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699endif
700
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701endmenu
702
703menu "Boot options"
704
705config CMDLINE
706 string "Default kernel command string"
707 default ""
708 help
709 Provide a set of default command-line options at build time by
710 entering them here. As a minimum, you should specify the the
711 root device (e.g. root=/dev/nfs).
712
713config CMDLINE_FORCE
714 bool "Always use the default kernel command string"
715 help
716 Always use the default kernel command string, even if the boot
717 loader passes other arguments to the kernel.
718 This is useful if you cannot or don't want to change the
719 command-line options your boot loader passes to the kernel.
720
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721config EFI_STUB
722 bool
723
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724config EFI
725 bool "UEFI runtime support"
726 depends on OF && !CPU_BIG_ENDIAN
727 select LIBFDT
728 select UCS2_STRING
729 select EFI_PARAMS_FROM_FDT
e15dd494 730 select EFI_RUNTIME_WRAPPERS
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731 select EFI_STUB
732 select EFI_ARMSTUB
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733 default y
734 help
735 This option provides support for runtime services provided
736 by UEFI firmware (such as non-volatile variables, realtime
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737 clock, and platform reset). A UEFI stub is also provided to
738 allow the kernel to be booted as an EFI application. This
739 is only useful on systems that have UEFI firmware.
f84d0275 740
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741config DMI
742 bool "Enable support for SMBIOS (DMI) tables"
743 depends on EFI
744 default y
745 help
746 This enables SMBIOS/DMI feature for systems.
747
748 This option is only useful on systems that have UEFI firmware.
749 However, even with this option, the resultant kernel should
750 continue to boot on existing non-UEFI platforms.
751
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752endmenu
753
754menu "Userspace binary formats"
755
756source "fs/Kconfig.binfmt"
757
758config COMPAT
759 bool "Kernel support for 32-bit EL0"
a8fcd8b1 760 depends on !ARM64_64K_PAGES || EXPERT
8c2c3df3 761 select COMPAT_BINFMT_ELF
af1839eb 762 select HAVE_UID16
84b9e9b4 763 select OLD_SIGSUSPEND3
51682036 764 select COMPAT_OLD_SIGACTION
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765 help
766 This option enables support for a 32-bit EL0 running under a 64-bit
767 kernel at EL1. AArch32-specific components such as system calls,
768 the user helper functions, VFP support and the ptrace interface are
769 handled appropriately by the kernel.
770
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771 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
772 will only be able to execute AArch32 binaries that were compiled with
773 64k aligned segments.
774
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775 If you want to execute 32-bit userspace applications, say Y.
776
777config SYSVIPC_COMPAT
778 def_bool y
779 depends on COMPAT && SYSVIPC
780
781endmenu
782
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783menu "Power management options"
784
785source "kernel/power/Kconfig"
786
787config ARCH_SUSPEND_POSSIBLE
788 def_bool y
789
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790endmenu
791
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792menu "CPU Power Management"
793
794source "drivers/cpuidle/Kconfig"
795
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796source "drivers/cpufreq/Kconfig"
797
798endmenu
799
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800source "net/Kconfig"
801
802source "drivers/Kconfig"
803
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804source "drivers/firmware/Kconfig"
805
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806source "drivers/acpi/Kconfig"
807
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808source "fs/Kconfig"
809
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810source "arch/arm64/kvm/Kconfig"
811
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812source "arch/arm64/Kconfig.debug"
813
814source "security/Kconfig"
815
816source "crypto/Kconfig"
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817if CRYPTO
818source "arch/arm64/crypto/Kconfig"
819endif
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820
821source "lib/Kconfig"