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8eb99267 MZ |
1 | /* |
2 | * Copyright (C) 2015 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include <linux/compiler.h> | |
19 | #include <linux/kvm_host.h> | |
20 | ||
03336b1d | 21 | #include <asm/debug-monitors.h> |
9d8415d6 | 22 | #include <asm/kvm_asm.h> |
13720a56 | 23 | #include <asm/kvm_hyp.h> |
8eb99267 MZ |
24 | |
25 | #define read_debug(r,n) read_sysreg(r##n##_el1) | |
26 | #define write_debug(v,r,n) write_sysreg(v, r##n##_el1) | |
27 | ||
28 | #define save_debug(ptr,reg,nr) \ | |
29 | switch (nr) { \ | |
30 | case 15: ptr[15] = read_debug(reg, 15); \ | |
31 | case 14: ptr[14] = read_debug(reg, 14); \ | |
32 | case 13: ptr[13] = read_debug(reg, 13); \ | |
33 | case 12: ptr[12] = read_debug(reg, 12); \ | |
34 | case 11: ptr[11] = read_debug(reg, 11); \ | |
35 | case 10: ptr[10] = read_debug(reg, 10); \ | |
36 | case 9: ptr[9] = read_debug(reg, 9); \ | |
37 | case 8: ptr[8] = read_debug(reg, 8); \ | |
38 | case 7: ptr[7] = read_debug(reg, 7); \ | |
39 | case 6: ptr[6] = read_debug(reg, 6); \ | |
40 | case 5: ptr[5] = read_debug(reg, 5); \ | |
41 | case 4: ptr[4] = read_debug(reg, 4); \ | |
42 | case 3: ptr[3] = read_debug(reg, 3); \ | |
43 | case 2: ptr[2] = read_debug(reg, 2); \ | |
44 | case 1: ptr[1] = read_debug(reg, 1); \ | |
45 | default: ptr[0] = read_debug(reg, 0); \ | |
46 | } | |
47 | ||
48 | #define restore_debug(ptr,reg,nr) \ | |
49 | switch (nr) { \ | |
50 | case 15: write_debug(ptr[15], reg, 15); \ | |
51 | case 14: write_debug(ptr[14], reg, 14); \ | |
52 | case 13: write_debug(ptr[13], reg, 13); \ | |
53 | case 12: write_debug(ptr[12], reg, 12); \ | |
54 | case 11: write_debug(ptr[11], reg, 11); \ | |
55 | case 10: write_debug(ptr[10], reg, 10); \ | |
56 | case 9: write_debug(ptr[9], reg, 9); \ | |
57 | case 8: write_debug(ptr[8], reg, 8); \ | |
58 | case 7: write_debug(ptr[7], reg, 7); \ | |
59 | case 6: write_debug(ptr[6], reg, 6); \ | |
60 | case 5: write_debug(ptr[5], reg, 5); \ | |
61 | case 4: write_debug(ptr[4], reg, 4); \ | |
62 | case 3: write_debug(ptr[3], reg, 3); \ | |
63 | case 2: write_debug(ptr[2], reg, 2); \ | |
64 | case 1: write_debug(ptr[1], reg, 1); \ | |
65 | default: write_debug(ptr[0], reg, 0); \ | |
66 | } | |
67 | ||
f85279b4 WD |
68 | static void __hyp_text __debug_save_spe_vhe(u64 *pmscr_el1) |
69 | { | |
70 | /* The vcpu can run. but it can't hide. */ | |
71 | } | |
72 | ||
73 | static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1) | |
74 | { | |
75 | u64 reg; | |
76 | ||
bfe766cf JT |
77 | /* Clear pmscr in case of early return */ |
78 | *pmscr_el1 = 0; | |
79 | ||
f85279b4 WD |
80 | /* SPE present on this CPU? */ |
81 | if (!cpuid_feature_extract_unsigned_field(read_sysreg(id_aa64dfr0_el1), | |
82 | ID_AA64DFR0_PMSVER_SHIFT)) | |
83 | return; | |
84 | ||
85 | /* Yes; is it owned by EL3? */ | |
a173c390 WD |
86 | reg = read_sysreg_s(SYS_PMBIDR_EL1); |
87 | if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) | |
f85279b4 WD |
88 | return; |
89 | ||
90 | /* No; is the host actually using the thing? */ | |
a173c390 WD |
91 | reg = read_sysreg_s(SYS_PMBLIMITR_EL1); |
92 | if (!(reg & BIT(SYS_PMBLIMITR_EL1_E_SHIFT))) | |
f85279b4 WD |
93 | return; |
94 | ||
95 | /* Yes; save the control register and disable data generation */ | |
a173c390 WD |
96 | *pmscr_el1 = read_sysreg_s(SYS_PMSCR_EL1); |
97 | write_sysreg_s(0, SYS_PMSCR_EL1); | |
f85279b4 WD |
98 | isb(); |
99 | ||
100 | /* Now drain all buffered data to memory */ | |
101 | psb_csync(); | |
102 | dsb(nsh); | |
103 | } | |
104 | ||
105 | static hyp_alternate_select(__debug_save_spe, | |
106 | __debug_save_spe_nvhe, __debug_save_spe_vhe, | |
107 | ARM64_HAS_VIRT_HOST_EXTN); | |
108 | ||
109 | static void __hyp_text __debug_restore_spe(u64 pmscr_el1) | |
110 | { | |
111 | if (!pmscr_el1) | |
112 | return; | |
113 | ||
114 | /* The host page table is installed, but not yet synchronised */ | |
115 | isb(); | |
116 | ||
117 | /* Re-enable data generation */ | |
a173c390 | 118 | write_sysreg_s(pmscr_el1, SYS_PMSCR_EL1); |
f85279b4 WD |
119 | } |
120 | ||
8eb99267 MZ |
121 | void __hyp_text __debug_save_state(struct kvm_vcpu *vcpu, |
122 | struct kvm_guest_debug_arch *dbg, | |
123 | struct kvm_cpu_context *ctxt) | |
124 | { | |
125 | u64 aa64dfr0; | |
126 | int brps, wrps; | |
127 | ||
128 | if (!(vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY)) | |
129 | return; | |
130 | ||
131 | aa64dfr0 = read_sysreg(id_aa64dfr0_el1); | |
132 | brps = (aa64dfr0 >> 12) & 0xf; | |
133 | wrps = (aa64dfr0 >> 20) & 0xf; | |
134 | ||
135 | save_debug(dbg->dbg_bcr, dbgbcr, brps); | |
136 | save_debug(dbg->dbg_bvr, dbgbvr, brps); | |
137 | save_debug(dbg->dbg_wcr, dbgwcr, wrps); | |
138 | save_debug(dbg->dbg_wvr, dbgwvr, wrps); | |
139 | ||
140 | ctxt->sys_regs[MDCCINT_EL1] = read_sysreg(mdccint_el1); | |
141 | } | |
142 | ||
143 | void __hyp_text __debug_restore_state(struct kvm_vcpu *vcpu, | |
144 | struct kvm_guest_debug_arch *dbg, | |
145 | struct kvm_cpu_context *ctxt) | |
146 | { | |
147 | u64 aa64dfr0; | |
148 | int brps, wrps; | |
149 | ||
150 | if (!(vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY)) | |
151 | return; | |
152 | ||
153 | aa64dfr0 = read_sysreg(id_aa64dfr0_el1); | |
154 | ||
155 | brps = (aa64dfr0 >> 12) & 0xf; | |
156 | wrps = (aa64dfr0 >> 20) & 0xf; | |
157 | ||
158 | restore_debug(dbg->dbg_bcr, dbgbcr, brps); | |
159 | restore_debug(dbg->dbg_bvr, dbgbvr, brps); | |
160 | restore_debug(dbg->dbg_wcr, dbgwcr, wrps); | |
161 | restore_debug(dbg->dbg_wvr, dbgwvr, wrps); | |
162 | ||
163 | write_sysreg(ctxt->sys_regs[MDCCINT_EL1], mdccint_el1); | |
164 | } | |
165 | ||
166 | void __hyp_text __debug_cond_save_host_state(struct kvm_vcpu *vcpu) | |
167 | { | |
168 | /* If any of KDE, MDE or KVM_ARM64_DEBUG_DIRTY is set, perform | |
169 | * a full save/restore cycle. */ | |
170 | if ((vcpu->arch.ctxt.sys_regs[MDSCR_EL1] & DBG_MDSCR_KDE) || | |
171 | (vcpu->arch.ctxt.sys_regs[MDSCR_EL1] & DBG_MDSCR_MDE)) | |
172 | vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY; | |
173 | ||
f85279b4 | 174 | __debug_save_state(vcpu, &vcpu->arch.host_debug_state.regs, |
8eb99267 | 175 | kern_hyp_va(vcpu->arch.host_cpu_context)); |
f85279b4 | 176 | __debug_save_spe()(&vcpu->arch.host_debug_state.pmscr_el1); |
8eb99267 MZ |
177 | } |
178 | ||
179 | void __hyp_text __debug_cond_restore_host_state(struct kvm_vcpu *vcpu) | |
180 | { | |
f85279b4 WD |
181 | __debug_restore_spe(vcpu->arch.host_debug_state.pmscr_el1); |
182 | __debug_restore_state(vcpu, &vcpu->arch.host_debug_state.regs, | |
8eb99267 MZ |
183 | kern_hyp_va(vcpu->arch.host_cpu_context)); |
184 | ||
185 | if (vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY) | |
186 | vcpu->arch.debug_flags &= ~KVM_ARM64_DEBUG_DIRTY; | |
187 | } | |
188 | ||
cf0ba18a | 189 | u32 __hyp_text __kvm_get_mdcr_el2(void) |
8eb99267 MZ |
190 | { |
191 | return read_sysreg(mdcr_el2); | |
192 | } |