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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
51533b61 MS |
2 | #ifndef __iop_trigger_grp_defs_h |
3 | #define __iop_trigger_grp_defs_h | |
4 | ||
5 | /* | |
6 | * This file is autogenerated from | |
7 | * file: ../../inst/io_proc/rtl/iop_trigger_grp.r | |
8 | * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp | |
9 | * last modfied: Mon Apr 11 16:08:46 2005 | |
10 | * | |
11 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r | |
12 | * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ | |
13 | * Any changes here will be lost. | |
14 | * | |
15 | * -*- buffer-read-only: t -*- | |
16 | */ | |
17 | /* Main access macros */ | |
18 | #ifndef REG_RD | |
19 | #define REG_RD( scope, inst, reg ) \ | |
20 | REG_READ( reg_##scope##_##reg, \ | |
21 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
22 | #endif | |
23 | ||
24 | #ifndef REG_WR | |
25 | #define REG_WR( scope, inst, reg, val ) \ | |
26 | REG_WRITE( reg_##scope##_##reg, \ | |
27 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
28 | #endif | |
29 | ||
30 | #ifndef REG_RD_VECT | |
31 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
32 | REG_READ( reg_##scope##_##reg, \ | |
33 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
34 | (index) * STRIDE_##scope##_##reg ) | |
35 | #endif | |
36 | ||
37 | #ifndef REG_WR_VECT | |
38 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
39 | REG_WRITE( reg_##scope##_##reg, \ | |
40 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
41 | (index) * STRIDE_##scope##_##reg, (val) ) | |
42 | #endif | |
43 | ||
44 | #ifndef REG_RD_INT | |
45 | #define REG_RD_INT( scope, inst, reg ) \ | |
46 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
47 | #endif | |
48 | ||
49 | #ifndef REG_WR_INT | |
50 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
51 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
52 | #endif | |
53 | ||
54 | #ifndef REG_RD_INT_VECT | |
55 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
56 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
57 | (index) * STRIDE_##scope##_##reg ) | |
58 | #endif | |
59 | ||
60 | #ifndef REG_WR_INT_VECT | |
61 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
62 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
63 | (index) * STRIDE_##scope##_##reg, (val) ) | |
64 | #endif | |
65 | ||
66 | #ifndef REG_TYPE_CONV | |
67 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
68 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
69 | #endif | |
70 | ||
71 | #ifndef reg_page_size | |
72 | #define reg_page_size 8192 | |
73 | #endif | |
74 | ||
75 | #ifndef REG_ADDR | |
76 | #define REG_ADDR( scope, inst, reg ) \ | |
77 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
78 | #endif | |
79 | ||
80 | #ifndef REG_ADDR_VECT | |
81 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
82 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
83 | (index) * STRIDE_##scope##_##reg ) | |
84 | #endif | |
85 | ||
86 | /* C-code for register scope iop_trigger_grp */ | |
87 | ||
88 | #define STRIDE_iop_trigger_grp_rw_cfg 4 | |
89 | /* Register rw_cfg, scope iop_trigger_grp, type rw */ | |
90 | typedef struct { | |
91 | unsigned int action : 2; | |
92 | unsigned int once : 1; | |
93 | unsigned int trig : 3; | |
94 | unsigned int en_only_by_reg : 1; | |
95 | unsigned int dis_only_by_reg : 1; | |
96 | unsigned int dummy1 : 24; | |
97 | } reg_iop_trigger_grp_rw_cfg; | |
98 | #define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0 | |
99 | #define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0 | |
100 | ||
101 | /* Register rw_cmd, scope iop_trigger_grp, type rw */ | |
102 | typedef struct { | |
103 | unsigned int dis : 4; | |
104 | unsigned int en : 4; | |
105 | unsigned int dummy1 : 24; | |
106 | } reg_iop_trigger_grp_rw_cmd; | |
107 | #define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16 | |
108 | #define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16 | |
109 | ||
110 | /* Register rw_intr_mask, scope iop_trigger_grp, type rw */ | |
111 | typedef struct { | |
112 | unsigned int trig0 : 1; | |
113 | unsigned int trig1 : 1; | |
114 | unsigned int trig2 : 1; | |
115 | unsigned int trig3 : 1; | |
116 | unsigned int dummy1 : 28; | |
117 | } reg_iop_trigger_grp_rw_intr_mask; | |
118 | #define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20 | |
119 | #define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20 | |
120 | ||
121 | /* Register rw_ack_intr, scope iop_trigger_grp, type rw */ | |
122 | typedef struct { | |
123 | unsigned int trig0 : 1; | |
124 | unsigned int trig1 : 1; | |
125 | unsigned int trig2 : 1; | |
126 | unsigned int trig3 : 1; | |
127 | unsigned int dummy1 : 28; | |
128 | } reg_iop_trigger_grp_rw_ack_intr; | |
129 | #define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24 | |
130 | #define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24 | |
131 | ||
132 | /* Register r_intr, scope iop_trigger_grp, type r */ | |
133 | typedef struct { | |
134 | unsigned int trig0 : 1; | |
135 | unsigned int trig1 : 1; | |
136 | unsigned int trig2 : 1; | |
137 | unsigned int trig3 : 1; | |
138 | unsigned int dummy1 : 28; | |
139 | } reg_iop_trigger_grp_r_intr; | |
140 | #define REG_RD_ADDR_iop_trigger_grp_r_intr 28 | |
141 | ||
142 | /* Register r_masked_intr, scope iop_trigger_grp, type r */ | |
143 | typedef struct { | |
144 | unsigned int trig0 : 1; | |
145 | unsigned int trig1 : 1; | |
146 | unsigned int trig2 : 1; | |
147 | unsigned int trig3 : 1; | |
148 | unsigned int dummy1 : 28; | |
149 | } reg_iop_trigger_grp_r_masked_intr; | |
150 | #define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32 | |
151 | ||
152 | ||
153 | /* Constants */ | |
154 | enum { | |
155 | regk_iop_trigger_grp_fall = 0x00000002, | |
156 | regk_iop_trigger_grp_fall_lo = 0x00000006, | |
157 | regk_iop_trigger_grp_no = 0x00000000, | |
158 | regk_iop_trigger_grp_off = 0x00000000, | |
159 | regk_iop_trigger_grp_pulse = 0x00000000, | |
160 | regk_iop_trigger_grp_rise = 0x00000001, | |
161 | regk_iop_trigger_grp_rise_fall = 0x00000003, | |
162 | regk_iop_trigger_grp_rise_fall_hi = 0x00000007, | |
163 | regk_iop_trigger_grp_rise_fall_lo = 0x00000004, | |
164 | regk_iop_trigger_grp_rise_hi = 0x00000005, | |
165 | regk_iop_trigger_grp_rw_cfg_default = 0x000000c0, | |
166 | regk_iop_trigger_grp_rw_cfg_size = 0x00000004, | |
167 | regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000, | |
168 | regk_iop_trigger_grp_toggle = 0x00000003, | |
169 | regk_iop_trigger_grp_yes = 0x00000001 | |
170 | }; | |
171 | #endif /* __iop_trigger_grp_defs_h */ |