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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
51533b61 MS |
2 | #ifndef __marb_defs_h |
3 | #define __marb_defs_h | |
4 | ||
5 | /* | |
6 | * This file is autogenerated from | |
7 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | |
8 | * id: <not found> | |
9 | * last modfied: Mon Apr 11 16:12:16 2005 | |
10 | * | |
11 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r | |
12 | * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ | |
13 | * Any changes here will be lost. | |
14 | * | |
15 | * -*- buffer-read-only: t -*- | |
16 | */ | |
17 | /* Main access macros */ | |
18 | #ifndef REG_RD | |
19 | #define REG_RD( scope, inst, reg ) \ | |
20 | REG_READ( reg_##scope##_##reg, \ | |
21 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
22 | #endif | |
23 | ||
24 | #ifndef REG_WR | |
25 | #define REG_WR( scope, inst, reg, val ) \ | |
26 | REG_WRITE( reg_##scope##_##reg, \ | |
27 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
28 | #endif | |
29 | ||
30 | #ifndef REG_RD_VECT | |
31 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
32 | REG_READ( reg_##scope##_##reg, \ | |
33 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
34 | (index) * STRIDE_##scope##_##reg ) | |
35 | #endif | |
36 | ||
37 | #ifndef REG_WR_VECT | |
38 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
39 | REG_WRITE( reg_##scope##_##reg, \ | |
40 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
41 | (index) * STRIDE_##scope##_##reg, (val) ) | |
42 | #endif | |
43 | ||
44 | #ifndef REG_RD_INT | |
45 | #define REG_RD_INT( scope, inst, reg ) \ | |
46 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
47 | #endif | |
48 | ||
49 | #ifndef REG_WR_INT | |
50 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
51 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
52 | #endif | |
53 | ||
54 | #ifndef REG_RD_INT_VECT | |
55 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
56 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
57 | (index) * STRIDE_##scope##_##reg ) | |
58 | #endif | |
59 | ||
60 | #ifndef REG_WR_INT_VECT | |
61 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
62 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
63 | (index) * STRIDE_##scope##_##reg, (val) ) | |
64 | #endif | |
65 | ||
66 | #ifndef REG_TYPE_CONV | |
67 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
68 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
69 | #endif | |
70 | ||
71 | #ifndef reg_page_size | |
72 | #define reg_page_size 8192 | |
73 | #endif | |
74 | ||
75 | #ifndef REG_ADDR | |
76 | #define REG_ADDR( scope, inst, reg ) \ | |
77 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
78 | #endif | |
79 | ||
80 | #ifndef REG_ADDR_VECT | |
81 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
82 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
83 | (index) * STRIDE_##scope##_##reg ) | |
84 | #endif | |
85 | ||
86 | /* C-code for register scope marb */ | |
87 | ||
88 | #define STRIDE_marb_rw_int_slots 4 | |
89 | /* Register rw_int_slots, scope marb, type rw */ | |
90 | typedef struct { | |
91 | unsigned int owner : 4; | |
92 | unsigned int dummy1 : 28; | |
93 | } reg_marb_rw_int_slots; | |
94 | #define REG_RD_ADDR_marb_rw_int_slots 0 | |
95 | #define REG_WR_ADDR_marb_rw_int_slots 0 | |
96 | ||
97 | #define STRIDE_marb_rw_ext_slots 4 | |
98 | /* Register rw_ext_slots, scope marb, type rw */ | |
99 | typedef struct { | |
100 | unsigned int owner : 4; | |
101 | unsigned int dummy1 : 28; | |
102 | } reg_marb_rw_ext_slots; | |
103 | #define REG_RD_ADDR_marb_rw_ext_slots 256 | |
104 | #define REG_WR_ADDR_marb_rw_ext_slots 256 | |
105 | ||
106 | #define STRIDE_marb_rw_regs_slots 4 | |
107 | /* Register rw_regs_slots, scope marb, type rw */ | |
108 | typedef struct { | |
109 | unsigned int owner : 4; | |
110 | unsigned int dummy1 : 28; | |
111 | } reg_marb_rw_regs_slots; | |
112 | #define REG_RD_ADDR_marb_rw_regs_slots 512 | |
113 | #define REG_WR_ADDR_marb_rw_regs_slots 512 | |
114 | ||
115 | /* Register rw_intr_mask, scope marb, type rw */ | |
116 | typedef struct { | |
117 | unsigned int bp0 : 1; | |
118 | unsigned int bp1 : 1; | |
119 | unsigned int bp2 : 1; | |
120 | unsigned int bp3 : 1; | |
121 | unsigned int dummy1 : 28; | |
122 | } reg_marb_rw_intr_mask; | |
123 | #define REG_RD_ADDR_marb_rw_intr_mask 528 | |
124 | #define REG_WR_ADDR_marb_rw_intr_mask 528 | |
125 | ||
126 | /* Register rw_ack_intr, scope marb, type rw */ | |
127 | typedef struct { | |
128 | unsigned int bp0 : 1; | |
129 | unsigned int bp1 : 1; | |
130 | unsigned int bp2 : 1; | |
131 | unsigned int bp3 : 1; | |
132 | unsigned int dummy1 : 28; | |
133 | } reg_marb_rw_ack_intr; | |
134 | #define REG_RD_ADDR_marb_rw_ack_intr 532 | |
135 | #define REG_WR_ADDR_marb_rw_ack_intr 532 | |
136 | ||
137 | /* Register r_intr, scope marb, type r */ | |
138 | typedef struct { | |
139 | unsigned int bp0 : 1; | |
140 | unsigned int bp1 : 1; | |
141 | unsigned int bp2 : 1; | |
142 | unsigned int bp3 : 1; | |
143 | unsigned int dummy1 : 28; | |
144 | } reg_marb_r_intr; | |
145 | #define REG_RD_ADDR_marb_r_intr 536 | |
146 | ||
147 | /* Register r_masked_intr, scope marb, type r */ | |
148 | typedef struct { | |
149 | unsigned int bp0 : 1; | |
150 | unsigned int bp1 : 1; | |
151 | unsigned int bp2 : 1; | |
152 | unsigned int bp3 : 1; | |
153 | unsigned int dummy1 : 28; | |
154 | } reg_marb_r_masked_intr; | |
155 | #define REG_RD_ADDR_marb_r_masked_intr 540 | |
156 | ||
157 | /* Register rw_stop_mask, scope marb, type rw */ | |
158 | typedef struct { | |
159 | unsigned int dma0 : 1; | |
160 | unsigned int dma1 : 1; | |
161 | unsigned int dma2 : 1; | |
162 | unsigned int dma3 : 1; | |
163 | unsigned int dma4 : 1; | |
164 | unsigned int dma5 : 1; | |
165 | unsigned int dma6 : 1; | |
166 | unsigned int dma7 : 1; | |
167 | unsigned int dma8 : 1; | |
168 | unsigned int dma9 : 1; | |
169 | unsigned int cpui : 1; | |
170 | unsigned int cpud : 1; | |
171 | unsigned int iop : 1; | |
172 | unsigned int slave : 1; | |
173 | unsigned int dummy1 : 18; | |
174 | } reg_marb_rw_stop_mask; | |
175 | #define REG_RD_ADDR_marb_rw_stop_mask 544 | |
176 | #define REG_WR_ADDR_marb_rw_stop_mask 544 | |
177 | ||
178 | /* Register r_stopped, scope marb, type r */ | |
179 | typedef struct { | |
180 | unsigned int dma0 : 1; | |
181 | unsigned int dma1 : 1; | |
182 | unsigned int dma2 : 1; | |
183 | unsigned int dma3 : 1; | |
184 | unsigned int dma4 : 1; | |
185 | unsigned int dma5 : 1; | |
186 | unsigned int dma6 : 1; | |
187 | unsigned int dma7 : 1; | |
188 | unsigned int dma8 : 1; | |
189 | unsigned int dma9 : 1; | |
190 | unsigned int cpui : 1; | |
191 | unsigned int cpud : 1; | |
192 | unsigned int iop : 1; | |
193 | unsigned int slave : 1; | |
194 | unsigned int dummy1 : 18; | |
195 | } reg_marb_r_stopped; | |
196 | #define REG_RD_ADDR_marb_r_stopped 548 | |
197 | ||
198 | /* Register rw_no_snoop, scope marb, type rw */ | |
199 | typedef struct { | |
200 | unsigned int dma0 : 1; | |
201 | unsigned int dma1 : 1; | |
202 | unsigned int dma2 : 1; | |
203 | unsigned int dma3 : 1; | |
204 | unsigned int dma4 : 1; | |
205 | unsigned int dma5 : 1; | |
206 | unsigned int dma6 : 1; | |
207 | unsigned int dma7 : 1; | |
208 | unsigned int dma8 : 1; | |
209 | unsigned int dma9 : 1; | |
210 | unsigned int cpui : 1; | |
211 | unsigned int cpud : 1; | |
212 | unsigned int iop : 1; | |
213 | unsigned int slave : 1; | |
214 | unsigned int dummy1 : 18; | |
215 | } reg_marb_rw_no_snoop; | |
216 | #define REG_RD_ADDR_marb_rw_no_snoop 832 | |
217 | #define REG_WR_ADDR_marb_rw_no_snoop 832 | |
218 | ||
219 | /* Register rw_no_snoop_rq, scope marb, type rw */ | |
220 | typedef struct { | |
221 | unsigned int dummy1 : 10; | |
222 | unsigned int cpui : 1; | |
223 | unsigned int cpud : 1; | |
224 | unsigned int dummy2 : 20; | |
225 | } reg_marb_rw_no_snoop_rq; | |
226 | #define REG_RD_ADDR_marb_rw_no_snoop_rq 836 | |
227 | #define REG_WR_ADDR_marb_rw_no_snoop_rq 836 | |
228 | ||
229 | ||
230 | /* Constants */ | |
231 | enum { | |
232 | regk_marb_cpud = 0x0000000b, | |
233 | regk_marb_cpui = 0x0000000a, | |
234 | regk_marb_dma0 = 0x00000000, | |
235 | regk_marb_dma1 = 0x00000001, | |
236 | regk_marb_dma2 = 0x00000002, | |
237 | regk_marb_dma3 = 0x00000003, | |
238 | regk_marb_dma4 = 0x00000004, | |
239 | regk_marb_dma5 = 0x00000005, | |
240 | regk_marb_dma6 = 0x00000006, | |
241 | regk_marb_dma7 = 0x00000007, | |
242 | regk_marb_dma8 = 0x00000008, | |
243 | regk_marb_dma9 = 0x00000009, | |
244 | regk_marb_iop = 0x0000000c, | |
245 | regk_marb_no = 0x00000000, | |
246 | regk_marb_r_stopped_default = 0x00000000, | |
247 | regk_marb_rw_ext_slots_default = 0x00000000, | |
248 | regk_marb_rw_ext_slots_size = 0x00000040, | |
249 | regk_marb_rw_int_slots_default = 0x00000000, | |
250 | regk_marb_rw_int_slots_size = 0x00000040, | |
251 | regk_marb_rw_intr_mask_default = 0x00000000, | |
252 | regk_marb_rw_no_snoop_default = 0x00000000, | |
253 | regk_marb_rw_no_snoop_rq_default = 0x00000000, | |
254 | regk_marb_rw_regs_slots_default = 0x00000000, | |
255 | regk_marb_rw_regs_slots_size = 0x00000004, | |
256 | regk_marb_rw_stop_mask_default = 0x00000000, | |
257 | regk_marb_slave = 0x0000000d, | |
258 | regk_marb_yes = 0x00000001 | |
259 | }; | |
260 | #endif /* __marb_defs_h */ | |
261 | #ifndef __marb_bp_defs_h | |
262 | #define __marb_bp_defs_h | |
263 | ||
264 | /* | |
265 | * This file is autogenerated from | |
266 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | |
267 | * id: <not found> | |
268 | * last modfied: Mon Apr 11 16:12:16 2005 | |
269 | * | |
270 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r | |
271 | * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ | |
272 | * Any changes here will be lost. | |
273 | * | |
274 | * -*- buffer-read-only: t -*- | |
275 | */ | |
276 | /* Main access macros */ | |
277 | #ifndef REG_RD | |
278 | #define REG_RD( scope, inst, reg ) \ | |
279 | REG_READ( reg_##scope##_##reg, \ | |
280 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
281 | #endif | |
282 | ||
283 | #ifndef REG_WR | |
284 | #define REG_WR( scope, inst, reg, val ) \ | |
285 | REG_WRITE( reg_##scope##_##reg, \ | |
286 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
287 | #endif | |
288 | ||
289 | #ifndef REG_RD_VECT | |
290 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
291 | REG_READ( reg_##scope##_##reg, \ | |
292 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
293 | (index) * STRIDE_##scope##_##reg ) | |
294 | #endif | |
295 | ||
296 | #ifndef REG_WR_VECT | |
297 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
298 | REG_WRITE( reg_##scope##_##reg, \ | |
299 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
300 | (index) * STRIDE_##scope##_##reg, (val) ) | |
301 | #endif | |
302 | ||
303 | #ifndef REG_RD_INT | |
304 | #define REG_RD_INT( scope, inst, reg ) \ | |
305 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
306 | #endif | |
307 | ||
308 | #ifndef REG_WR_INT | |
309 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
310 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
311 | #endif | |
312 | ||
313 | #ifndef REG_RD_INT_VECT | |
314 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
315 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
316 | (index) * STRIDE_##scope##_##reg ) | |
317 | #endif | |
318 | ||
319 | #ifndef REG_WR_INT_VECT | |
320 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
321 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
322 | (index) * STRIDE_##scope##_##reg, (val) ) | |
323 | #endif | |
324 | ||
325 | #ifndef REG_TYPE_CONV | |
326 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
327 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
328 | #endif | |
329 | ||
330 | #ifndef reg_page_size | |
331 | #define reg_page_size 8192 | |
332 | #endif | |
333 | ||
334 | #ifndef REG_ADDR | |
335 | #define REG_ADDR( scope, inst, reg ) \ | |
336 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
337 | #endif | |
338 | ||
339 | #ifndef REG_ADDR_VECT | |
340 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
341 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
342 | (index) * STRIDE_##scope##_##reg ) | |
343 | #endif | |
344 | ||
345 | /* C-code for register scope marb_bp */ | |
346 | ||
347 | /* Register rw_first_addr, scope marb_bp, type rw */ | |
348 | typedef unsigned int reg_marb_bp_rw_first_addr; | |
349 | #define REG_RD_ADDR_marb_bp_rw_first_addr 0 | |
350 | #define REG_WR_ADDR_marb_bp_rw_first_addr 0 | |
351 | ||
352 | /* Register rw_last_addr, scope marb_bp, type rw */ | |
353 | typedef unsigned int reg_marb_bp_rw_last_addr; | |
354 | #define REG_RD_ADDR_marb_bp_rw_last_addr 4 | |
355 | #define REG_WR_ADDR_marb_bp_rw_last_addr 4 | |
356 | ||
357 | /* Register rw_op, scope marb_bp, type rw */ | |
358 | typedef struct { | |
359 | unsigned int rd : 1; | |
360 | unsigned int wr : 1; | |
361 | unsigned int rd_excl : 1; | |
362 | unsigned int pri_wr : 1; | |
363 | unsigned int us_rd : 1; | |
364 | unsigned int us_wr : 1; | |
365 | unsigned int us_rd_excl : 1; | |
366 | unsigned int us_pri_wr : 1; | |
367 | unsigned int dummy1 : 24; | |
368 | } reg_marb_bp_rw_op; | |
369 | #define REG_RD_ADDR_marb_bp_rw_op 8 | |
370 | #define REG_WR_ADDR_marb_bp_rw_op 8 | |
371 | ||
372 | /* Register rw_clients, scope marb_bp, type rw */ | |
373 | typedef struct { | |
374 | unsigned int dma0 : 1; | |
375 | unsigned int dma1 : 1; | |
376 | unsigned int dma2 : 1; | |
377 | unsigned int dma3 : 1; | |
378 | unsigned int dma4 : 1; | |
379 | unsigned int dma5 : 1; | |
380 | unsigned int dma6 : 1; | |
381 | unsigned int dma7 : 1; | |
382 | unsigned int dma8 : 1; | |
383 | unsigned int dma9 : 1; | |
384 | unsigned int cpui : 1; | |
385 | unsigned int cpud : 1; | |
386 | unsigned int iop : 1; | |
387 | unsigned int slave : 1; | |
388 | unsigned int dummy1 : 18; | |
389 | } reg_marb_bp_rw_clients; | |
390 | #define REG_RD_ADDR_marb_bp_rw_clients 12 | |
391 | #define REG_WR_ADDR_marb_bp_rw_clients 12 | |
392 | ||
393 | /* Register rw_options, scope marb_bp, type rw */ | |
394 | typedef struct { | |
395 | unsigned int wrap : 1; | |
396 | unsigned int dummy1 : 31; | |
397 | } reg_marb_bp_rw_options; | |
398 | #define REG_RD_ADDR_marb_bp_rw_options 16 | |
399 | #define REG_WR_ADDR_marb_bp_rw_options 16 | |
400 | ||
401 | /* Register r_brk_addr, scope marb_bp, type r */ | |
402 | typedef unsigned int reg_marb_bp_r_brk_addr; | |
403 | #define REG_RD_ADDR_marb_bp_r_brk_addr 20 | |
404 | ||
405 | /* Register r_brk_op, scope marb_bp, type r */ | |
406 | typedef struct { | |
407 | unsigned int rd : 1; | |
408 | unsigned int wr : 1; | |
409 | unsigned int rd_excl : 1; | |
410 | unsigned int pri_wr : 1; | |
411 | unsigned int us_rd : 1; | |
412 | unsigned int us_wr : 1; | |
413 | unsigned int us_rd_excl : 1; | |
414 | unsigned int us_pri_wr : 1; | |
415 | unsigned int dummy1 : 24; | |
416 | } reg_marb_bp_r_brk_op; | |
417 | #define REG_RD_ADDR_marb_bp_r_brk_op 24 | |
418 | ||
419 | /* Register r_brk_clients, scope marb_bp, type r */ | |
420 | typedef struct { | |
421 | unsigned int dma0 : 1; | |
422 | unsigned int dma1 : 1; | |
423 | unsigned int dma2 : 1; | |
424 | unsigned int dma3 : 1; | |
425 | unsigned int dma4 : 1; | |
426 | unsigned int dma5 : 1; | |
427 | unsigned int dma6 : 1; | |
428 | unsigned int dma7 : 1; | |
429 | unsigned int dma8 : 1; | |
430 | unsigned int dma9 : 1; | |
431 | unsigned int cpui : 1; | |
432 | unsigned int cpud : 1; | |
433 | unsigned int iop : 1; | |
434 | unsigned int slave : 1; | |
435 | unsigned int dummy1 : 18; | |
436 | } reg_marb_bp_r_brk_clients; | |
437 | #define REG_RD_ADDR_marb_bp_r_brk_clients 28 | |
438 | ||
439 | /* Register r_brk_first_client, scope marb_bp, type r */ | |
440 | typedef struct { | |
441 | unsigned int dma0 : 1; | |
442 | unsigned int dma1 : 1; | |
443 | unsigned int dma2 : 1; | |
444 | unsigned int dma3 : 1; | |
445 | unsigned int dma4 : 1; | |
446 | unsigned int dma5 : 1; | |
447 | unsigned int dma6 : 1; | |
448 | unsigned int dma7 : 1; | |
449 | unsigned int dma8 : 1; | |
450 | unsigned int dma9 : 1; | |
451 | unsigned int cpui : 1; | |
452 | unsigned int cpud : 1; | |
453 | unsigned int iop : 1; | |
454 | unsigned int slave : 1; | |
455 | unsigned int dummy1 : 18; | |
456 | } reg_marb_bp_r_brk_first_client; | |
457 | #define REG_RD_ADDR_marb_bp_r_brk_first_client 32 | |
458 | ||
459 | /* Register r_brk_size, scope marb_bp, type r */ | |
460 | typedef unsigned int reg_marb_bp_r_brk_size; | |
461 | #define REG_RD_ADDR_marb_bp_r_brk_size 36 | |
462 | ||
463 | /* Register rw_ack, scope marb_bp, type rw */ | |
464 | typedef unsigned int reg_marb_bp_rw_ack; | |
465 | #define REG_RD_ADDR_marb_bp_rw_ack 40 | |
466 | #define REG_WR_ADDR_marb_bp_rw_ack 40 | |
467 | ||
468 | ||
469 | /* Constants */ | |
470 | enum { | |
471 | regk_marb_bp_no = 0x00000000, | |
472 | regk_marb_bp_rw_op_default = 0x00000000, | |
473 | regk_marb_bp_rw_options_default = 0x00000000, | |
474 | regk_marb_bp_yes = 0x00000001 | |
475 | }; | |
476 | #endif /* __marb_bp_defs_h */ |