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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/bitops.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/pci.h> | |
5 | #include <asm/dma.h> | |
6 | #include <asm/io.h> | |
7 | #include <asm/processor.h> | |
8 | #include <asm/timer.h> | |
120fad72 | 9 | #include <asm/pci-direct.h> |
1da177e4 LT |
10 | |
11 | #include "cpu.h" | |
12 | ||
13 | /* | |
14 | * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU | |
15 | */ | |
5f0f1c16 | 16 | static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1) |
1da177e4 LT |
17 | { |
18 | unsigned char ccr2, ccr3; | |
19 | unsigned long flags; | |
20 | ||
21 | /* we test for DEVID by checking whether CCR3 is writable */ | |
22 | local_irq_save(flags); | |
23 | ccr3 = getCx86(CX86_CCR3); | |
24 | setCx86(CX86_CCR3, ccr3 ^ 0x80); | |
25 | getCx86(0xc0); /* dummy to change bus */ | |
26 | ||
27 | if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */ | |
28 | ccr2 = getCx86(CX86_CCR2); | |
29 | setCx86(CX86_CCR2, ccr2 ^ 0x04); | |
30 | getCx86(0xc0); /* dummy */ | |
31 | ||
32 | if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */ | |
33 | *dir0 = 0xfd; | |
34 | else { /* Cx486S A step */ | |
35 | setCx86(CX86_CCR2, ccr2); | |
36 | *dir0 = 0xfe; | |
37 | } | |
38 | } | |
39 | else { | |
40 | setCx86(CX86_CCR3, ccr3); /* restore CCR3 */ | |
41 | ||
42 | /* read DIR0 and DIR1 CPU registers */ | |
43 | *dir0 = getCx86(CX86_DIR0); | |
44 | *dir1 = getCx86(CX86_DIR1); | |
45 | } | |
46 | local_irq_restore(flags); | |
47 | } | |
48 | ||
49 | /* | |
50 | * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in | |
51 | * order to identify the Cyrix CPU model after we're out of setup.c | |
52 | * | |
53 | * Actually since bugs.h doesn't even reference this perhaps someone should | |
54 | * fix the documentation ??? | |
55 | */ | |
b4af3f7c | 56 | static unsigned char Cx86_dir0_msb __cpuinitdata = 0; |
1da177e4 | 57 | |
b4af3f7c | 58 | static char Cx86_model[][9] __cpuinitdata = { |
1da177e4 LT |
59 | "Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ", |
60 | "M II ", "Unknown" | |
61 | }; | |
b4af3f7c | 62 | static char Cx486_name[][5] __cpuinitdata = { |
1da177e4 LT |
63 | "SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx", |
64 | "SRx2", "DRx2" | |
65 | }; | |
b4af3f7c | 66 | static char Cx486S_name[][4] __cpuinitdata = { |
1da177e4 LT |
67 | "S", "S2", "Se", "S2e" |
68 | }; | |
b4af3f7c | 69 | static char Cx486D_name[][4] __cpuinitdata = { |
1da177e4 LT |
70 | "DX", "DX2", "?", "?", "?", "DX4" |
71 | }; | |
b4af3f7c MD |
72 | static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock"; |
73 | static char cyrix_model_mult1[] __cpuinitdata = "12??43"; | |
74 | static char cyrix_model_mult2[] __cpuinitdata = "12233445"; | |
1da177e4 LT |
75 | |
76 | /* | |
77 | * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old | |
78 | * BIOSes for compatibility with DOS games. This makes the udelay loop | |
79 | * work correctly, and improves performance. | |
80 | * | |
81 | * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP | |
82 | */ | |
83 | ||
84 | extern void calibrate_delay(void) __init; | |
85 | ||
b4af3f7c | 86 | static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c) |
1da177e4 LT |
87 | { |
88 | unsigned long flags; | |
89 | ||
90 | if (Cx86_dir0_msb == 3) { | |
91 | unsigned char ccr3, ccr5; | |
92 | ||
93 | local_irq_save(flags); | |
94 | ccr3 = getCx86(CX86_CCR3); | |
95 | setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ | |
96 | ccr5 = getCx86(CX86_CCR5); | |
97 | if (ccr5 & 2) | |
98 | setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */ | |
99 | setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ | |
100 | local_irq_restore(flags); | |
101 | ||
102 | if (ccr5 & 2) { /* possible wrong calibration done */ | |
103 | printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n"); | |
104 | calibrate_delay(); | |
105 | c->loops_per_jiffy = loops_per_jiffy; | |
106 | } | |
107 | } | |
108 | } | |
109 | ||
110 | ||
b4af3f7c | 111 | static void __cpuinit set_cx86_reorder(void) |
1da177e4 LT |
112 | { |
113 | u8 ccr3; | |
114 | ||
115 | printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n"); | |
116 | ccr3 = getCx86(CX86_CCR3); | |
117 |