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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/bitops.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/pci.h> | |
5 | #include <asm/dma.h> | |
6 | #include <asm/io.h> | |
7 | #include <asm/processor.h> | |
8 | #include <asm/timer.h> | |
9 | ||
10 | #include "cpu.h" | |
11 | ||
12 | /* | |
13 | * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU | |
14 | */ | |
5f0f1c16 | 15 | static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1) |
1da177e4 LT |
16 | { |
17 | unsigned char ccr2, ccr3; | |
18 | unsigned long flags; | |
19 | ||
20 | /* we test for DEVID by checking whether CCR3 is writable */ | |
21 | local_irq_save(flags); | |
22 | ccr3 = getCx86(CX86_CCR3); | |
23 | setCx86(CX86_CCR3, ccr3 ^ 0x80); | |
24 | getCx86(0xc0); /* dummy to change bus */ | |
25 | ||
26 | if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */ | |
27 | ccr2 = getCx86(CX86_CCR2); | |
28 | setCx86(CX86_CCR2, ccr2 ^ 0x04); | |
29 | getCx86(0xc0); /* dummy */ | |
30 | ||
31 | if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */ | |
32 | *dir0 = 0xfd; | |
33 | else { /* Cx486S A step */ | |
34 | setCx86(CX86_CCR2, ccr2); | |
35 | *dir0 = 0xfe; | |
36 | } | |
37 | } | |
38 | else { | |
39 | setCx86(CX86_CCR3, ccr3); /* restore CCR3 */ | |
40 | ||
41 | /* read DIR0 and DIR1 CPU registers */ | |
42 | *dir0 = getCx86(CX86_DIR0); | |
43 | *dir1 = getCx86(CX86_DIR1); | |
44 | } | |
45 | local_irq_restore(flags); | |
46 | } | |
47 | ||
48 | /* | |
49 | * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in | |
50 | * order to identify the Cyrix CPU model after we're out of setup.c | |
51 | * | |
52 | * Actually since bugs.h doesn't even reference this perhaps someone should | |
53 | * fix the documentation ??? | |
54 | */ | |
b4af3f7c | 55 | static unsigned char Cx86_dir0_msb __cpuinitdata = 0; |
1da177e4 | 56 | |
b4af3f7c | 57 | static char Cx86_model[][9] __cpuinitdata = { |
1da177e4 LT |
58 | "Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ", |
59 | "M II ", "Unknown" | |
60 | }; | |
b4af3f7c | 61 | static char Cx486_name[][5] __cpuinitdata = { |
1da177e4 LT |
62 | "SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx", |
63 | "SRx2", "DRx2" | |
64 | }; | |
b4af3f7c | 65 | static char Cx486S_name[][4] __cpuinitdata = { |
1da177e4 LT |
66 | "S", "S2", "Se", "S2e" |
67 | }; | |
b4af3f7c | 68 | static char Cx486D_name[][4] __cpuinitdata = { |
1da177e4 LT |
69 | "DX", "DX2", "?", "?", "?", "DX4" |
70 | }; | |
b4af3f7c MD |
71 | static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock"; |
72 | static char cyrix_model_mult1[] __cpuinitdata = "12??43"; | |
73 | static char cyrix_model_mult2[] __cpuinitdata = "12233445"; | |
1da177e4 LT |
74 | |
75 | /* | |
76 | * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old | |
77 | * BIOSes for compatibility with DOS games. This makes the udelay loop | |
78 | * work correctly, and improves performance. | |
79 | * | |
80 | * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP | |
81 | */ | |
82 | ||
83 | extern void calibrate_delay(void) __init; | |
84 | ||
b4af3f7c | 85 | static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c) |
1da177e4 LT |
86 | { |
87 | unsigned long flags; | |
88 | ||
89 | if (Cx86_dir0_msb == 3) { | |
90 | unsigned char ccr3, ccr5; | |
91 | ||
92 | local_irq_save(flags); | |
93 | ccr3 = getCx86(CX86_CCR3); | |
94 | setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ | |
95 | ccr5 = getCx86(CX86_CCR5); | |
96 | if (ccr5 & 2) | |
97 | setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */ | |
98 | setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ | |
99 | local_irq_restore(flags); | |
100 | ||
101 | if (ccr5 & 2) { /* possible wrong calibration done */ | |
102 | printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n"); | |
103 | calibrate_delay(); | |
104 | c->loops_per_jiffy = loops_per_jiffy; | |
105 | } | |
106 | } | |
107 | } | |
108 | ||
109 | ||
b4af3f7c | 110 | static void __cpuinit set_cx86_reorder(void) |
1da177e4 LT |
111 | { |
112 | u8 ccr3; | |
113 | ||
114 | printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n"); | |
115 | ccr3 = getCx86(CX86_CCR3); | |
116 |