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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | /****************************************************************************/ |
3 | ||
4 | /* | |
5 | * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. | |
6 | * | |
7 | * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) | |
8 | */ | |
9 | ||
10 | /****************************************************************************/ | |
11 | #ifndef m527xsim_h | |
12 | #define m527xsim_h | |
13 | /****************************************************************************/ | |
14 | ||
733f31b7 GU |
15 | #define CPU_NAME "COLDFIRE(m527x)" |
16 | #define CPU_INSTR_PER_JIFFY 3 | |
ce3de78a | 17 | #define MCF_BUSCLK (MCF_CLK / 2) |
7fc82b65 | 18 | |
a12cf0a8 | 19 | #include <asm/m52xxacr.h> |
1da177e4 LT |
20 | |
21 | /* | |
22 | * Define the 5270/5271 SIM register set addresses. | |
23 | */ | |
254eef74 GU |
24 | #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ |
25 | #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */ | |
26 | ||
1da177e4 LT |
27 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
28 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | |
29 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | |
30 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | |
31 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | |
32 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | |
33 | #define MCFINTC_IRLR 0x18 /* */ | |
34 | #define MCFINTC_IACKL 0x19 /* */ | |
35 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | |
36 | ||
37 | #define MCFINT_VECBASE 64 /* Vector base number */ | |
38 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ | |
39 | #define MCFINT_UART1 14 /* Interrupt number for UART1 */ | |
40 | #define MCFINT_UART2 15 /* Interrupt number for UART2 */ | |
2d24b532 | 41 | #define MCFINT_I2C0 17 /* Interrupt number for I2C */ |
91d60417 | 42 | #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ |
308bfc12 GU |
43 | #define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */ |
44 | #define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */ | |
45 | #define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */ | |
1da177e4 LT |
46 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ |
47 | ||
308bfc12 GU |
48 | #define MCFINT2_VECBASE 128 /* Vector base number 2 */ |
49 | #define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */ | |
50 | #define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */ | |
51 | #define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */ | |
52 | ||
20e681fd GU |
53 | #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) |
54 | #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) | |
55 | #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) | |
56 | ||
308bfc12 GU |
57 | #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) |
58 | #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) | |
59 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) | |
60 | #define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1) | |
61 | #define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1) | |
62 | #define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) | |
63 | ||
6c84a60e | 64 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
bdee4e26 | 65 | #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) |
2d24b532 | 66 | #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) |
6c84a60e | 67 | |
1da177e4 LT |
68 | /* |
69 | * SDRAM configuration registers. | |
70 | */ | |
d871629b | 71 | #ifdef CONFIG_M5271 |
6a92e198 GU |
72 | #define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */ |
73 | #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ | |
74 | #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ | |
75 | #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ | |
76 | #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ | |
d871629b GU |
77 | #endif |
78 | #ifdef CONFIG_M5275 | |
6a92e198 GU |
79 | #define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */ |
80 | #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ | |
81 | #define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */ | |
82 | #define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */ | |
83 | #define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */ | |
84 | #define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */ | |
85 | #define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */ | |
86 | #define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */ | |
1da177e4 LT |
87 | #endif |
88 | ||
babc08b7 GU |
89 | /* |
90 | * DMA unit base addresses. | |
91 | */ | |
92 | #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) | |
93 | #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) | |
94 | #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) | |
95 | #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) | |
96 | ||
57015421 GU |
97 | /* |
98 | * UART module. | |
99 | */ | |
20e681fd GU |
100 | #define MCFUART_BASE0 (MCF_IPSBAR + 0x200) |
101 | #define MCFUART_BASE1 (MCF_IPSBAR + 0x240) | |
102 | #define MCFUART_BASE2 (MCF_IPSBAR + 0x280) | |
9a6b0c73 GU |
103 | |
104 | /* | |
105 | * FEC ethernet module. | |
106 | */ | |
107 | #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) | |
108 | #define MCFFEC_SIZE0 0x800 | |
a630ec1b | 109 | #ifdef CONFIG_M5275 |
9a6b0c73 GU |
110 | #define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) |
111 | #define MCFFEC_SIZE1 0x800 | |
a630ec1b | 112 | #endif |
f1554da3 | 113 | |
6c84a60e GU |
114 | /* |
115 | * QSPI module. | |
116 | */ | |
117 | #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) | |
118 | #define MCFQSPI_SIZE 0x40 | |
119 | ||
120 | #ifdef CONFIG_M5271 | |
121 | #define MCFQSPI_CS0 91 | |
122 | #define MCFQSPI_CS1 92 | |
123 | #define MCFQSPI_CS2 99 | |
124 | #define MCFQSPI_CS3 103 | |
125 | #endif | |
126 | #ifdef CONFIG_M5275 | |
127 | #define MCFQSPI_CS0 59 | |
128 | #define MCFQSPI_CS1 60 | |
129 | #define MCFQSPI_CS2 61 | |
130 | #define MCFQSPI_CS3 62 | |
131 | #endif | |
132 | ||
133 | /* | |
134 | * GPIO module. | |
135 | */ | |
f1554da3 | 136 | #ifdef CONFIG_M5271 |
137 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) | |
138 | #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) | |
139 | #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) | |
140 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) | |
141 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) | |
142 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) | |
143 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) | |
144 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) | |
145 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) | |
146 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) | |
147 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) | |
148 | #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) | |
149 | ||
150 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) | |
151 | #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) | |
152 | #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) | |
153 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) | |
154 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) | |
155 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) | |
156 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) | |
157 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) | |
158 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) | |
159 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) | |
160 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) | |
161 | #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) | |
162 | ||
163 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) | |
164 | #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) | |
165 | #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) | |
166 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) | |
167 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) | |
168 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) | |
169 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) | |
170 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) | |
171 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) | |
172 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) | |
173 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) | |
174 | #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) | |
175 | ||
176 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) | |
177 | #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) | |
178 | #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) | |
179 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) | |
180 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) | |
181 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) | |
182 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) | |
183 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) | |
184 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) | |
185 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) | |
186 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) | |
187 | #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) | |
188 | ||
189 | /* | |
190 | * Generic GPIO support | |
191 | */ | |
39dc5b7f GU |
192 | #define MCFGPIO_PODR MCFGPIO_PODR_ADDR |
193 | #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR | |
194 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR | |
195 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR | |
196 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR | |
f1554da3 | 197 | |
39dc5b7f GU |
198 | #define MCFGPIO_PIN_MAX 100 |
199 | #define MCFGPIO_IRQ_MAX 8 | |
200 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | |
91d60417 | 201 | |
f821e349 GU |
202 | /* |
203 | * Port Pin Assignment registers. | |
204 | */ | |
205 | #define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040) | |
206 | #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042) | |
207 | #define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044) | |
208 | #define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045) | |
209 | #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046) | |
210 | #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047) | |
211 | #define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048) | |
91d60417 SK |
212 | #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) |
213 | #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) | |
f821e349 GU |
214 | |
215 | #define UART0_ENABLE_MASK 0x000f | |
216 | #define UART1_ENABLE_MASK 0x0ff0 | |
217 | #define UART2_ENABLE_MASK 0x3000 | |
218 | #endif /* CONFIG_M5271 */ | |
f1554da3 | 219 | |
220 | #ifdef CONFIG_M5275 | |
221 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) | |
222 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005) | |
223 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008) | |
224 | #define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A) | |
225 | #define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B) | |
226 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C) | |
227 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D) | |
228 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E) | |
229 | #define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F) | |
230 | #define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010) | |
231 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011) | |
232 | #define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012) | |
233 | #define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013) | |
234 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014) | |
235 | #define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015) | |
236 | #define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016) | |
237 | #define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017) | |
238 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018) | |
239 | ||
240 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020) | |
241 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021) | |
242 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024) | |
243 | #define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026) | |
244 | #define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027) | |
245 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028) | |
246 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029) | |
247 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A) | |
248 | #define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B) | |
249 | #define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C) | |
250 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D) | |
251 | #define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E) | |
252 | #define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F) | |
253 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030) | |
254 | #define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031) | |
255 | #define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032) | |
256 | #define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033) | |
257 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034) | |
258 | ||
259 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C) | |
260 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D) | |
261 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040) | |
262 | #define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042) | |
263 | #define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043) | |
264 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044) | |
265 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045) | |
266 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046) | |
267 | #define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047) | |
268 | #define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048) | |
269 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049) | |
270 | #define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A) | |
271 | #define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B) | |
272 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C) | |
273 | #define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D) | |
274 | #define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E) | |
275 | #define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F) | |
276 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050) | |
277 | ||
278 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058) | |
279 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059) | |
280 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C) | |
281 | #define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E) | |
282 | #define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F) | |
283 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060) | |
284 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061) | |
285 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062) | |
286 | #define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063) | |
287 | #define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064) | |
288 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065) | |
289 | #define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066) | |
290 | #define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067) | |
291 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068) | |
292 | #define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069) | |
293 | #define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A) | |
294 | #define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B) | |
295 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C) | |
296 | ||
297 | ||
298 | /* | |
299 | * Generic GPIO support | |
300 | */ | |
39dc5b7f GU |
301 | #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL |
302 | #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL | |
303 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL | |
304 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL | |
305 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL | |
306 | ||
307 | #define MCFGPIO_PIN_MAX 148 | |
308 | #define MCFGPIO_IRQ_MAX 8 | |
309 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | |
91d60417 | 310 | |
f821e349 GU |
311 | /* |
312 | * Port Pin Assignment registers. | |
313 | */ | |
314 | #define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070) | |
315 | #define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071) | |
316 | #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072) | |
317 | #define MCFGPIO_PAR_USB (MCF_IPSBAR + 0x100076) | |
318 | #define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078) | |
319 | #define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079) | |
320 | #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10007A) | |
321 | #define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x10007C) | |
91d60417 | 322 | #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) |
f821e349 GU |
323 | #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100080) |
324 | #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082) | |
325 | #define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084) | |
326 | ||
327 | #define UART0_ENABLE_MASK 0x000f | |
328 | #define UART1_ENABLE_MASK 0x00f0 | |
329 | #define UART2_ENABLE_MASK 0x3f00 | |
330 | #endif /* CONFIG_M5275 */ | |
f1554da3 | 331 | |
332 | /* | |
f317c71a | 333 | * PIT timer base addresses. |
f1554da3 | 334 | */ |
f317c71a GU |
335 | #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) |
336 | #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) | |
337 | #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) | |
338 | #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) | |
f1554da3 | 339 | |
f317c71a GU |
340 | /* |
341 | * EPort | |
342 | */ | |
57b48143 | 343 | #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) |
f1554da3 | 344 | #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) |
57b48143 | 345 | #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) |
f1554da3 | 346 | #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) |
347 | #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) | |
57b48143 | 348 | #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) |
f1554da3 | 349 | |
4c0b008d | 350 | /* |
25985edc | 351 | * Reset Control Unit (relative to IPSBAR). |
4c0b008d | 352 | */ |
0b2a2139 GU |
353 | #define MCF_RCR (MCF_IPSBAR + 0x110000) |
354 | #define MCF_RSR (MCF_IPSBAR + 0x110001) | |
4c0b008d GU |
355 | |
356 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ | |
357 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ | |
358 | ||
2d24b532 SK |
359 | /* |
360 | * I2C module. | |
361 | */ | |
362 | #define MCFI2C_BASE0 (MCF_IPSBAR + 0x300) | |
363 | #define MCFI2C_SIZE0 0x40 | |
364 | ||
1da177e4 LT |
365 | /****************************************************************************/ |
366 | #endif /* m527xsim_h */ |