[mirror_ubuntu-disco-kernel.git] / arch / mips / boot / dts / brcm / bcm7360.dtsi

// SPDX-License-Identifier: GPL-2.0
/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "brcm,bcm7360";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		mips-hpt-frequency = <375000000>;

		cpu@0 {
			compatible = "brcm,bmips3300";
			device_type = "cpu";
			reg = <0>;
		};
	};

	aliases {
		uart0 = &uart0;
	};

	cpu_intc: interrupt-controller {
		#address-cells = <0>;
		compatible = "mti,cpu-interrupt-controller";

		interrupt-controller;
		#interrupt-cells = <1>;
	};

	clocks {
		uart_clk: uart_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <81000000>;
		};

		upg_clk: upg_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
		};
	};

	rdb {
		#address-cells = <1>;
		#size-cells = <1>;

		compatible = "simple-bus";
		ranges = <0 0x10000000 0x01000000>;

		periph_intc: interrupt-controller@411400 {
			compatible = "brcm,bcm7038-l1-intc";
			reg = <0x411400 0x30>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&cpu_intc>;
			interrupts = <2>;
		};

		sun_l2_intc: interrupt-controller@403000 {
			compatible = "brcm,l2-intc";
			reg = <0x403000 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&periph_intc>;
			interrupts = <48>;
		};

		gisb-arb@400000 {
			compatible = "brcm,bcm7400-gisb-arb";
			reg = <0x400000 0xdc>;
			native-endian;
			interrupt-parent = <&sun_l2_intc>;
			interrupts = <0>, <2>;
			brcm,gisb-arb-master-mask = <0x2f3>;
			brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
						     "rdc_0", "raaga_0",
						     "avd_0", "jtag_0";
		};

		upg_irq0_intc: interrupt-controller@406600 {
			compatible = "brcm,bcm7120-l2-intc";
			reg = <0x406600 0x8>;

			brcm,int-map-mask = <0x44>, <0x7000000>;
			brcm,int-fwd-mask = <0x70000>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&periph_intc>;
			interrupts = <56>, <54>;
			interrupt-names = "upg_main", "upg_bsc";
		};

		upg_aon_irq0_intc: interrupt-controller@408b80 {
			compatible = "brcm,bcm7120-l2-intc";
			reg = <0x408b80 0x8>;

			brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
			brcm,int-fwd-mask = <0>;
			brcm,irq-can-wake;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&periph_intc>;
			interrupts = <57>, <55>, <59>;
			interrupt-names = "upg_main_aon", "upg_bsc_aon",
					  "upg_spi";
		};

		sun_top_ctrl: syscon@404000 {
			compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
			reg = <0x404000 0x51c>;
			native-endian;
		};

		reboot {
			compatible = "brcm,brcmstb-reboot";
			syscon = <&sun_top_ctrl 0x304 0x308>;
		};

		uart0: serial@406800 {
			compatible = "ns16550a";
			reg = <0x406800 0x20>;
			reg-io-width = <0x4>;
			reg-shift = <0x2>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <61>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart1: serial@406840 {
			compatible = "ns16550a";
			reg = <0x406840 0x20>;
			reg-io-width = <0x4>;
			reg-shift = <0x2>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <62>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart2: serial@406880 {
			compatible = "ns16550a";
			reg = <0x406880 0x20>;
			reg-io-width = <0x4>;
			reg-shift = <0x2>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <63>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		bsca: i2c@406200 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406200 0x58>;
		      interrupts = <24>;
		      interrupt-names = "upg_bsca";
		      status = "disabled";
		};

		bscb: i2c@406280 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406280 0x58>;
		      interrupts = <25>;
		      interrupt-names = "upg_bscb";
		      status = "disabled";
		};

		bscc: i2c@406300 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406300 0x58>;
		      interrupts = <26>;
		      interrupt-names = "upg_bscc";
		      status = "disabled";
		};

		bscd: i2c@408980 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_aon_irq0_intc>;
		      reg = <0x408980 0x58>;
		      interrupts = <27>;
		      interrupt-names = "upg_bscd";
		      status = "disabled";
		};

		pwma: pwm@406400 {
			compatible = "brcm,bcm7038-pwm";
			reg = <0x406400 0x28>;
			#pwm-cells = <2>;
			clocks = <&upg_clk>;
			status = "disabled";
		};

		aon_pm_l2_intc: interrupt-controller@408440 {
			compatible = "brcm,l2-intc";
			reg = <0x408440 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&periph_intc>;
			interrupts = <50>;
			brcm,irq-can-wake;
		};

		upg_gio: gpio@406500 {
			compatible = "brcm,brcmstb-gpio";
			reg = <0x406500 0xa0>;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupt-parent = <&upg_irq0_intc>;
			interrupts = <6>;
			brcm,gpio-bank-widths = <32 32 32 29 4>;
		};

		upg_gio_aon: gpio@408c00 {
			compatible = "brcm,brcmstb-gpio";
			reg = <0x408c00 0x60>;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupt-parent = <&upg_aon_irq0_intc>;
			interrupts = <6>;
			interrupts-extended = <&upg_aon_irq0_intc 6>,
					      <&aon_pm_l2_intc 5>;
			wakeup-source;
			brcm,gpio-bank-widths = <21 32 2>;
		};

		enet0: ethernet@430000 {
			phy-mode = "internal";
			phy-handle = <&phy1>;
			mac-address = [ 00 10 18 36 23 1a ];
			compatible = "brcm,genet-v2";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			reg = <0x430000 0x4c8c>;
			interrupts = <24>, <25>;
			interrupt-parent = <&periph_intc>;
			status = "disabled";

			mdio@e14 {
				compatible = "brcm,genet-mdio-v2";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0xe14 0x8>;

				phy1: ethernet-phy@1 {
					max-speed = <100>;
					reg = <0x1>;
					compatible = "brcm,40nm-ephy",
						"ethernet-phy-ieee802.3-c22";
				};
			};
		};

		ehci0: usb@480300 {
			compatible = "brcm,bcm7360-ehci", "generic-ehci";
			reg = <0x480300 0x100>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <65>;
			status = "disabled";
		};

		ohci0: usb@480400 {
			compatible = "brcm,bcm7360-ohci", "generic-ohci";
			reg = <0x480400 0x100>;
			native-endian;
			no-big-frame-no;
			interrupt-parent = <&periph_intc>;
			interrupts = <66>;
			status = "disabled";
		};

		hif_l2_intc: interrupt-controller@411000 {
			compatible = "brcm,l2-intc";
			reg = <0x411000 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&periph_intc>;
			interrupts = <30>;
		};

		nand: nand@412800 {
			compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
			#address-cells = <1>;
			#size-cells = <0>;
			reg-names = "nand";
			reg = <0x412800 0x400>;
			interrupt-parent = <&hif_l2_intc>;
			interrupts = <24>;
			status = "disabled";
		};

		sata: sata@181000 {
			compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
			reg-names = "ahci", "top-ctrl";
			reg = <0x181000 0xa9c>, <0x180020 0x1c>;
			interrupt-parent = <&periph_intc>;
			interrupts = <86>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sata0: sata-port@0 {
				reg = <0>;
				phys = <&sata_phy0>;
			};

			sata1: sata-port@1 {
				reg = <1>;
				phys = <&sata_phy1>;
			};
		};

		sata_phy: sata-phy@180100 {
			compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
			reg = <0x180100 0x0eff>;
			reg-names = "phy";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sata_phy0: sata-phy@0 {
				reg = <0>;
				#phy-cells = <0>;
			};

			sata_phy1: sata-phy@1 {
				reg = <1>;
				#phy-cells = <0>;
			};
		};

		sdhci0: sdhci@410000 {
			compatible = "brcm,bcm7425-sdhci";
			reg = <0x410000 0x100>;
			interrupt-parent = <&periph_intc>;
			interrupts = <82>;
			status = "disabled";
		};

		spi_l2_intc: interrupt-controller@411d00 {
			compatible = "brcm,l2-intc";
			reg = <0x411d00 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&periph_intc>;
			interrupts = <31>;
		};

		qspi: spi@413000 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "brcm,spi-bcm-qspi",
				     "brcm,spi-brcmstb-qspi";
			clocks = <&upg_clk>;
			reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
			reg-names = "cs_reg", "hif_mspi", "bspi";
			interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
			interrupt-parent = <&spi_l2_intc>;
			interrupt-names = "spi_lr_fullness_reached",
					  "spi_lr_session_aborted",
					  "spi_lr_impatient",
					  "spi_lr_session_done",
					  "spi_lr_overread",
					  "mspi_done",
					  "mspi_halted";
			status = "disabled";
		};

		mspi: spi@408a00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,spi-bcm-qspi",
				     "brcm,spi-brcmstb-mspi";
			clocks = <&upg_clk>;
			reg = <0x408a00 0x180>;
			reg-names = "mspi";
			interrupts = <0x14>;
			interrupt-parent = <&upg_aon_irq0_intc>;
			interrupt-names = "mspi_done";
			status = "disabled";
		};
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
8945e37e KC	2	/ {
	3	#address-cells = <1>;
	4	#size-cells = <1>;
	5	compatible = "brcm,bcm7360";
	6
	7	cpus {
	8	#address-cells = <1>;
	9	#size-cells = <0>;
	10
	11	mips-hpt-frequency = <375000000>;
	12
	13	cpu@0 {
	14	compatible = "brcm,bmips3300";
	15	device_type = "cpu";
	16	reg = <0>;
	17	};
	18	};
	19
	20	aliases {
	21	uart0 = &uart0;
	22	};
	23
a2c510a2	24	cpu_intc: interrupt-controller {
8945e37e KC	25	#address-cells = <0>;
	26	compatible = "mti,cpu-interrupt-controller";
	27
	28	interrupt-controller;
	29	#interrupt-cells = <1>;
	30	};
	31
	32	clocks {
	33	uart_clk: uart_clk {
	34	compatible = "fixed-clock";
	35	#clock-cells = <0>;
	36	clock-frequency = <81000000>;
	37	};
7bbe59dd JS	38
	39	upg_clk: upg_clk {
	40	compatible = "fixed-clock";
	41	#clock-cells = <0>;
	42	clock-frequency = <27000000>;
	43	};
8945e37e KC	44	};
	45
	46	rdb {
	47	#address-cells = <1>;
	48	#size-cells = <1>;
	49
	50	compatible = "simple-bus";
	51	ranges = <0 0x10000000 0x01000000>;
	52
a2c510a2	53	periph_intc: interrupt-controller@411400 {
8945e37e KC	54	compatible = "brcm,bcm7038-l1-intc";
	55	reg = <0x411400 0x30>;
	56
	57	interrupt-controller;
	58	#interrupt-cells = <1>;
	59
	60	interrupt-parent = <&cpu_intc>;
	61	interrupts = <2>;
	62	};
	63
a2c510a2	64	sun_l2_intc: interrupt-controller@403000 {
8945e37e KC	65	compatible = "brcm,l2-intc";
	66	reg = <0x403000 0x30>;
	67	interrupt-controller;
	68	#interrupt-cells = <1>;
	69	interrupt-parent = <&periph_intc>;
	70	interrupts = <48>;
	71	};
	72
	73	gisb-arb@400000 {
	74	compatible = "brcm,bcm7400-gisb-arb";
	75	reg = <0x400000 0xdc>;
	76	native-endian;
	77	interrupt-parent = <&sun_l2_intc>;
	78	interrupts = <0>, <2>;
	79	brcm,gisb-arb-master-mask = <0x2f3>;
	80	brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
	81	"rdc_0", "raaga_0",
	82	"avd_0", "jtag_0";
	83	};
	84
a2c510a2	85	upg_irq0_intc: interrupt-controller@406600 {
8945e37e KC	86	compatible = "brcm,bcm7120-l2-intc";
	87	reg = <0x406600 0x8>;
	88
fb575b85	89	brcm,int-map-mask = <0x44>, <0x7000000>;
8945e37e KC	90	brcm,int-fwd-mask = <0x70000>;
	91
	92	interrupt-controller;
	93	#interrupt-cells = <1>;
	94
	95	interrupt-parent = <&periph_intc>;
fb575b85 JS	96	interrupts = <56>, <54>;
	97	interrupt-names = "upg_main", "upg_bsc";
	98	};
	99
a2c510a2	100	upg_aon_irq0_intc: interrupt-controller@408b80 {
fb575b85 JS	101	compatible = "brcm,bcm7120-l2-intc";
	102	reg = <0x408b80 0x8>;
	103
	104	brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
	105	brcm,int-fwd-mask = <0>;
	106	brcm,irq-can-wake;
	107
	108	interrupt-controller;
	109	#interrupt-cells = <1>;
	110
	111	interrupt-parent = <&periph_intc>;
	112	interrupts = <57>, <55>, <59>;
	113	interrupt-names = "upg_main_aon", "upg_bsc_aon",
	114	"upg_spi";
8945e37e KC	115	};
	116
	117	sun_top_ctrl: syscon@404000 {
	118	compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
	119	reg = <0x404000 0x51c>;
25d6463e	120	native-endian;
8945e37e KC	121	};
	122
	123	reboot {
	124	compatible = "brcm,brcmstb-reboot";
	125	syscon = <&sun_top_ctrl 0x304 0x308>;
	126	};
	127
	128	uart0: serial@406800 {
	129	compatible = "ns16550a";
	130	reg = <0x406800 0x20>;
	131	reg-io-width = <0x4>;
	132	reg-shift = <0x2>;
	133	native-endian;
	134	interrupt-parent = <&periph_intc>;
	135	interrupts = <61>;
	136	clocks = <&uart_clk>;
	137	status = "disabled";
	138	};
	139
8bac078c JS	140	uart1: serial@406840 {
	141	compatible = "ns16550a";
	142	reg = <0x406840 0x20>;
	143	reg-io-width = <0x4>;
	144	reg-shift = <0x2>;
	145	native-endian;
	146	interrupt-parent = <&periph_intc>;
	147	interrupts = <62>;
	148	clocks = <&uart_clk>;
	149	status = "disabled";
	150	};
	151
	152	uart2: serial@406880 {
	153	compatible = "ns16550a";
	154	reg = <0x406880 0x20>;
	155	reg-io-width = <0x4>;
	156	reg-shift = <0x2>;
	157	native-endian;
	158	interrupt-parent = <&periph_intc>;
	159	interrupts = <63>;
	160	clocks = <&uart_clk>;
	161	status = "disabled";
	162	};
	163
fb575b85 JS	164	bsca: i2c@406200 {
	165	clock-frequency = <390000>;
	166	compatible = "brcm,brcmstb-i2c";
	167	interrupt-parent = <&upg_irq0_intc>;
	168	reg = <0x406200 0x58>;
	169	interrupts = <24>;
	170	interrupt-names = "upg_bsca";
	171	status = "disabled";
	172	};
	173
	174	bscb: i2c@406280 {
	175	clock-frequency = <390000>;
	176	compatible = "brcm,brcmstb-i2c";
	177	interrupt-parent = <&upg_irq0_intc>;
	178	reg = <0x406280 0x58>;
	179	interrupts = <25>;
	180	interrupt-names = "upg_bscb";
	181	status = "disabled";
	182	};
	183
	184	bscc: i2c@406300 {
	185	clock-frequency = <390000>;
	186	compatible = "brcm,brcmstb-i2c";
	187	interrupt-parent = <&upg_irq0_intc>;
	188	reg = <0x406300 0x58>;
	189	interrupts = <26>;
	190	interrupt-names = "upg_bscc";
	191	status = "disabled";
	192	};
	193
	194	bscd: i2c@408980 {
	195	clock-frequency = <390000>;
	196	compatible = "brcm,brcmstb-i2c";
	197	interrupt-parent = <&upg_aon_irq0_intc>;
	198	reg = <0x408980 0x58>;
	199	interrupts = <27>;
	200	interrupt-names = "upg_bscd";
	201	status = "disabled";
	202	};
	203
7bbe59dd JS	204	pwma: pwm@406400 {
	205	compatible = "brcm,bcm7038-pwm";
	206	reg = <0x406400 0x28>;
	207	#pwm-cells = <2>;
	208	clocks = <&upg_clk>;
	209	status = "disabled";
	210	};
	211
c707844d JS	212	aon_pm_l2_intc: interrupt-controller@408440 {
	213	compatible = "brcm,l2-intc";
	214	reg = <0x408440 0x30>;
	215	interrupt-controller;
	216	#interrupt-cells = <1>;
	217	interrupt-parent = <&periph_intc>;
	218	interrupts = <50>;
	219	brcm,irq-can-wake;
	220	};
	221
	222	upg_gio: gpio@406500 {
	223	compatible = "brcm,brcmstb-gpio";
	224	reg = <0x406500 0xa0>;
	225	#gpio-cells = <2>;
	226	#interrupt-cells = <2>;
	227	gpio-controller;
	228	interrupt-controller;
	229	interrupt-parent = <&upg_irq0_intc>;
	230	interrupts = <6>;
	231	brcm,gpio-bank-widths = <32 32 32 29 4>;
	232	};
	233
	234	upg_gio_aon: gpio@408c00 {
	235	compatible = "brcm,brcmstb-gpio";
	236	reg = <0x408c00 0x60>;
	237	#gpio-cells = <2>;
	238	#interrupt-cells = <2>;
	239	gpio-controller;
	240	interrupt-controller;
	241	interrupt-parent = <&upg_aon_irq0_intc>;
	242	interrupts = <6>;
	243	interrupts-extended = <&upg_aon_irq0_intc 6>,
	244	<&aon_pm_l2_intc 5>;
	245	wakeup-source;
	246	brcm,gpio-bank-widths = <21 32 2>;
	247	};
	248
8945e37e KC	249	enet0: ethernet@430000 {
	250	phy-mode = "internal";
	251	phy-handle = <&phy1>;
	252	mac-address = [ 00 10 18 36 23 1a ];
	253	compatible = "brcm,genet-v2";
	254	#address-cells = <0x1>;
	255	#size-cells = <0x1>;
	256	reg = <0x430000 0x4c8c>;
	257	interrupts = <24>, <25>;
	258	interrupt-parent = <&periph_intc>;
	259	status = "disabled";
	260
	261	mdio@e14 {
	262	compatible = "brcm,genet-mdio-v2";
	263	#address-cells = <0x1>;
	264	#size-cells = <0x0>;
	265	reg = <0xe14 0x8>;
	266
	267	phy1: ethernet-phy@1 {
	268	max-speed = <100>;
	269	reg = <0x1>;
	270	compatible = "brcm,40nm-ephy",
	271	"ethernet-phy-ieee802.3-c22";
	272	};
	273	};
	274	};
	275
	276	ehci0: usb@480300 {
	277	compatible = "brcm,bcm7360-ehci", "generic-ehci";
	278	reg = <0x480300 0x100>;
	279	native-endian;
	280	interrupt-parent = <&periph_intc>;
	281	interrupts = <65>;
	282	status = "disabled";
	283	};
	284
	285	ohci0: usb@480400 {
	286	compatible = "brcm,bcm7360-ohci", "generic-ohci";
	287	reg = <0x480400 0x100>;
	288	native-endian;
	289	no-big-frame-no;
	290	interrupt-parent = <&periph_intc>;
	291	interrupts = <66>;
	292	status = "disabled";
	293	};
5c40d493	294
cfc8be04 JS	295	hif_l2_intc: interrupt-controller@411000 {
	296	compatible = "brcm,l2-intc";
	297	reg = <0x411000 0x30>;
	298	interrupt-controller;
	299	#interrupt-cells = <1>;
	300	interrupt-parent = <&periph_intc>;
	301	interrupts = <30>;
	302	};
	303
	304	nand: nand@412800 {
	305	compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
	306	#address-cells = <1>;
	307	#size-cells = <0>;
	308	reg-names = "nand";
	309	reg = <0x412800 0x400>;
	310	interrupt-parent = <&hif_l2_intc>;
	311	interrupts = <24>;
	312	status = "disabled";
	313	};
	314
5c40d493 JS	315	sata: sata@181000 {
	316	compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
	317	reg-names = "ahci", "top-ctrl";
	318	reg = <0x181000 0xa9c>, <0x180020 0x1c>;
	319	interrupt-parent = <&periph_intc>;
	320	interrupts = <86>;
	321	#address-cells = <1>;
	322	#size-cells = <0>;
	323	status = "disabled";
	324
	325	sata0: sata-port@0 {
	326	reg = <0>;
	327	phys = <&sata_phy0>;
	328	};
	329
	330	sata1: sata-port@1 {
	331	reg = <1>;
	332	phys = <&sata_phy1>;
	333	};
	334	};
	335
	336	sata_phy: sata-phy@180100 {
	337	compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
	338	reg = <0x180100 0x0eff>;
	339	reg-names = "phy";
	340	#address-cells = <1>;
	341	#size-cells = <0>;
	342	status = "disabled";
	343
	344	sata_phy0: sata-phy@0 {
	345	reg = <0>;
	346	#phy-cells = <0>;
	347	};
	348
	349	sata_phy1: sata-phy@1 {
	350	reg = <1>;
	351	#phy-cells = <0>;
	352	};
	353	};
b2420e27 JS	354
	355	sdhci0: sdhci@410000 {
	356	compatible = "brcm,bcm7425-sdhci";
	357	reg = <0x410000 0x100>;
	358	interrupt-parent = <&periph_intc>;
	359	interrupts = <82>;
	360	status = "disabled";
	361	};
d783738c JS	362
	363	spi_l2_intc: interrupt-controller@411d00 {
	364	compatible = "brcm,l2-intc";
	365	reg = <0x411d00 0x30>;
	366	interrupt-controller;
	367	#interrupt-cells = <1>;
	368	interrupt-parent = <&periph_intc>;
	369	interrupts = <31>;
	370	};
	371
	372	qspi: spi@413000 {
	373	#address-cells = <0x1>;
	374	#size-cells = <0x0>;
	375	compatible = "brcm,spi-bcm-qspi",
	376	"brcm,spi-brcmstb-qspi";
	377	clocks = <&upg_clk>;
	378	reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
	379	reg-names = "cs_reg", "hif_mspi", "bspi";
	380	interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
	381	interrupt-parent = <&spi_l2_intc>;
	382	interrupt-names = "spi_lr_fullness_reached",
	383	"spi_lr_session_aborted",
	384	"spi_lr_impatient",
	385	"spi_lr_session_done",
	386	"spi_lr_overread",
	387	"mspi_done",
	388	"mspi_halted";
	389	status = "disabled";
	390	};
	391
	392	mspi: spi@408a00 {
	393	#address-cells = <1>;
	394	#size-cells = <0>;
	395	compatible = "brcm,spi-bcm-qspi",
	396	"brcm,spi-brcmstb-mspi";
	397	clocks = <&upg_clk>;
	398	reg = <0x408a00 0x180>;
	399	reg-names = "mspi";
	400	interrupts = <0x14>;
	401	interrupt-parent = <&upg_aon_irq0_intc>;
	402	interrupt-names = "mspi_done";
	403	status = "disabled";
	404	};
8945e37e KC	405	};
8945e37e KC	406	};