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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
73b4390f RB |
2 | /* |
3 | * Copyright 2002 Integrated Device Technology, Inc. | |
4 | * All rights reserved. | |
5 | * | |
6 | * DMA register definition. | |
7 | * | |
8 | * Author : ryan.holmQVist@idt.com | |
70342287 | 9 | * Date : 20011005 |
73b4390f RB |
10 | */ |
11 | ||
12 | #ifndef _ASM_RC32434_DMA_V_H_ | |
13 | #define _ASM_RC32434_DMA_V_H_ | |
14 | ||
15 | #include <asm/mach-rc32434/dma.h> | |
16 | #include <asm/mach-rc32434/rc32434.h> | |
17 | ||
18 | #define DMA_CHAN_OFFSET 0x14 | |
19 | #define IS_DMA_USED(X) (((X) & \ | |
20 | (DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \ | |
21 | != 0) | |
22 | #define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK) | |
23 | ||
24 | #define DMA_HALT_TIMEOUT 500 | |
25 | ||
26 | static inline int rc32434_halt_dma(struct dma_reg *ch) | |
27 | { | |
28 | int timeout = 1; | |
29 | if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) { | |
30 | __raw_writel(0, &ch->dmac); | |
31 | for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) { | |
32 | if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) { | |
33 | __raw_writel(0, &ch->dmas); | |
34 | break; | |
35 | } | |
36 | } | |
37 | } | |
38 | ||
39 | return timeout ? 0 : 1; | |
40 | } | |
41 | ||
42 | static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr) | |
43 | { | |
44 | __raw_writel(0, &ch->dmandptr); | |
45 | __raw_writel(dma_addr, &ch->dmadptr); | |
46 | } | |
47 | ||
48 | static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr) | |
49 | { | |
50 | __raw_writel(dma_addr, &ch->dmandptr); | |
51 | } | |
52 | ||
70342287 | 53 | #endif /* _ASM_RC32434_DMA_V_H_ */ |