[mirror_ubuntu-disco-kernel.git] / arch / mips / kernel / mips-mt.c

// SPDX-License-Identifier: GPL-2.0
/*
 * General MIPS MT support routines, usable in AP/SP and SMVP.
 * Copyright (C) 2005 Mips Technologies, Inc
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/security.h>

#include <asm/cpu.h>
#include <asm/processor.h>
#include <linux/atomic.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/mipsmtregs.h>
#include <asm/r4kcache.h>
#include <asm/cacheflush.h>

int vpelimit;

static int __init maxvpes(char *str)
{
	get_option(&str, &vpelimit);

	return 1;
}

__setup("maxvpes=", maxvpes);

int tclimit;

static int __init maxtcs(char *str)
{
	get_option(&str, &tclimit);

	return 1;
}

__setup("maxtcs=", maxtcs);

/*
 * Dump new MIPS MT state for the core. Does not leave TCs halted.
 * Takes an argument which taken to be a pre-call MVPControl value.
 */

void mips_mt_regdump(unsigned long mvpctl)
{
	unsigned long flags;
	unsigned long vpflags;
	unsigned long mvpconf0;
	int nvpe;
	int ntc;
	int i;
	int tc;
	unsigned long haltval;
	unsigned long tcstatval;

	local_irq_save(flags);
	vpflags = dvpe();
	printk("=== MIPS MT State Dump ===\n");
	printk("-- Global State --\n");
	printk("   MVPControl Passed: %08lx\n", mvpctl);
	printk("   MVPControl Read: %08lx\n", vpflags);
	printk("   MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
	ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
	printk("-- per-VPE State --\n");
	for (i = 0; i < nvpe; i++) {
		for (tc = 0; tc < ntc; tc++) {
			settc(tc);
			if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
				printk("  VPE %d\n", i);
				printk("   VPEControl : %08lx\n",
				       read_vpe_c0_vpecontrol());
				printk("   VPEConf0 : %08lx\n",
				       read_vpe_c0_vpeconf0());
				printk("   VPE%d.Status : %08lx\n",
				       i, read_vpe_c0_status());
				printk("   VPE%d.EPC : %08lx %pS\n",
				       i, read_vpe_c0_epc(),
				       (void *) read_vpe_c0_epc());
				printk("   VPE%d.Cause : %08lx\n",
				       i, read_vpe_c0_cause());
				printk("   VPE%d.Config7 : %08lx\n",
				       i, read_vpe_c0_config7());
				break; /* Next VPE */
			}
		}
	}
	printk("-- per-TC State --\n");
	for (tc = 0; tc < ntc; tc++) {
		settc(tc);
		if (read_tc_c0_tcbind() == read_c0_tcbind()) {
			/* Are we dumping ourself?  */
			haltval = 0; /* Then we're not halted, and mustn't be */
			tcstatval = flags; /* And pre-dump TCStatus is flags */
			printk("  TC %d (current TC with VPE EPC above)\n", tc);
		} else {
			haltval = read_tc_c0_tchalt();
			write_tc_c0_tchalt(1);
			tcstatval = read_tc_c0_tcstatus();
			printk("  TC %d\n", tc);
		}
		printk("   TCStatus : %08lx\n", tcstatval);
		printk("   TCBind : %08lx\n", read_tc_c0_tcbind());
		printk("   TCRestart : %08lx %pS\n",
		       read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
		printk("   TCHalt : %08lx\n", haltval);
		printk("   TCContext : %08lx\n", read_tc_c0_tccontext());
		if (!haltval)
			write_tc_c0_tchalt(0);
	}
	printk("===========================\n");
	evpe(vpflags);
	local_irq_restore(flags);
}

static int mt_opt_norps;
static int mt_opt_rpsctl = -1;
static int mt_opt_nblsu = -1;
static int mt_opt_forceconfig7;
static int mt_opt_config7 = -1;

static int __init rps_disable(char *s)
{
	mt_opt_norps = 1;
	return 1;
}
__setup("norps", rps_disable);

static int __init rpsctl_set(char *str)
{
	get_option(&str, &mt_opt_rpsctl);
	return 1;
}
__setup("rpsctl=", rpsctl_set);

static int __init nblsu_set(char *str)
{
	get_option(&str, &mt_opt_nblsu);
	return 1;
}
__setup("nblsu=", nblsu_set);

static int __init config7_set(char *str)
{
	get_option(&str, &mt_opt_config7);
	mt_opt_forceconfig7 = 1;
	return 1;
}
__setup("config7=", config7_set);

/* Experimental cache flush control parameters that should go away some day */
int mt_protiflush;
int mt_protdflush;
int mt_n_iflushes = 1;
int mt_n_dflushes = 1;

static int __init set_protiflush(char *s)
{
	mt_protiflush = 1;
	return 1;
}
__setup("protiflush", set_protiflush);

static int __init set_protdflush(char *s)
{
	mt_protdflush = 1;
	return 1;
}
__setup("protdflush", set_protdflush);

static int __init niflush(char *s)
{
	get_option(&s, &mt_n_iflushes);
	return 1;
}
__setup("niflush=", niflush);

static int __init ndflush(char *s)
{
	get_option(&s, &mt_n_dflushes);
	return 1;
}
__setup("ndflush=", ndflush);

static unsigned int itc_base;

static int __init set_itc_base(char *str)
{
	get_option(&str, &itc_base);
	return 1;
}

__setup("itcbase=", set_itc_base);

void mips_mt_set_cpuoptions(void)
{
	unsigned int oconfig7 = read_c0_config7();
	unsigned int nconfig7 = oconfig7;

	if (mt_opt_norps) {
		printk("\"norps\" option deprecated: use \"rpsctl=\"\n");
	}
	if (mt_opt_rpsctl >= 0) {
		printk("34K return prediction stack override set to %d.\n",
			mt_opt_rpsctl);
		if (mt_opt_rpsctl)
			nconfig7 |= (1 << 2);
		else
			nconfig7 &= ~(1 << 2);
	}
	if (mt_opt_nblsu >= 0) {
		printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
		if (mt_opt_nblsu)
			nconfig7 |= (1 << 5);
		else
			nconfig7 &= ~(1 << 5);
	}
	if (mt_opt_forceconfig7) {
		printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
		nconfig7 = mt_opt_config7;
	}
	if (oconfig7 != nconfig7) {
		__asm__ __volatile("sync");
		write_c0_config7(nconfig7);
		ehb();
		printk("Config7: 0x%08x\n", read_c0_config7());
	}

	/* Report Cache management debug options */
	if (mt_protiflush)
		printk("I-cache flushes single-threaded\n");
	if (mt_protdflush)
		printk("D-cache flushes single-threaded\n");
	if (mt_n_iflushes != 1)
		printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
	if (mt_n_dflushes != 1)
		printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);

	if (itc_base != 0) {
		/*
		 * Configure ITC mapping.  This code is very
		 * specific to the 34K core family, which uses
		 * a special mode bit ("ITC") in the ErrCtl
		 * register to enable access to ITC control
		 * registers via cache "tag" operations.
		 */
		unsigned long ectlval;
		unsigned long itcblkgrn;

		/* ErrCtl register is known as "ecc" to Linux */
		ectlval = read_c0_ecc();
		write_c0_ecc(ectlval | (0x1 << 26));
		ehb();
#define INDEX_0 (0x80000000)
#define INDEX_8 (0x80000008)
		/* Read "cache tag" for Dcache pseudo-index 8 */
		cache_op(Index_Load_Tag_D, INDEX_8);
		ehb();
		itcblkgrn = read_c0_dtaglo();
		itcblkgrn &= 0xfffe0000;
		/* Set for 128 byte pitch of ITC cells */
		itcblkgrn |= 0x00000c00;
		/* Stage in Tag register */
		write_c0_dtaglo(itcblkgrn);
		ehb();
		/* Write out to ITU with CACHE op */
		cache_op(Index_Store_Tag_D, INDEX_8);
		/* Now set base address, and turn ITC on with 0x1 bit */
		write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
		ehb();
		/* Write out to ITU with CACHE op */
		cache_op(Index_Store_Tag_D, INDEX_0);
		write_c0_ecc(ectlval);
		ehb();
		printk("Mapped %ld ITC cells starting at 0x%08x\n",
			((itcblkgrn & 0x7fe00000) >> 20), itc_base);
	}
}

/*
 * Function to protect cache flushes from concurrent execution
 * depends on MP software model chosen.
 */

void mt_cflush_lockdown(void)
{
	/* FILL IN VSMP and AP/SP VERSIONS HERE */
}

void mt_cflush_release(void)
{
	/* FILL IN VSMP and AP/SP VERSIONS HERE */
}

struct class *mt_class;

static int __init mt_init(void)
{
	struct class *mtc;

	mtc = class_create(THIS_MODULE, "mt");
	if (IS_ERR(mtc))
		return PTR_ERR(mtc);

	mt_class = mtc;

	return 0;
}

subsys_initcall(mt_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
41c594ab	2	/*
b633648c	3	* General MIPS MT support routines, usable in AP/SP and SMVP.
41c594ab RB	4	* Copyright (C) 2005 Mips Technologies, Inc
	5	*/
	6
27a3bbaf	7	#include <linux/device.h>
41c594ab RB	8	#include <linux/kernel.h>
41c594ab RB	9	#include <linux/sched.h>
73bc256d	10	#include <linux/export.h>
41c594ab	11	#include <linux/interrupt.h>
f72af3cf	12	#include <linux/security.h>
41c594ab RB	13
	14	#include <asm/cpu.h>
	15	#include <asm/processor.h>
60063497	16	#include <linux/atomic.h>
41c594ab RB	17	#include <asm/hardirq.h>
41c594ab RB	18	#include <asm/mmu_context.h>
41c594ab RB	19	#include <asm/mipsmtregs.h>
	20	#include <asm/r4kcache.h>
	21	#include <asm/cacheflush.h>
	22
07cc0c9e RB	23	int vpelimit;
	24
	25	static int __init maxvpes(char *str)
	26	{
	27	get_option(&str, &vpelimit);
	28
	29	return 1;
	30	}
	31
	32	__setup("maxvpes=", maxvpes);
	33
	34	int tclimit;
	35
	36	static int __init maxtcs(char *str)
	37	{
	38	get_option(&str, &tclimit);
	39
	40	return 1;
	41	}
	42
	43	__setup("maxtcs=", maxtcs);
	44
41c594ab RB	45	/*
	46	* Dump new MIPS MT state for the core. Does not leave TCs halted.
	47	* Takes an argument which taken to be a pre-call MVPControl value.
	48	*/
	49
	50	void mips_mt_regdump(unsigned long mvpctl)
	51	{
	52	unsigned long flags;
	53	unsigned long vpflags;
	54	unsigned long mvpconf0;
	55	int nvpe;
	56	int ntc;
	57	int i;
	58	int tc;
	59	unsigned long haltval;
	60	unsigned long tcstatval;
41c594ab RB	61
	62	local_irq_save(flags);
	63	vpflags = dvpe();
	64	printk("=== MIPS MT State Dump ===\n");
	65	printk("-- Global State --\n");
	66	printk(" MVPControl Passed: %08lx\n", mvpctl);
	67	printk(" MVPControl Read: %08lx\n", vpflags);
	68	printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
	69	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
	70	ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
	71	printk("-- per-VPE State --\n");
d223a861 RB	72	for (i = 0; i < nvpe; i++) {
d223a861 RB	73	for (tc = 0; tc < ntc; tc++) {
41c594ab	74	settc(tc);
d223a861 RB	75	if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
	76	printk(" VPE %d\n", i);
	77	printk(" VPEControl : %08lx\n",
	78	read_vpe_c0_vpecontrol());
	79	printk(" VPEConf0 : %08lx\n",
	80	read_vpe_c0_vpeconf0());
	81	printk(" VPE%d.Status : %08lx\n",
	82	i, read_vpe_c0_status());
b012cffe RB	83	printk(" VPE%d.EPC : %08lx %pS\n",
	84	i, read_vpe_c0_epc(),
	85	(void *) read_vpe_c0_epc());
d223a861 RB	86	printk(" VPE%d.Cause : %08lx\n",
	87	i, read_vpe_c0_cause());
	88	printk(" VPE%d.Config7 : %08lx\n",
	89	i, read_vpe_c0_config7());
	90	break; /* Next VPE */
	91	}
41c594ab	92	}
41c594ab RB	93	}
41c594ab RB	94	printk("-- per-TC State --\n");
d223a861	95	for (tc = 0; tc < ntc; tc++) {
41c594ab	96	settc(tc);
d223a861	97	if (read_tc_c0_tcbind() == read_c0_tcbind()) {
41c594ab RB	98	/* Are we dumping ourself? */
	99	haltval = 0; /* Then we're not halted, and mustn't be */
	100	tcstatval = flags; /* And pre-dump TCStatus is flags */
	101	printk(" TC %d (current TC with VPE EPC above)\n", tc);
	102	} else {
	103	haltval = read_tc_c0_tchalt();
	104	write_tc_c0_tchalt(1);
	105	tcstatval = read_tc_c0_tcstatus();
	106	printk(" TC %d\n", tc);
	107	}
	108	printk(" TCStatus : %08lx\n", tcstatval);
	109	printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
b012cffe RB	110	printk(" TCRestart : %08lx %pS\n",
b012cffe RB	111	read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
41c594ab RB	112	printk(" TCHalt : %08lx\n", haltval);
	113	printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
	114	if (!haltval)
	115	write_tc_c0_tchalt(0);
	116	}
41c594ab RB	117	printk("===========================\n");
	118	evpe(vpflags);
	119	local_irq_restore(flags);
	120	}
	121
982f6ffe	122	static int mt_opt_norps;
41c594ab RB	123	static int mt_opt_rpsctl = -1;
41c594ab RB	124	static int mt_opt_nblsu = -1;
982f6ffe	125	static int mt_opt_forceconfig7;
41c594ab RB	126	static int mt_opt_config7 = -1;
	127
	128	static int __init rps_disable(char *s)
	129	{
	130	mt_opt_norps = 1;
	131	return 1;
	132	}
	133	__setup("norps", rps_disable);
	134
	135	static int __init rpsctl_set(char *str)
	136	{
	137	get_option(&str, &mt_opt_rpsctl);
	138	return 1;
	139	}
	140	__setup("rpsctl=", rpsctl_set);
	141
	142	static int __init nblsu_set(char *str)
	143	{
	144	get_option(&str, &mt_opt_nblsu);
	145	return 1;
	146	}
	147	__setup("nblsu=", nblsu_set);
	148
	149	static int __init config7_set(char *str)
	150	{
	151	get_option(&str, &mt_opt_config7);
	152	mt_opt_forceconfig7 = 1;
	153	return 1;
	154	}
	155	__setup("config7=", config7_set);
	156
	157	/* Experimental cache flush control parameters that should go away some day */
982f6ffe RB	158	int mt_protiflush;
982f6ffe RB	159	int mt_protdflush;
41c594ab RB	160	int mt_n_iflushes = 1;
	161	int mt_n_dflushes = 1;
	162
	163	static int __init set_protiflush(char *s)
	164	{
	165	mt_protiflush = 1;
	166	return 1;
	167	}
	168	__setup("protiflush", set_protiflush);
	169
	170	static int __init set_protdflush(char *s)
	171	{
	172	mt_protdflush = 1;
	173	return 1;
	174	}
	175	__setup("protdflush", set_protdflush);
	176
	177	static int __init niflush(char *s)
	178	{
	179	get_option(&s, &mt_n_iflushes);
	180	return 1;
	181	}
	182	__setup("niflush=", niflush);
	183
	184	static int __init ndflush(char *s)
	185	{
	186	get_option(&s, &mt_n_dflushes);
	187	return 1;
	188	}
	189	__setup("ndflush=", ndflush);
41c594ab	190
982f6ffe	191	static unsigned int itc_base;
41c594ab RB	192
	193	static int __init set_itc_base(char *str)
	194	{
	195	get_option(&str, &itc_base);
	196	return 1;
	197	}
	198
	199	__setup("itcbase=", set_itc_base);
	200
	201	void mips_mt_set_cpuoptions(void)
	202	{
	203	unsigned int oconfig7 = read_c0_config7();
	204	unsigned int nconfig7 = oconfig7;
	205
	206	if (mt_opt_norps) {
6997991a	207	printk("\"norps\" option deprecated: use \"rpsctl=\"\n");
41c594ab RB	208	}
	209	if (mt_opt_rpsctl >= 0) {
	210	printk("34K return prediction stack override set to %d.\n",
	211	mt_opt_rpsctl);
	212	if (mt_opt_rpsctl)
	213	nconfig7 \|= (1 << 2);
	214	else
	215	nconfig7 &= ~(1 << 2);
	216	}
	217	if (mt_opt_nblsu >= 0) {
	218	printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
	219	if (mt_opt_nblsu)
	220	nconfig7 \|= (1 << 5);
	221	else
	222	nconfig7 &= ~(1 << 5);
	223	}
	224	if (mt_opt_forceconfig7) {
	225	printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
	226	nconfig7 = mt_opt_config7;
	227	}
	228	if (oconfig7 != nconfig7) {
	229	__asm__ __volatile("sync");
	230	write_c0_config7(nconfig7);
49a89efb	231	ehb();
41c594ab RB	232	printk("Config7: 0x%08x\n", read_c0_config7());
	233	}
	234
	235	/* Report Cache management debug options */
	236	if (mt_protiflush)
	237	printk("I-cache flushes single-threaded\n");
	238	if (mt_protdflush)
	239	printk("D-cache flushes single-threaded\n");
	240	if (mt_n_iflushes != 1)
	241	printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
	242	if (mt_n_dflushes != 1)
	243	printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
	244
41c594ab RB	245	if (itc_base != 0) {
	246	/*
	247	* Configure ITC mapping. This code is very
	248	* specific to the 34K core family, which uses
	249	* a special mode bit ("ITC") in the ErrCtl
	250	* register to enable access to ITC control
	251	* registers via cache "tag" operations.
	252	*/
	253	unsigned long ectlval;
	254	unsigned long itcblkgrn;
	255
	256	/* ErrCtl register is known as "ecc" to Linux */
	257	ectlval = read_c0_ecc();
	258	write_c0_ecc(ectlval \| (0x1 << 26));
	259	ehb();
	260	#define INDEX_0 (0x80000000)
	261	#define INDEX_8 (0x80000008)
	262	/* Read "cache tag" for Dcache pseudo-index 8 */
	263	cache_op(Index_Load_Tag_D, INDEX_8);
	264	ehb();
	265	itcblkgrn = read_c0_dtaglo();
	266	itcblkgrn &= 0xfffe0000;
	267	/* Set for 128 byte pitch of ITC cells */
	268	itcblkgrn \|= 0x00000c00;
	269	/* Stage in Tag register */
	270	write_c0_dtaglo(itcblkgrn);
	271	ehb();
	272	/* Write out to ITU with CACHE op */
	273	cache_op(Index_Store_Tag_D, INDEX_8);
	274	/* Now set base address, and turn ITC on with 0x1 bit */
	275	write_c0_dtaglo((itc_base & 0xfffffc00) \| 0x1 );
	276	ehb();
	277	/* Write out to ITU with CACHE op */
	278	cache_op(Index_Store_Tag_D, INDEX_0);
	279	write_c0_ecc(ectlval);
	280	ehb();
	281	printk("Mapped %ld ITC cells starting at 0x%08x\n",
	282	((itcblkgrn & 0x7fe00000) >> 20), itc_base);
	283	}
	284	}
	285
	286	/*
	287	* Function to protect cache flushes from concurrent execution
	288	* depends on MP software model chosen.
	289	*/
	290
	291	void mt_cflush_lockdown(void)
	292	{
41c594ab RB	293	/* FILL IN VSMP and AP/SP VERSIONS HERE */
	294	}
	295
	296	void mt_cflush_release(void)
	297	{
41c594ab RB	298	/* FILL IN VSMP and AP/SP VERSIONS HERE */
41c594ab RB	299	}
27a3bbaf RB	300
	301	struct class *mt_class;
	302
	303	static int __init mt_init(void)
	304	{
	305	struct class *mtc;
	306
	307	mtc = class_create(THIS_MODULE, "mt");
	308	if (IS_ERR(mtc))
	309	return PTR_ERR(mtc);
	310
	311	mt_class = mtc;
	312
	313	return 0;
	314	}
	315
	316	subsys_initcall(mt_init);