[mirror_ubuntu-disco-kernel.git] / arch / powerpc / include / asm / book3s / 64 / tlbflush-hash.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H
#define _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H

/*
 * TLB flushing for 64-bit hash-MMU CPUs
 */

#include <linux/percpu.h>
#include <asm/page.h>

#define PPC64_TLB_BATCH_NR 192

struct ppc64_tlb_batch {
	int			active;
	unsigned long		index;
	struct mm_struct	*mm;
	real_pte_t		pte[PPC64_TLB_BATCH_NR];
	unsigned long		vpn[PPC64_TLB_BATCH_NR];
	unsigned int		psize;
	int			ssize;
};
DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);

extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);

#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE

static inline void arch_enter_lazy_mmu_mode(void)
{
	struct ppc64_tlb_batch *batch;

	if (radix_enabled())
		return;
	batch = this_cpu_ptr(&ppc64_tlb_batch);
	batch->active = 1;
}

static inline void arch_leave_lazy_mmu_mode(void)
{
	struct ppc64_tlb_batch *batch;

	if (radix_enabled())
		return;
	batch = this_cpu_ptr(&ppc64_tlb_batch);

	if (batch->index)
		__flush_tlb_pending(batch);
	batch->active = 0;
}

#define arch_flush_lazy_mmu_mode()      do {} while (0)


extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize,
			    int ssize, unsigned long flags);
extern void flush_hash_range(unsigned long number, int local);
extern void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
				pmd_t *pmdp, unsigned int psize, int ssize,
				unsigned long flags);
static inline void hash__local_flush_tlb_mm(struct mm_struct *mm)
{
}

static inline void hash__flush_tlb_mm(struct mm_struct *mm)
{
}

static inline void hash__local_flush_tlb_page(struct vm_area_struct *vma,
					  unsigned long vmaddr)
{
}

static inline void hash__flush_tlb_page(struct vm_area_struct *vma,
				    unsigned long vmaddr)
{
}

static inline void hash__flush_tlb_range(struct vm_area_struct *vma,
				     unsigned long start, unsigned long end)
{
}

static inline void hash__flush_tlb_kernel_range(unsigned long start,
					    unsigned long end)
{
}


struct mmu_gather;
extern void hash__tlb_flush(struct mmu_gather *tlb);
/* Private function for use by PCI IO mapping code */
extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
				     unsigned long end);
extern void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd,
				unsigned long addr);
#endif /*  _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
ee3b93eb AK	2	#ifndef _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H
	3	#define _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H
	4
ee3b93eb AK	5	/*
	6	* TLB flushing for 64-bit hash-MMU CPUs
	7	*/
	8
	9	#include <linux/percpu.h>
	10	#include <asm/page.h>
	11
	12	#define PPC64_TLB_BATCH_NR 192
	13
	14	struct ppc64_tlb_batch {
	15	int active;
	16	unsigned long index;
	17	struct mm_struct *mm;
	18	real_pte_t pte[PPC64_TLB_BATCH_NR];
	19	unsigned long vpn[PPC64_TLB_BATCH_NR];
	20	unsigned int psize;
	21	int ssize;
	22	};
	23	DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
	24
	25	extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
	26
	27	#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
	28
	29	static inline void arch_enter_lazy_mmu_mode(void)
	30	{
1a472c9d	31	struct ppc64_tlb_batch *batch;
ee3b93eb	32
1a472c9d AK	33	if (radix_enabled())
	34	return;
	35	batch = this_cpu_ptr(&ppc64_tlb_batch);
ee3b93eb AK	36	batch->active = 1;
	37	}
	38
	39	static inline void arch_leave_lazy_mmu_mode(void)
	40	{
1a472c9d AK	41	struct ppc64_tlb_batch *batch;
	42
	43	if (radix_enabled())
	44	return;
	45	batch = this_cpu_ptr(&ppc64_tlb_batch);
ee3b93eb AK	46
	47	if (batch->index)
	48	__flush_tlb_pending(batch);
	49	batch->active = 0;
	50	}
	51
	52	#define arch_flush_lazy_mmu_mode() do {} while (0)
	53
	54
	55	extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize,
	56	int ssize, unsigned long flags);
	57	extern void flush_hash_range(unsigned long number, int local);
	58	extern void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
	59	pmd_t *pmdp, unsigned int psize, int ssize,
	60	unsigned long flags);
676012a6	61	static inline void hash__local_flush_tlb_mm(struct mm_struct *mm)
ee3b93eb AK	62	{
	63	}
	64
676012a6	65	static inline void hash__flush_tlb_mm(struct mm_struct *mm)
ee3b93eb AK	66	{
	67	}
	68
676012a6 AK	69	static inline void hash__local_flush_tlb_page(struct vm_area_struct *vma,
676012a6 AK	70	unsigned long vmaddr)
ee3b93eb AK	71	{
	72	}
	73
676012a6 AK	74	static inline void hash__flush_tlb_page(struct vm_area_struct *vma,
676012a6 AK	75	unsigned long vmaddr)
ee3b93eb AK	76	{
	77	}
	78
676012a6 AK	79	static inline void hash__flush_tlb_range(struct vm_area_struct *vma,
676012a6 AK	80	unsigned long start, unsigned long end)
ee3b93eb AK	81	{
	82	}
	83
676012a6 AK	84	static inline void hash__flush_tlb_kernel_range(unsigned long start,
676012a6 AK	85	unsigned long end)
ee3b93eb AK	86	{
	87	}
	88
676012a6 AK	89
	90	struct mmu_gather;
	91	extern void hash__tlb_flush(struct mmu_gather *tlb);
ee3b93eb AK	92	/* Private function for use by PCI IO mapping code */
	93	extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
	94	unsigned long end);
	95	extern void flush_tlb_pmd_range(struct mm_struct mm, pmd_t pmd,
	96	unsigned long addr);
	97	#endif /* _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H */