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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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2 | #ifndef _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H |
3 | #define _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H | |
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4 | #ifdef __KERNEL__ |
5 | ||
6 | /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based | |
7 | * processors | |
8 | * | |
9 | MMU Assist Register 3: | |
10 | ||
11 | 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63 | |
12 | RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR | |
13 | ||
14 | - PRESENT *must* be in the bottom three bits because swap cache | |
15 | entries use the top 29 bits. | |
16 | ||
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17 | */ |
18 | ||
19 | /* Definitions for FSL Book-E Cores */ | |
20 | #define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */ | |
21 | #define _PAGE_USER 0x00002 /* S: User page (maps to UR) */ | |
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22 | #define _PAGE_RW 0x00004 /* S: Write permission (SW) */ |
23 | #define _PAGE_DIRTY 0x00008 /* S: Page dirty */ | |
ea3cc330 | 24 | #define _PAGE_EXEC 0x00010 /* H: SX permission */ |
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25 | #define _PAGE_ACCESSED 0x00020 /* S: Page referenced */ |
26 | ||
27 | #define _PAGE_ENDIAN 0x00040 /* H: E bit */ | |
28 | #define _PAGE_GUARDED 0x00080 /* H: G bit */ | |
29 | #define _PAGE_COHERENT 0x00100 /* H: M bit */ | |
30 | #define _PAGE_NO_CACHE 0x00200 /* H: I bit */ | |
31 | #define _PAGE_WRITETHRU 0x00400 /* H: W bit */ | |
32 | #define _PAGE_SPECIAL 0x00800 /* S: Special page */ | |
33 | ||
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34 | #define _PMD_PRESENT 0 |
35 | #define _PMD_PRESENT_MASK (PAGE_MASK) | |
36 | #define _PMD_BAD (~PAGE_MASK) | |
37 | ||
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38 | #define PTE_WIMGE_SHIFT (6) |
39 | ||
c605782b | 40 | #endif /* __KERNEL__ */ |
17ed9e31 | 41 | #endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H */ |