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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
98ae22e1 MN |
2 | /* |
3 | * Transactional memory support routines to reclaim and recheckpoint | |
4 | * transactional process state. | |
5 | * | |
6 | * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation. | |
7 | */ | |
8 | ||
9 | #include <asm/asm-offsets.h> | |
10 | #include <asm/ppc_asm.h> | |
11 | #include <asm/ppc-opcode.h> | |
12 | #include <asm/ptrace.h> | |
13 | #include <asm/reg.h> | |
7f06f21d | 14 | #include <asm/bug.h> |
98ae22e1 MN |
15 | |
16 | #ifdef CONFIG_VSX | |
de79f7b9 PM |
17 | /* See fpu.S, this is borrowed from there */ |
18 | #define __SAVE_32FPRS_VSRS(n,c,base) \ | |
98ae22e1 MN |
19 | BEGIN_FTR_SECTION \ |
20 | b 2f; \ | |
21 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ | |
de79f7b9 | 22 | SAVE_32FPRS(n,base); \ |
98ae22e1 | 23 | b 3f; \ |
de79f7b9 | 24 | 2: SAVE_32VSRS(n,c,base); \ |
98ae22e1 | 25 | 3: |
98ae22e1 MN |
26 | #define __REST_32FPRS_VSRS(n,c,base) \ |
27 | BEGIN_FTR_SECTION \ | |
28 | b 2f; \ | |
29 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ | |
30 | REST_32FPRS(n,base); \ | |
31 | b 3f; \ | |
32 | 2: REST_32VSRS(n,c,base); \ | |
33 | 3: | |
34 | #else | |
de79f7b9 PM |
35 | #define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base) |
36 | #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base) | |
98ae22e1 | 37 | #endif |
de79f7b9 PM |
38 | #define SAVE_32FPRS_VSRS(n,c,base) \ |
39 | __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base) | |
98ae22e1 MN |
40 | #define REST_32FPRS_VSRS(n,c,base) \ |
41 | __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base) | |
42 | ||
43 | /* Stack frame offsets for local variables. */ | |
44 | #define TM_FRAME_L0 TM_FRAME_SIZE-16 | |
45 | #define TM_FRAME_L1 TM_FRAME_SIZE-8 | |
98ae22e1 MN |
46 | |
47 | ||
48 | /* In order to access the TM SPRs, TM must be enabled. So, do so: */ | |
49 | _GLOBAL(tm_enable) | |
50 | mfmsr r4 | |
51 | li r3, MSR_TM >> 32 | |
52 | sldi r3, r3, 32 | |
53 | and. r0, r4, r3 | |
54 | bne 1f | |
55 | or r4, r4, r3 | |
56 | mtmsrd r4 | |
57 | 1: blr | |
58 | ||
59 | _GLOBAL(tm_save_sprs) | |
60 | mfspr r0, SPRN_TFHAR | |
61 | std r0, THREAD_TM_TFHAR(r3) | |
62 | mfspr r0, SPRN_TEXASR | |
63 | std r0, THREAD_TM_TEXASR(r3) | |
64 | mfspr r0, SPRN_TFIAR | |
65 | std r0, THREAD_TM_TFIAR(r3) | |
66 | blr | |
67 | ||
68 | _GLOBAL(tm_restore_sprs) | |
69 | ld r0, THREAD_TM_TFHAR(r3) | |
70 | mtspr SPRN_TFHAR, r0 | |
71 | ld r0, THREAD_TM_TEXASR(r3) | |
72 | mtspr SPRN_TEXASR, r0 | |
73 | ld r0, THREAD_TM_TFIAR(r3) | |
74 | mtspr SPRN_TFIAR, r0 | |
75 | blr | |
76 | ||
77 | /* Passed an 8-bit failure cause as first argument. */ | |
78 | _GLOBAL(tm_abort) | |
79 | TABORT(R3) | |
80 | blr | |
81 | ||
98ae22e1 MN |
82 | /* void tm_reclaim(struct thread_struct *thread, |
83 | * unsigned long orig_msr, | |
84 | * uint8_t cause) | |
85 | * | |
86 | * - Performs a full reclaim. This destroys outstanding | |
87 | * transactions and updates thread->regs.tm_ckpt_* with the | |
88 | * original checkpointed state. Note that thread->regs is | |
89 | * unchanged. | |
90 | * - FP regs are written back to thread->transact_fpr before | |
91 | * reclaiming. These are the transactional (current) versions. | |
92 | * | |
93 | * Purpose is to both abort transactions of, and preserve the state of, | |
94 | * a transactions at a context switch. We preserve/restore both sets of process | |
95 | * state to restore them when the thread's scheduled again. We continue in | |
96 | * userland as though nothing happened, but when the transaction is resumed | |
97 | * they will abort back to the checkpointed state we save out here. | |
98 | * | |
99 | * Call with IRQs off, stacks get all out of sync for some periods in here! | |
100 | */ | |
101 | _GLOBAL(tm_reclaim) | |
102 | mfcr r6 | |
103 | mflr r0 | |
bbe30b3b | 104 | stw r6, 8(r1) |
98ae22e1 | 105 | std r0, 16(r1) |
6403105b | 106 | std r2, STK_GOT(r1) |
98ae22e1 MN |
107 | stdu r1, -TM_FRAME_SIZE(r1) |
108 | ||
109 | /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */ | |
110 | ||
c2e31bdc | 111 | std r3, STK_PARAM(R3)(r1) |
dc310669 | 112 | std r4, STK_PARAM(R4)(r1) |
98ae22e1 MN |
113 | SAVE_NVGPRS(r1) |
114 | ||
190ce869 | 115 | /* We need to setup MSR for VSX register save instructions. */ |
98ae22e1 MN |
116 | mfmsr r14 |
117 | mr r15, r14 | |
118 | ori r15, r15, MSR_FP | |
190ce869 | 119 | li r16, 0 |
c69e63b0 | 120 | ori r16, r16, MSR_EE /* IRQs hard off */ |
090b9284 | 121 | andc r15, r15, r16 |
98ae22e1 MN |
122 | oris r15, r15, MSR_VEC@h |
123 | #ifdef CONFIG_VSX | |
124 | BEGIN_FTR_SECTION | |
125 | oris r15,r15, MSR_VSX@h | |
126 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
127 | #endif | |
128 | mtmsrd r15 | |
129 | std r14, TM_FRAME_L0(r1) | |
130 | ||
7f06f21d MN |
131 | /* Do sanity check on MSR to make sure we are suspended */ |
132 | li r7, (MSR_TS_S)@higher | |
133 | srdi r6, r14, 32 | |
134 | and r6, r6, r7 | |
135 | 1: tdeqi r6, 0 | |
136 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0 | |
137 | ||
dc310669 CB |
138 | /* Stash the stack pointer away for use after reclaim */ |
139 | std r1, PACAR1(r13) | |
140 | ||
190ce869 MN |
141 | /* Clear MSR RI since we are about to change r1, EE is already off. */ |
142 | li r4, 0 | |
143 | mtmsrd r4, 1 | |
144 | ||
145 | /* | |
146 | * BE CAREFUL HERE: | |
147 | * At this point we can't take an SLB miss since we have MSR_RI | |
148 | * off. Load only to/from the stack/paca which are in SLB bolted regions | |
149 | * until we turn MSR RI back on. | |
150 | * | |
151 | * The moment we treclaim, ALL of our GPRs will switch | |
98ae22e1 MN |
152 | * to user register state. (FPRs, CCR etc. also!) |
153 | * Use an sprg and a tm_scratch in the PACA to shuffle. | |
154 | */ | |
155 | TRECLAIM(R5) /* Cause in r5 */ | |
156 | ||
157 | /* ******************** GPRs ******************** */ | |
158 | /* Stash the checkpointed r13 away in the scratch SPR and get the real | |
159 | * paca | |
160 | */ | |
161 | SET_SCRATCH0(r13) | |
162 | GET_PACA(r13) | |
163 | ||
164 | /* Stash the checkpointed r1 away in paca tm_scratch and get the real | |
165 | * stack pointer back | |
166 | */ | |
167 | std r1, PACATMSCRATCH(r13) | |
168 | ld r1, PACAR1(r13) | |
169 | ||
e9bdc3d6 MN |
170 | /* Store the PPR in r11 and reset to decent value */ |
171 | std r11, GPR11(r1) /* Temporary stash */ | |
190ce869 MN |
172 | |
173 | /* Reset MSR RI so we can take SLB faults again */ | |
174 | li r11, MSR_RI | |
175 | mtmsrd r11, 1 | |
176 | ||
e9bdc3d6 MN |
177 | mfspr r11, SPRN_PPR |
178 | HMT_MEDIUM | |
179 | ||
98ae22e1 MN |
180 | /* Now get some more GPRS free */ |
181 | std r7, GPR7(r1) /* Temporary stash */ | |
182 | std r12, GPR12(r1) /* '' '' '' */ | |
c2e31bdc | 183 | ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */ |
98ae22e1 | 184 | |
e9bdc3d6 MN |
185 | std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */ |
186 | ||
98ae22e1 MN |
187 | addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */ |
188 | ||
189 | /* Make r7 look like an exception frame so that we | |
190 | * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr! | |
191 | */ | |
192 | subi r7, r7, STACK_FRAME_OVERHEAD | |
193 | ||
194 | /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */ | |
195 | SAVE_GPR(0, r7) /* user r0 */ | |
196 | SAVE_GPR(2, r7) /* user r2 */ | |
197 | SAVE_4GPRS(3, r7) /* user r3-r6 */ | |
e9bdc3d6 MN |
198 | SAVE_GPR(8, r7) /* user r8 */ |
199 | SAVE_GPR(9, r7) /* user r9 */ | |
200 | SAVE_GPR(10, r7) /* user r10 */ | |
98ae22e1 MN |
201 | ld r3, PACATMSCRATCH(r13) /* user r1 */ |
202 | ld r4, GPR7(r1) /* user r7 */ | |
e9bdc3d6 MN |
203 | ld r5, GPR11(r1) /* user r11 */ |
204 | ld r6, GPR12(r1) /* user r12 */ | |
205 | GET_SCRATCH0(8) /* user r13 */ | |
98ae22e1 MN |
206 | std r3, GPR1(r7) |
207 | std r4, GPR7(r7) | |
e9bdc3d6 MN |
208 | std r5, GPR11(r7) |
209 | std r6, GPR12(r7) | |
210 | std r8, GPR13(r7) | |
98ae22e1 MN |
211 | |
212 | SAVE_NVGPRS(r7) /* user r14-r31 */ | |
213 | ||
214 | /* ******************** NIP ******************** */ | |
215 | mfspr r3, SPRN_TFHAR | |
216 | std r3, _NIP(r7) /* Returns to failhandler */ | |
217 | /* The checkpointed NIP is ignored when rescheduling/rechkpting, | |
218 | * but is used in signal return to 'wind back' to the abort handler. | |
219 | */ | |
220 | ||
221 | /* ******************** CR,LR,CCR,MSR ********** */ | |
222 | mfctr r3 | |
223 | mflr r4 | |
224 | mfcr r5 | |
225 | mfxer r6 | |
226 | ||
227 | std r3, _CTR(r7) | |
228 | std r4, _LINK(r7) | |
229 | std r5, _CCR(r7) | |
230 | std r6, _XER(r7) | |
231 | ||
28e61cc4 | 232 | |
e9bdc3d6 | 233 | /* ******************** TAR, DSCR ********** */ |
28e61cc4 | 234 | mfspr r3, SPRN_TAR |
e9bdc3d6 | 235 | mfspr r4, SPRN_DSCR |
28e61cc4 MN |
236 | |
237 | std r3, THREAD_TM_TAR(r12) | |
e9bdc3d6 | 238 | std r4, THREAD_TM_DSCR(r12) |
28e61cc4 | 239 | |
98ae22e1 MN |
240 | /* MSR and flags: We don't change CRs, and we don't need to alter |
241 | * MSR. | |
242 | */ | |
243 | ||
dc310669 CB |
244 | |
245 | /* ******************** FPR/VR/VSRs ************ | |
246 | * After reclaiming, capture the checkpointed FPRs/VRs /if used/. | |
247 | * | |
248 | * (If VSX used, FP and VMX are implied. Or, we don't need to look | |
249 | * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.) | |
250 | * | |
251 | * We're passed the thread's MSR as the second parameter | |
252 | * | |
253 | * We enabled VEC/FP/VSX in the msr above, so we can execute these | |
254 | * instructions! | |
255 | */ | |
256 | ld r4, STK_PARAM(R4)(r1) /* Second parameter, MSR * */ | |
257 | mr r3, r12 | |
258 | andis. r0, r4, MSR_VEC@h | |
259 | beq dont_backup_vec | |
260 | ||
000ec280 | 261 | addi r7, r3, THREAD_CKVRSTATE |
dc310669 CB |
262 | SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */ |
263 | mfvscr v0 | |
264 | li r6, VRSTATE_VSCR | |
265 | stvx v0, r7, r6 | |
266 | dont_backup_vec: | |
267 | mfspr r0, SPRN_VRSAVE | |
000ec280 | 268 | std r0, THREAD_CKVRSAVE(r3) |
dc310669 CB |
269 | |
270 | andi. r0, r4, MSR_FP | |
271 | beq dont_backup_fp | |
272 | ||
000ec280 | 273 | addi r7, r3, THREAD_CKFPSTATE |
dc310669 CB |
274 | SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */ |
275 | ||
276 | mffs fr0 | |
277 | stfd fr0,FPSTATE_FPSCR(r7) | |
278 | ||
279 | dont_backup_fp: | |
280 | ||
98ae22e1 MN |
281 | /* TM regs, incl TEXASR -- these live in thread_struct. Note they've |
282 | * been updated by the treclaim, to explain to userland the failure | |
283 | * cause (aborted). | |
284 | */ | |
285 | mfspr r0, SPRN_TEXASR | |
286 | mfspr r3, SPRN_TFHAR | |
287 | mfspr r4, SPRN_TFIAR | |
288 | std r0, THREAD_TM_TEXASR(r12) | |
289 | std r3, THREAD_TM_TFHAR(r12) | |
290 | std r4, THREAD_TM_TFIAR(r12) | |
291 | ||
e9bdc3d6 | 292 | /* AMR is checkpointed too, but is unsupported by Linux. */ |
98ae22e1 MN |
293 | |
294 | /* Restore original MSR/IRQ state & clear TM mode */ | |
295 | ld r14, TM_FRAME_L0(r1) /* Orig MSR */ | |
dc310669 | 296 | |
98ae22e1 MN |
297 | li r15, 0 |
298 | rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1 | |
299 | mtmsrd r14 | |
300 | ||
301 | REST_NVGPRS(r1) | |
302 | ||
303 | addi r1, r1, TM_FRAME_SIZE | |
bbe30b3b | 304 | lwz r4, 8(r1) |
98ae22e1 MN |
305 | ld r0, 16(r1) |
306 | mtcr r4 | |
307 | mtlr r0 | |
6403105b | 308 | ld r2, STK_GOT(r1) |
e9bdc3d6 | 309 | |
1739ea9e | 310 | /* Load CPU's default DSCR */ |
1db36525 | 311 | ld r0, PACA_DSCR_DEFAULT(r13) |
e9bdc3d6 MN |
312 | mtspr SPRN_DSCR, r0 |
313 | ||
98ae22e1 MN |
314 | blr |
315 | ||
316 | ||
2bafb7ff MN |
317 | /* void __tm_recheckpoint(struct thread_struct *thread, |
318 | * unsigned long orig_msr) | |
98ae22e1 MN |
319 | * - Restore the checkpointed register state saved by tm_reclaim |
320 | * when we switch_to a process. | |
321 | * | |
322 | * Call with IRQs off, stacks get all out of sync for | |
323 | * some periods in here! | |
324 | */ | |
e6b8fd02 | 325 | _GLOBAL(__tm_recheckpoint) |
98ae22e1 MN |
326 | mfcr r5 |
327 | mflr r0 | |
bbe30b3b | 328 | stw r5, 8(r1) |
98ae22e1 | 329 | std r0, 16(r1) |
6403105b | 330 | std r2, STK_GOT(r1) |
98ae22e1 MN |
331 | stdu r1, -TM_FRAME_SIZE(r1) |
332 | ||
333 | /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. | |
334 | * This is used for backing up the NVGPRs: | |
335 | */ | |
336 | SAVE_NVGPRS(r1) | |
337 | ||
98ae22e1 MN |
338 | /* Load complete register state from ts_ckpt* registers */ |
339 | ||
340 | addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */ | |
341 | ||
342 | /* Make r7 look like an exception frame so that we | |
343 | * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr! | |
344 | */ | |
345 | subi r7, r7, STACK_FRAME_OVERHEAD | |
346 | ||
98ae22e1 MN |
347 | mfmsr r6 |
348 | /* R4 = original MSR to indicate whether thread used FP/Vector etc. */ | |
349 | ||
350 | /* Enable FP/vec in MSR if necessary! */ | |
351 | lis r5, MSR_VEC@h | |
352 | ori r5, r5, MSR_FP | |
353 | and. r5, r4, r5 | |
354 | beq restore_gprs /* if neither, skip both */ | |
355 | ||
356 | #ifdef CONFIG_VSX | |
357 | BEGIN_FTR_SECTION | |
358 | oris r5, r5, MSR_VSX@h | |
359 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
360 | #endif | |
361 | or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */ | |
362 | mtmsr r5 | |
363 | ||
f110c0c1 | 364 | #ifdef CONFIG_ALTIVEC |
dc310669 CB |
365 | /* |
366 | * FP and VEC registers: These are recheckpointed from | |
367 | * thread.ckfp_state and thread.ckvr_state respectively. The | |
368 | * thread.fp_state[] version holds the 'live' (transactional) | |
369 | * and will be loaded subsequently by any FPUnavailable trap. | |
98ae22e1 MN |
370 | */ |
371 | andis. r0, r4, MSR_VEC@h | |
372 | beq dont_restore_vec | |
373 | ||
000ec280 | 374 | addi r8, r3, THREAD_CKVRSTATE |
de79f7b9 | 375 | li r5, VRSTATE_VSCR |
c2ce6f9f AB |
376 | lvx v0, r8, r5 |
377 | mtvscr v0 | |
de79f7b9 | 378 | REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */ |
408a7e08 | 379 | dont_restore_vec: |
000ec280 | 380 | ld r5, THREAD_CKVRSAVE(r3) |
98ae22e1 | 381 | mtspr SPRN_VRSAVE, r5 |
f110c0c1 | 382 | #endif |
98ae22e1 | 383 | |
98ae22e1 MN |
384 | andi. r0, r4, MSR_FP |
385 | beq dont_restore_fp | |
386 | ||
000ec280 | 387 | addi r8, r3, THREAD_CKFPSTATE |
de79f7b9 | 388 | lfd fr0, FPSTATE_FPSCR(r8) |
98ae22e1 | 389 | MTFSF_L(fr0) |
de79f7b9 | 390 | REST_32FPRS_VSRS(0, R4, R8) |
98ae22e1 MN |
391 | |
392 | dont_restore_fp: | |
393 | mtmsr r6 /* FP/Vec off again! */ | |
394 | ||
395 | restore_gprs: | |
28e61cc4 | 396 | |
e9bdc3d6 MN |
397 | /* ******************** CR,LR,CCR,MSR ********** */ |
398 | ld r4, _CTR(r7) | |
399 | ld r5, _LINK(r7) | |
e9bdc3d6 | 400 | ld r8, _XER(r7) |
28e61cc4 | 401 | |
e9bdc3d6 MN |
402 | mtctr r4 |
403 | mtlr r5 | |
e9bdc3d6 | 404 | mtxer r8 |
28e61cc4 | 405 | |
e9bdc3d6 MN |
406 | /* ******************** TAR ******************** */ |
407 | ld r4, THREAD_TM_TAR(r3) | |
408 | mtspr SPRN_TAR, r4 | |
98ae22e1 | 409 | |
e9bdc3d6 MN |
410 | /* Load up the PPR and DSCR in GPRs only at this stage */ |
411 | ld r5, THREAD_TM_DSCR(r3) | |
412 | ld r6, THREAD_TM_PPR(r3) | |
98ae22e1 | 413 | |
7f06f21d MN |
414 | REST_GPR(0, r7) /* GPR0 */ |
415 | REST_2GPRS(2, r7) /* GPR2-3 */ | |
e9bdc3d6 | 416 | REST_GPR(4, r7) /* GPR4 */ |
98ae22e1 MN |
417 | REST_4GPRS(8, r7) /* GPR8-11 */ |
418 | REST_2GPRS(12, r7) /* GPR12-13 */ | |
419 | ||
420 | REST_NVGPRS(r7) /* GPR14-31 */ | |
421 | ||
e9bdc3d6 MN |
422 | /* Load up PPR and DSCR here so we don't run with user values for long |
423 | */ | |
424 | mtspr SPRN_DSCR, r5 | |
425 | mtspr SPRN_PPR, r6 | |
426 | ||
7f06f21d MN |
427 | /* Do final sanity check on TEXASR to make sure FS is set. Do this |
428 | * here before we load up the userspace r1 so any bugs we hit will get | |
429 | * a call chain */ | |
430 | mfspr r5, SPRN_TEXASR | |
431 | srdi r5, r5, 16 | |
432 | li r6, (TEXASR_FS)@h | |
433 | and r6, r6, r5 | |
434 | 1: tdeqi r6, 0 | |
435 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0 | |
436 | ||
437 | /* Do final sanity check on MSR to make sure we are not transactional | |
438 | * or suspended | |
439 | */ | |
440 | mfmsr r6 | |
441 | li r5, (MSR_TS_MASK)@higher | |
442 | srdi r6, r6, 32 | |
443 | and r6, r6, r5 | |
444 | 1: tdnei r6, 0 | |
445 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0 | |
446 | ||
447 | /* Restore CR */ | |
448 | ld r6, _CCR(r7) | |
449 | mtcr r6 | |
450 | ||
e9bdc3d6 | 451 | REST_GPR(6, r7) |
190ce869 MN |
452 | |
453 | /* | |
454 | * Store r1 and r5 on the stack so that we can access them | |
455 | * after we clear MSR RI. | |
456 | */ | |
457 | ||
458 | REST_GPR(5, r7) | |
459 | std r5, -8(r1) | |
460 | ld r5, GPR1(r7) | |
461 | std r5, -16(r1) | |
462 | ||
463 | REST_GPR(7, r7) | |
464 | ||
465 | /* Clear MSR RI since we are about to change r1. EE is already off */ | |
466 | li r5, 0 | |
467 | mtmsrd r5, 1 | |
468 | ||
469 | /* | |
470 | * BE CAREFUL HERE: | |
471 | * At this point we can't take an SLB miss since we have MSR_RI | |
472 | * off. Load only to/from the stack/paca which are in SLB bolted regions | |
473 | * until we turn MSR RI back on. | |
474 | */ | |
475 | ||
6bcb8014 | 476 | SET_SCRATCH0(r1) |
190ce869 MN |
477 | ld r5, -8(r1) |
478 | ld r1, -16(r1) | |
98ae22e1 MN |
479 | |
480 | /* Commit register state as checkpointed state: */ | |
481 | TRECHKPT | |
482 | ||
e9bdc3d6 MN |
483 | HMT_MEDIUM |
484 | ||
98ae22e1 MN |
485 | /* Our transactional state has now changed. |
486 | * | |
487 | * Now just get out of here. Transactional (current) state will be | |
488 | * updated once restore is called on the return path in the _switch-ed | |
489 | * -to process. | |
490 | */ | |
491 | ||
492 | GET_PACA(r13) | |
493 | GET_SCRATCH0(r1) | |
494 | ||
090b9284 MN |
495 | /* R1 is restored, so we are recoverable again. EE is still off */ |
496 | li r4, MSR_RI | |
497 | mtmsrd r4, 1 | |
498 | ||
98ae22e1 MN |
499 | REST_NVGPRS(r1) |
500 | ||
501 | addi r1, r1, TM_FRAME_SIZE | |
bbe30b3b | 502 | lwz r4, 8(r1) |
98ae22e1 MN |
503 | ld r0, 16(r1) |
504 | mtcr r4 | |
505 | mtlr r0 | |
6403105b | 506 | ld r2, STK_GOT(r1) |
e9bdc3d6 | 507 | |
1739ea9e | 508 | /* Load CPU's default DSCR */ |
1db36525 | 509 | ld r0, PACA_DSCR_DEFAULT(r13) |
e9bdc3d6 MN |
510 | mtspr SPRN_DSCR, r0 |
511 | ||
98ae22e1 MN |
512 | blr |
513 | ||
514 | /* ****************************************************************** */ |