[mirror_ubuntu-disco-kernel.git] / arch / sh / include / asm / pci.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_SH_PCI_H
#define __ASM_SH_PCI_H

#ifdef __KERNEL__

/* Can be used to override the logic in pci_scan_bus for skipping
   already-configured bus numbers - to be used for buggy BIOSes
   or architectures with incomplete PCI setup by the loader */

#define pcibios_assign_all_busses()	1

/*
 * A board can define one or more PCI channels that represent built-in (or
 * external) PCI controllers.
 */
struct pci_channel {
	struct pci_channel	*next;
	struct pci_bus		*bus;

	struct pci_ops		*pci_ops;

	struct resource		*resources;
	unsigned int		nr_resources;

	unsigned long		io_offset;
	unsigned long		mem_offset;

	unsigned long		reg_base;
	unsigned long		io_map_base;

	unsigned int		index;
	unsigned int		need_domain_info;

	/* Optional error handling */
	struct timer_list	err_timer, serr_timer;
	unsigned int		err_irq, serr_irq;
};

/* arch/sh/drivers/pci/pci.c */
extern raw_spinlock_t pci_config_lock;

extern int register_pci_controller(struct pci_channel *hose);
extern void pcibios_report_status(unsigned int status_mask, int warn);

/* arch/sh/drivers/pci/common.c */
extern int early_read_config_byte(struct pci_channel *hose, int top_bus,
				  int bus, int devfn, int offset, u8 *value);
extern int early_read_config_word(struct pci_channel *hose, int top_bus,
				  int bus, int devfn, int offset, u16 *value);
extern int early_read_config_dword(struct pci_channel *hose, int top_bus,
				   int bus, int devfn, int offset, u32 *value);
extern int early_write_config_byte(struct pci_channel *hose, int top_bus,
				   int bus, int devfn, int offset, u8 value);
extern int early_write_config_word(struct pci_channel *hose, int top_bus,
				   int bus, int devfn, int offset, u16 value);
extern int early_write_config_dword(struct pci_channel *hose, int top_bus,
				    int bus, int devfn, int offset, u32 value);
extern void pcibios_enable_timers(struct pci_channel *hose);
extern unsigned int pcibios_handle_status_errors(unsigned long addr,
				 unsigned int status, struct pci_channel *hose);
extern int pci_is_66mhz_capable(struct pci_channel *hose,
				int top_bus, int current_bus);

extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;

struct pci_dev;

#define HAVE_PCI_MMAP
#define ARCH_GENERIC_PCI_MMAP_RESOURCE

extern void pcibios_set_master(struct pci_dev *dev);

/* Dynamic DMA mapping stuff.
 * SuperH has everything mapped statically like x86.
 */

/* The PCI address space does equal the physical memory
 * address space.  The networking and block device layers use
 * this boolean for bounce buffer decisions.
 */
#define PCI_DMA_BUS_IS_PHYS	(dma_ops->is_phys)

#ifdef CONFIG_PCI
/*
 * None of the SH PCI controllers support MWI, it is always treated as a
 * direct memory write.
 */
#define PCI_DISABLE_MWI
#endif

/* Board-specific fixup routines. */
int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);

#define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index

static inline int pci_proc_domain(struct pci_bus *bus)
{
	struct pci_channel *hose = bus->sysdata;
	return hose->need_domain_info;
}

/* Chances are this interrupt is wired PC-style ...  */
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
	return channel ? 15 : 14;
}

#endif /* __KERNEL__ */
#endif /* __ASM_SH_PCI_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 LT	2	#ifndef __ASM_SH_PCI_H
	3	#define __ASM_SH_PCI_H
	4
	5	#ifdef __KERNEL__
	6
1da177e4 LT	7	/* Can be used to override the logic in pci_scan_bus for skipping
	8	already-configured bus numbers - to be used for buggy BIOSes
	9	or architectures with incomplete PCI setup by the loader */
	10
	11	#define pcibios_assign_all_busses() 1
1da177e4 LT	12
	13	/*
	14	* A board can define one or more PCI channels that represent built-in (or
	15	* external) PCI controllers.
	16	*/
	17	struct pci_channel {
e79066a6	18	struct pci_channel *next;
320e68da	19	struct pci_bus *bus;
e79066a6	20
e79066a6	21	struct pci_ops *pci_ops;
b6c58b1d PM	22
	23	struct resource *resources;
	24	unsigned int nr_resources;
e79066a6	25
09cfeb13 PM	26	unsigned long io_offset;
	27	unsigned long mem_offset;
	28
e79066a6	29	unsigned long reg_base;
e79066a6	30	unsigned long io_map_base;
320e68da PM	31
	32	unsigned int index;
	33	unsigned int need_domain_info;
ef407bee PM	34
	35	/* Optional error handling */
	36	struct timer_list err_timer, serr_timer;
	37	unsigned int err_irq, serr_irq;
1da177e4 LT	38	};
1da177e4 LT	39
ef407bee	40	/* arch/sh/drivers/pci/pci.c */
39a90865 PM	41	extern raw_spinlock_t pci_config_lock;
39a90865 PM	42
bcf39352	43	extern int register_pci_controller(struct pci_channel *hose);
ef407bee PM	44	extern void pcibios_report_status(unsigned int status_mask, int warn);
	45
	46	/* arch/sh/drivers/pci/common.c */
9ad62ec4 PM	47	extern int early_read_config_byte(struct pci_channel *hose, int top_bus,
	48	int bus, int devfn, int offset, u8 *value);
	49	extern int early_read_config_word(struct pci_channel *hose, int top_bus,
	50	int bus, int devfn, int offset, u16 *value);
	51	extern int early_read_config_dword(struct pci_channel *hose, int top_bus,
	52	int bus, int devfn, int offset, u32 *value);
	53	extern int early_write_config_byte(struct pci_channel *hose, int top_bus,
	54	int bus, int devfn, int offset, u8 value);
	55	extern int early_write_config_word(struct pci_channel *hose, int top_bus,
	56	int bus, int devfn, int offset, u16 value);
	57	extern int early_write_config_dword(struct pci_channel *hose, int top_bus,
	58	int bus, int devfn, int offset, u32 value);
ef407bee PM	59	extern void pcibios_enable_timers(struct pci_channel *hose);
	60	extern unsigned int pcibios_handle_status_errors(unsigned long addr,
	61	unsigned int status, struct pci_channel *hose);
85b59f5b PM	62	extern int pci_is_66mhz_capable(struct pci_channel *hose,
85b59f5b PM	63	int top_bus, int current_bus);
e79066a6	64
a3c0e0d0	65	extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
1da177e4 LT	66
	67	struct pci_dev;
	68
98333851	69	#define HAVE_PCI_MMAP
adf7bde6	70	#define ARCH_GENERIC_PCI_MMAP_RESOURCE
11df1954	71
1da177e4 LT	72	extern void pcibios_set_master(struct pci_dev *dev);
1da177e4 LT	73
1da177e4 LT	74	/* Dynamic DMA mapping stuff.
	75	* SuperH has everything mapped statically like x86.
	76	*/
	77
	78	/* The PCI address space does equal the physical memory
	79	* address space. The networking and block device layers use
	80	* this boolean for bounce buffer decisions.
	81	*/
73c926be	82	#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
1da177e4	83
3e98f9f1	84	#ifdef CONFIG_PCI
b7e2ac61 PM	85	/*
	86	* None of the SH PCI controllers support MWI, it is always treated as a
	87	* direct memory write.
	88	*/
	89	#define PCI_DISABLE_MWI
3e98f9f1	90	#endif
ef339f24	91
1da177e4	92	/* Board-specific fixup routines. */
d5341942	93	int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
1da177e4	94
320e68da PM	95	#define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
	96
	97	static inline int pci_proc_domain(struct pci_bus *bus)
	98	{
	99	struct pci_channel *hose = bus->sysdata;
	100	return hose->need_domain_info;
	101	}
	102
9ade1217 PM	103	/* Chances are this interrupt is wired PC-style ... */
	104	static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
	105	{
	106	return channel ? 15 : 14;
	107	}
1da177e4	108
9ade1217	109	#endif /* __KERNEL__ */
1da177e4 LT	110	#endif /* __ASM_SH_PCI_H */
1da177e4 LT	111