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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | /* |
3 | * linux/arch/x86_64/entry.S | |
4 | * | |
5 | * Copyright (C) 1991, 1992 Linus Torvalds | |
6 | * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs | |
7 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
4d732138 | 8 | * |
1da177e4 LT |
9 | * entry.S contains the system-call and fault low-level handling routines. |
10 | * | |
8b4777a4 AL |
11 | * Some of this is documented in Documentation/x86/entry_64.txt |
12 | * | |
0bd7b798 | 13 | * A note on terminology: |
4d732138 IM |
14 | * - iret frame: Architecture defined interrupt frame from SS to RIP |
15 | * at the top of the kernel process stack. | |
2e91a17b AK |
16 | * |
17 | * Some macro usage: | |
4d732138 IM |
18 | * - ENTRY/END: Define functions in the symbol table. |
19 | * - TRACE_IRQ_*: Trace hardirq state for lock debugging. | |
20 | * - idtentry: Define exception entry points. | |
1da177e4 | 21 | */ |
1da177e4 LT |
22 | #include <linux/linkage.h> |
23 | #include <asm/segment.h> | |
1da177e4 LT |
24 | #include <asm/cache.h> |
25 | #include <asm/errno.h> | |
e2d5df93 | 26 | #include <asm/asm-offsets.h> |
1da177e4 LT |
27 | #include <asm/msr.h> |
28 | #include <asm/unistd.h> | |
29 | #include <asm/thread_info.h> | |
30 | #include <asm/hw_irq.h> | |
0341c14d | 31 | #include <asm/page_types.h> |
2601e64d | 32 | #include <asm/irqflags.h> |
72fe4858 | 33 | #include <asm/paravirt.h> |
9939ddaf | 34 | #include <asm/percpu.h> |
d7abc0fa | 35 | #include <asm/asm.h> |
63bcff2a | 36 | #include <asm/smap.h> |
3891a04a | 37 | #include <asm/pgtable_types.h> |
784d5699 | 38 | #include <asm/export.h> |
8c1f7558 | 39 | #include <asm/frame.h> |
2641f08b | 40 | #include <asm/nospec-branch.h> |
d7e7528b | 41 | #include <linux/err.h> |
1da177e4 | 42 | |
6fd166aa PZ |
43 | #include "calling.h" |
44 | ||
4d732138 IM |
45 | .code64 |
46 | .section .entry.text, "ax" | |
16444a8a | 47 | |
72fe4858 | 48 | #ifdef CONFIG_PARAVIRT |
2be29982 | 49 | ENTRY(native_usergs_sysret64) |
8c1f7558 | 50 | UNWIND_HINT_EMPTY |
72fe4858 GOC |
51 | swapgs |
52 | sysretq | |
8c1f7558 | 53 | END(native_usergs_sysret64) |
72fe4858 GOC |
54 | #endif /* CONFIG_PARAVIRT */ |
55 | ||
ca37e57b | 56 | .macro TRACE_IRQS_FLAGS flags:req |
2601e64d | 57 | #ifdef CONFIG_TRACE_IRQFLAGS |
a368d7fd | 58 | btl $9, \flags /* interrupts off? */ |
4d732138 | 59 | jnc 1f |
2601e64d IM |
60 | TRACE_IRQS_ON |
61 | 1: | |
62 | #endif | |
63 | .endm | |
64 | ||
ca37e57b AL |
65 | .macro TRACE_IRQS_IRETQ |
66 | TRACE_IRQS_FLAGS EFLAGS(%rsp) | |
67 | .endm | |
68 | ||
5963e317 SR |
69 | /* |
70 | * When dynamic function tracer is enabled it will add a breakpoint | |
71 | * to all locations that it is about to modify, sync CPUs, update | |
72 | * all the code, sync CPUs, then remove the breakpoints. In this time | |
73 | * if lockdep is enabled, it might jump back into the debug handler | |
74 | * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). | |
75 | * | |
76 | * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to | |
77 | * make sure the stack pointer does not get reset back to the top | |
78 | * of the debug stack, and instead just reuses the current stack. | |
79 | */ | |
80 | #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) | |
81 | ||
82 | .macro TRACE_IRQS_OFF_DEBUG | |
4d732138 | 83 | call debug_stack_set_zero |
5963e317 | 84 | TRACE_IRQS_OFF |
4d732138 | 85 | call debug_stack_reset |
5963e317 SR |
86 | .endm |
87 | ||
88 | .macro TRACE_IRQS_ON_DEBUG | |
4d732138 | 89 | call debug_stack_set_zero |
5963e317 | 90 | TRACE_IRQS_ON |
4d732138 | 91 | call debug_stack_reset |
5963e317 SR |
92 | .endm |
93 | ||
f2db9382 | 94 | .macro TRACE_IRQS_IRETQ_DEBUG |
6709812f | 95 | btl $9, EFLAGS(%rsp) /* interrupts off? */ |
4d732138 | 96 | jnc 1f |
5963e317 SR |
97 | TRACE_IRQS_ON_DEBUG |
98 | 1: | |
99 | .endm | |
100 | ||
101 | #else | |
4d732138 IM |
102 | # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF |
103 | # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON | |
104 | # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ | |
5963e317 SR |
105 | #endif |
106 | ||
1da177e4 | 107 | /* |
4d732138 | 108 | * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. |
1da177e4 | 109 | * |
fda57b22 AL |
110 | * This is the only entry point used for 64-bit system calls. The |
111 | * hardware interface is reasonably well designed and the register to | |
112 | * argument mapping Linux uses fits well with the registers that are | |
113 | * available when SYSCALL is used. | |
114 | * | |
115 | * SYSCALL instructions can be found inlined in libc implementations as | |
116 | * well as some other programs and libraries. There are also a handful | |
117 | * of SYSCALL instructions in the vDSO used, for example, as a | |
118 | * clock_gettimeofday fallback. | |
119 | * | |
4d732138 | 120 | * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, |
b87cf63e DV |
121 | * then loads new ss, cs, and rip from previously programmed MSRs. |
122 | * rflags gets masked by a value from another MSR (so CLD and CLAC | |
123 | * are not needed). SYSCALL does not save anything on the stack | |
124 | * and does not change rsp. | |
125 | * | |
126 | * Registers on entry: | |
1da177e4 | 127 | * rax system call number |
b87cf63e DV |
128 | * rcx return address |
129 | * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) | |
1da177e4 | 130 | * rdi arg0 |
1da177e4 | 131 | * rsi arg1 |
0bd7b798 | 132 | * rdx arg2 |
b87cf63e | 133 | * r10 arg3 (needs to be moved to rcx to conform to C ABI) |
1da177e4 LT |
134 | * r8 arg4 |
135 | * r9 arg5 | |
4d732138 | 136 | * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) |
0bd7b798 | 137 | * |
1da177e4 LT |
138 | * Only called from user space. |
139 | * | |
7fcb3bc3 | 140 | * When user can change pt_regs->foo always force IRET. That is because |
7bf36bbc AK |
141 | * it deals with uncanonical addresses better. SYSRET has trouble |
142 | * with them due to bugs in both AMD and Intel CPUs. | |
0bd7b798 | 143 | */ |
1da177e4 | 144 | |
b2502b41 | 145 | ENTRY(entry_SYSCALL_64) |
8c1f7558 | 146 | UNWIND_HINT_EMPTY |
9ed8e7d8 DV |
147 | /* |
148 | * Interrupts are off on entry. | |
149 | * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, | |
150 | * it is too small to ever cause noticeable irq latency. | |
151 | */ | |
72fe4858 | 152 | |
8a9949bc | 153 | swapgs |
bf904d27 | 154 | /* tss.sp2 is scratch space. */ |
98f05b51 | 155 | movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2) |
bf904d27 | 156 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp |
4d732138 | 157 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp |
9ed8e7d8 DV |
158 | |
159 | /* Construct struct pt_regs on stack */ | |
98f05b51 AL |
160 | pushq $__USER_DS /* pt_regs->ss */ |
161 | pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */ | |
162 | pushq %r11 /* pt_regs->flags */ | |
163 | pushq $__USER_CS /* pt_regs->cs */ | |
164 | pushq %rcx /* pt_regs->ip */ | |
8a9949bc | 165 | GLOBAL(entry_SYSCALL_64_after_hwframe) |
98f05b51 | 166 | pushq %rax /* pt_regs->orig_ax */ |
30907fd1 DB |
167 | |
168 | PUSH_AND_CLEAR_REGS rax=$-ENOSYS | |
4d732138 | 169 | |
548c3050 AL |
170 | TRACE_IRQS_OFF |
171 | ||
1e423bff | 172 | /* IRQs are off. */ |
dfe64506 LT |
173 | movq %rax, %rdi |
174 | movq %rsp, %rsi | |
1e423bff AL |
175 | call do_syscall_64 /* returns with IRQs disabled */ |
176 | ||
29ea1b25 | 177 | TRACE_IRQS_IRETQ /* we're about to change IF */ |
fffbb5dc DV |
178 | |
179 | /* | |
180 | * Try to use SYSRET instead of IRET if we're returning to | |
8a055d7f AL |
181 | * a completely clean 64-bit userspace context. If we're not, |
182 | * go to the slow exit path. | |
fffbb5dc | 183 | */ |
4d732138 IM |
184 | movq RCX(%rsp), %rcx |
185 | movq RIP(%rsp), %r11 | |
8a055d7f AL |
186 | |
187 | cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ | |
188 | jne swapgs_restore_regs_and_return_to_usermode | |
fffbb5dc DV |
189 | |
190 | /* | |
191 | * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP | |
192 | * in kernel space. This essentially lets the user take over | |
17be0aec | 193 | * the kernel, since userspace controls RSP. |
fffbb5dc | 194 | * |
17be0aec | 195 | * If width of "canonical tail" ever becomes variable, this will need |
fffbb5dc | 196 | * to be updated to remain correct on both old and new CPUs. |
361b4b58 | 197 | * |
cbe0317b KS |
198 | * Change top bits to match most significant bit (47th or 56th bit |
199 | * depending on paging mode) in the address. | |
fffbb5dc | 200 | */ |
09e61a77 | 201 | #ifdef CONFIG_X86_5LEVEL |
39b95522 KS |
202 | ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \ |
203 | "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57 | |
09e61a77 | 204 | #else |
17be0aec DV |
205 | shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx |
206 | sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx | |
09e61a77 | 207 | #endif |
4d732138 | 208 | |
17be0aec DV |
209 | /* If this changed %rcx, it was not canonical */ |
210 | cmpq %rcx, %r11 | |
8a055d7f | 211 | jne swapgs_restore_regs_and_return_to_usermode |
fffbb5dc | 212 | |
4d732138 | 213 | cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ |
8a055d7f | 214 | jne swapgs_restore_regs_and_return_to_usermode |
fffbb5dc | 215 | |
4d732138 IM |
216 | movq R11(%rsp), %r11 |
217 | cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ | |
8a055d7f | 218 | jne swapgs_restore_regs_and_return_to_usermode |
fffbb5dc DV |
219 | |
220 | /* | |
3e035305 BP |
221 | * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot |
222 | * restore RF properly. If the slowpath sets it for whatever reason, we | |
223 | * need to restore it correctly. | |
224 | * | |
225 | * SYSRET can restore TF, but unlike IRET, restoring TF results in a | |
226 | * trap from userspace immediately after SYSRET. This would cause an | |
227 | * infinite loop whenever #DB happens with register state that satisfies | |
228 | * the opportunistic SYSRET conditions. For example, single-stepping | |
229 | * this user code: | |
fffbb5dc | 230 | * |
4d732138 | 231 | * movq $stuck_here, %rcx |
fffbb5dc DV |
232 | * pushfq |
233 | * popq %r11 | |
234 | * stuck_here: | |
235 | * | |
236 | * would never get past 'stuck_here'. | |
237 | */ | |
4d732138 | 238 | testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 |
8a055d7f | 239 | jnz swapgs_restore_regs_and_return_to_usermode |
fffbb5dc DV |
240 | |
241 | /* nothing to check for RSP */ | |
242 | ||
4d732138 | 243 | cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ |
8a055d7f | 244 | jne swapgs_restore_regs_and_return_to_usermode |
fffbb5dc DV |
245 | |
246 | /* | |
4d732138 IM |
247 | * We win! This label is here just for ease of understanding |
248 | * perf profiles. Nothing jumps here. | |
fffbb5dc DV |
249 | */ |
250 | syscall_return_via_sysret: | |
17be0aec | 251 | /* rcx and r11 are already restored (see code above) */ |
8c1f7558 | 252 | UNWIND_HINT_EMPTY |
502af0d7 | 253 | POP_REGS pop_rdi=0 skip_r11rcx=1 |
3e3b9293 AL |
254 | |
255 | /* | |
256 | * Now all regs are restored except RSP and RDI. | |
257 | * Save old stack pointer and switch to trampoline stack. | |
258 | */ | |
259 | movq %rsp, %rdi | |
c482feef | 260 | movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp |
3e3b9293 AL |
261 | |
262 | pushq RSP-RDI(%rdi) /* RSP */ | |
263 | pushq (%rdi) /* RDI */ | |
264 | ||
265 | /* | |
266 | * We are on the trampoline stack. All regs except RDI are live. | |
267 | * We can do future final exit work right here. | |
268 | */ | |
afaef01c AP |
269 | STACKLEAK_ERASE_NOCLOBBER |
270 | ||
6fd166aa | 271 | SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi |
3e3b9293 | 272 | |
4fbb3910 | 273 | popq %rdi |
3e3b9293 | 274 | popq %rsp |
fffbb5dc | 275 | USERGS_SYSRET64 |
b2502b41 | 276 | END(entry_SYSCALL_64) |
0bd7b798 | 277 | |
0100301b BG |
278 | /* |
279 | * %rdi: prev task | |
280 | * %rsi: next task | |
281 | */ | |
282 | ENTRY(__switch_to_asm) | |
8c1f7558 | 283 | UNWIND_HINT_FUNC |
0100301b BG |
284 | /* |
285 | * Save callee-saved registers | |
286 | * This must match the order in inactive_task_frame | |
287 | */ | |
288 | pushq %rbp | |
289 | pushq %rbx | |
290 | pushq %r12 | |
291 | pushq %r13 | |
292 | pushq %r14 | |
293 | pushq %r15 | |
7becd7b3 | 294 | pushfq |
0100301b BG |
295 | |
296 | /* switch stack */ | |
297 | movq %rsp, TASK_threadsp(%rdi) | |
298 | movq TASK_threadsp(%rsi), %rsp | |
299 | ||
050e9baa | 300 | #ifdef CONFIG_STACKPROTECTOR |
0100301b BG |
301 | movq TASK_stack_canary(%rsi), %rbx |
302 | movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset | |
303 | #endif | |
304 | ||
c995efd5 DW |
305 | #ifdef CONFIG_RETPOLINE |
306 | /* | |
307 | * When switching from a shallower to a deeper call stack | |
308 | * the RSB may either underflow or use entries populated | |
309 | * with userspace addresses. On CPUs where those concerns | |
310 | * exist, overwrite the RSB with entries which capture | |
311 | * speculative execution to prevent attack. | |
312 | */ | |
d1c99108 | 313 | FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW |
c995efd5 DW |
314 | #endif |
315 | ||
0100301b | 316 | /* restore callee-saved registers */ |
7becd7b3 | 317 | popfq |
0100301b BG |
318 | popq %r15 |
319 | popq %r14 | |
320 | popq %r13 | |
321 | popq %r12 | |
322 | popq %rbx | |
323 | popq %rbp | |
324 | ||
325 | jmp __switch_to | |
326 | END(__switch_to_asm) | |
327 | ||
1eeb207f DV |
328 | /* |
329 | * A newly forked process directly context switches into this address. | |
330 | * | |
0100301b | 331 | * rax: prev task we switched from |
616d2483 BG |
332 | * rbx: kernel thread func (NULL for user thread) |
333 | * r12: kernel thread arg | |
1eeb207f DV |
334 | */ |
335 | ENTRY(ret_from_fork) | |
8c1f7558 | 336 | UNWIND_HINT_EMPTY |
0100301b | 337 | movq %rax, %rdi |
ebd57499 | 338 | call schedule_tail /* rdi: 'prev' task parameter */ |
1eeb207f | 339 | |
ebd57499 JP |
340 | testq %rbx, %rbx /* from kernel_thread? */ |
341 | jnz 1f /* kernel threads are uncommon */ | |
24d978b7 | 342 | |
616d2483 | 343 | 2: |
8c1f7558 | 344 | UNWIND_HINT_REGS |
ebd57499 | 345 | movq %rsp, %rdi |
24d978b7 AL |
346 | call syscall_return_slowpath /* returns with IRQs disabled */ |
347 | TRACE_IRQS_ON /* user mode is traced as IRQS on */ | |
8a055d7f | 348 | jmp swapgs_restore_regs_and_return_to_usermode |
616d2483 BG |
349 | |
350 | 1: | |
351 | /* kernel thread */ | |
d31a5802 | 352 | UNWIND_HINT_EMPTY |
616d2483 | 353 | movq %r12, %rdi |
2641f08b | 354 | CALL_NOSPEC %rbx |
616d2483 BG |
355 | /* |
356 | * A kernel thread is allowed to return here after successfully | |
357 | * calling do_execve(). Exit to userspace to complete the execve() | |
358 | * syscall. | |
359 | */ | |
360 | movq $0, RAX(%rsp) | |
361 | jmp 2b | |
1eeb207f DV |
362 | END(ret_from_fork) |
363 | ||
939b7871 | 364 | /* |
3304c9c3 DV |
365 | * Build the entry stubs with some assembler magic. |
366 | * We pack 1 stub into every 8-byte block. | |
939b7871 | 367 | */ |
3304c9c3 | 368 | .align 8 |
939b7871 | 369 | ENTRY(irq_entries_start) |
3304c9c3 DV |
370 | vector=FIRST_EXTERNAL_VECTOR |
371 | .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) | |
8c1f7558 | 372 | UNWIND_HINT_IRET_REGS |
4d732138 | 373 | pushq $(~vector+0x80) /* Note: always in signed byte range */ |
3304c9c3 | 374 | jmp common_interrupt |
3304c9c3 | 375 | .align 8 |
8c1f7558 | 376 | vector=vector+1 |
3304c9c3 | 377 | .endr |
939b7871 PA |
378 | END(irq_entries_start) |
379 | ||
1d3e53e8 AL |
380 | .macro DEBUG_ENTRY_ASSERT_IRQS_OFF |
381 | #ifdef CONFIG_DEBUG_ENTRY | |
e17f8234 BO |
382 | pushq %rax |
383 | SAVE_FLAGS(CLBR_RAX) | |
384 | testl $X86_EFLAGS_IF, %eax | |
1d3e53e8 AL |
385 | jz .Lokay_\@ |
386 | ud2 | |
387 | .Lokay_\@: | |
e17f8234 | 388 | popq %rax |
1d3e53e8 AL |
389 | #endif |
390 | .endm | |
391 | ||
392 | /* | |
393 | * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers | |
394 | * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. | |
395 | * Requires kernel GSBASE. | |
396 | * | |
397 | * The invariant is that, if irq_count != -1, then the IRQ stack is in use. | |
398 | */ | |
2ba64741 | 399 | .macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0 |
1d3e53e8 | 400 | DEBUG_ENTRY_ASSERT_IRQS_OFF |
2ba64741 DB |
401 | |
402 | .if \save_ret | |
403 | /* | |
404 | * If save_ret is set, the original stack contains one additional | |
405 | * entry -- the return address. Therefore, move the address one | |
406 | * entry below %rsp to \old_rsp. | |
407 | */ | |
408 | leaq 8(%rsp), \old_rsp | |
409 | .else | |
1d3e53e8 | 410 | movq %rsp, \old_rsp |
2ba64741 | 411 | .endif |
8c1f7558 JP |
412 | |
413 | .if \regs | |
414 | UNWIND_HINT_REGS base=\old_rsp | |
415 | .endif | |
416 | ||
1d3e53e8 | 417 | incl PER_CPU_VAR(irq_count) |
29955909 | 418 | jnz .Lirq_stack_push_old_rsp_\@ |
1d3e53e8 AL |
419 | |
420 | /* | |
421 | * Right now, if we just incremented irq_count to zero, we've | |
422 | * claimed the IRQ stack but we haven't switched to it yet. | |
423 | * | |
424 | * If anything is added that can interrupt us here without using IST, | |
425 | * it must be *extremely* careful to limit its stack usage. This | |
426 | * could include kprobes and a hypothetical future IST-less #DB | |
427 | * handler. | |
29955909 AL |
428 | * |
429 | * The OOPS unwinder relies on the word at the top of the IRQ | |
430 | * stack linking back to the previous RSP for the entire time we're | |
431 | * on the IRQ stack. For this to work reliably, we need to write | |
432 | * it before we actually move ourselves to the IRQ stack. | |
433 | */ | |
434 | ||
435 | movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8) | |
436 | movq PER_CPU_VAR(irq_stack_ptr), %rsp | |
437 | ||
438 | #ifdef CONFIG_DEBUG_ENTRY | |
439 | /* | |
440 | * If the first movq above becomes wrong due to IRQ stack layout | |
441 | * changes, the only way we'll notice is if we try to unwind right | |
442 | * here. Assert that we set up the stack right to catch this type | |
443 | * of bug quickly. | |
1d3e53e8 | 444 | */ |
29955909 AL |
445 | cmpq -8(%rsp), \old_rsp |
446 | je .Lirq_stack_okay\@ | |
447 | ud2 | |
448 | .Lirq_stack_okay\@: | |
449 | #endif | |
1d3e53e8 | 450 | |
29955909 | 451 | .Lirq_stack_push_old_rsp_\@: |
1d3e53e8 | 452 | pushq \old_rsp |
8c1f7558 JP |
453 | |
454 | .if \regs | |
455 | UNWIND_HINT_REGS indirect=1 | |
456 | .endif | |
2ba64741 DB |
457 | |
458 | .if \save_ret | |
459 | /* | |
460 | * Push the return address to the stack. This return address can | |
461 | * be found at the "real" original RSP, which was offset by 8 at | |
462 | * the beginning of this macro. | |
463 | */ | |
464 | pushq -8(\old_rsp) | |
465 | .endif | |
1d3e53e8 AL |
466 | .endm |
467 | ||
468 | /* | |
469 | * Undoes ENTER_IRQ_STACK. | |
470 | */ | |
8c1f7558 | 471 | .macro LEAVE_IRQ_STACK regs=1 |
1d3e53e8 AL |
472 | DEBUG_ENTRY_ASSERT_IRQS_OFF |
473 | /* We need to be off the IRQ stack before decrementing irq_count. */ | |
474 | popq %rsp | |
475 | ||
8c1f7558 JP |
476 | .if \regs |
477 | UNWIND_HINT_REGS | |
478 | .endif | |
479 | ||
1d3e53e8 AL |
480 | /* |
481 | * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming | |
482 | * the irq stack but we're not on it. | |
483 | */ | |
484 | ||
485 | decl PER_CPU_VAR(irq_count) | |
486 | .endm | |
487 | ||
d99015b1 | 488 | /* |
f3d415ea | 489 | * Interrupt entry helper function. |
d99015b1 | 490 | * |
f3d415ea DB |
491 | * Entry runs with interrupts off. Stack layout at entry: |
492 | * +----------------------------------------------------+ | |
493 | * | regs->ss | | |
494 | * | regs->rsp | | |
495 | * | regs->eflags | | |
496 | * | regs->cs | | |
497 | * | regs->ip | | |
498 | * +----------------------------------------------------+ | |
499 | * | regs->orig_ax = ~(interrupt number) | | |
500 | * +----------------------------------------------------+ | |
501 | * | return address | | |
502 | * +----------------------------------------------------+ | |
d99015b1 | 503 | */ |
f3d415ea DB |
504 | ENTRY(interrupt_entry) |
505 | UNWIND_HINT_FUNC | |
506 | ASM_CLAC | |
f6f64681 | 507 | cld |
7f2590a1 | 508 | |
f3d415ea | 509 | testb $3, CS-ORIG_RAX+8(%rsp) |
7f2590a1 AL |
510 | jz 1f |
511 | SWAPGS | |
1b4e3ce4 | 512 | FENCE_SWAPGS_USER_ENTRY |
f3d415ea DB |
513 | /* |
514 | * Switch to the thread stack. The IRET frame and orig_ax are | |
515 | * on the stack, as well as the return address. RDI..R12 are | |
516 | * not (yet) on the stack and space has not (yet) been | |
517 | * allocated for them. | |
518 | */ | |
90a6acc4 | 519 | pushq %rdi |
f3d415ea | 520 | |
90a6acc4 DB |
521 | /* Need to switch before accessing the thread stack. */ |
522 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi | |
523 | movq %rsp, %rdi | |
524 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
f3d415ea DB |
525 | |
526 | /* | |
527 | * We have RDI, return address, and orig_ax on the stack on | |
528 | * top of the IRET frame. That means offset=24 | |
529 | */ | |
530 | UNWIND_HINT_IRET_REGS base=%rdi offset=24 | |
90a6acc4 DB |
531 | |
532 | pushq 7*8(%rdi) /* regs->ss */ | |
533 | pushq 6*8(%rdi) /* regs->rsp */ | |
534 | pushq 5*8(%rdi) /* regs->eflags */ | |
535 | pushq 4*8(%rdi) /* regs->cs */ | |
536 | pushq 3*8(%rdi) /* regs->ip */ | |
537 | pushq 2*8(%rdi) /* regs->orig_ax */ | |
538 | pushq 8(%rdi) /* return address */ | |
539 | UNWIND_HINT_FUNC | |
540 | ||
541 | movq (%rdi), %rdi | |
4447a7d2 | 542 | jmp 2f |
7f2590a1 | 543 | 1: |
1b4e3ce4 JP |
544 | FENCE_SWAPGS_KERNEL_ENTRY |
545 | 2: | |
0e34d226 DB |
546 | PUSH_AND_CLEAR_REGS save_ret=1 |
547 | ENCODE_FRAME_POINTER 8 | |
76f5df43 | 548 | |
2ba64741 | 549 | testb $3, CS+8(%rsp) |
dde74f2e | 550 | jz 1f |
02bc7768 AL |
551 | |
552 | /* | |
7f2590a1 AL |
553 | * IRQ from user mode. |
554 | * | |
f1075053 AL |
555 | * We need to tell lockdep that IRQs are off. We can't do this until |
556 | * we fix gsbase, and we should do it before enter_from_user_mode | |
f3d415ea | 557 | * (which can take locks). Since TRACE_IRQS_OFF is idempotent, |
f1075053 AL |
558 | * the simplest way to handle it is to just call it twice if |
559 | * we enter from user mode. There's no reason to optimize this since | |
560 | * TRACE_IRQS_OFF is a no-op if lockdep is off. | |
561 | */ | |
562 | TRACE_IRQS_OFF | |
563 | ||
478dc89c | 564 | CALL_enter_from_user_mode |
02bc7768 | 565 | |
76f5df43 | 566 | 1: |
2ba64741 | 567 | ENTER_IRQ_STACK old_rsp=%rdi save_ret=1 |
f6f64681 DV |
568 | /* We entered an interrupt context - irqs are off: */ |
569 | TRACE_IRQS_OFF | |
570 | ||
2ba64741 DB |
571 | ret |
572 | END(interrupt_entry) | |
a50480cb | 573 | _ASM_NOKPROBE(interrupt_entry) |
2ba64741 | 574 | |
f3d415ea DB |
575 | |
576 | /* Interrupt entry/exit. */ | |
1da177e4 | 577 | |
722024db AH |
578 | /* |
579 | * The interrupt stubs push (~vector+0x80) onto the stack and | |
580 | * then jump to common_interrupt. | |
581 | */ | |
939b7871 PA |
582 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
583 | common_interrupt: | |
4d732138 | 584 | addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ |
3aa99fc3 DB |
585 | call interrupt_entry |
586 | UNWIND_HINT_REGS indirect=1 | |
587 | call do_IRQ /* rdi points to pt_regs */ | |
34061f13 | 588 | /* 0(%rsp): old RSP */ |
7effaa88 | 589 | ret_from_intr: |
2140a994 | 590 | DISABLE_INTERRUPTS(CLBR_ANY) |
2601e64d | 591 | TRACE_IRQS_OFF |
625dbc3b | 592 | |
1d3e53e8 | 593 | LEAVE_IRQ_STACK |
625dbc3b | 594 | |
03335e95 | 595 | testb $3, CS(%rsp) |
dde74f2e | 596 | jz retint_kernel |
4d732138 | 597 | |
02bc7768 | 598 | /* Interrupt came from user space */ |
02bc7768 AL |
599 | GLOBAL(retint_user) |
600 | mov %rsp,%rdi | |
601 | call prepare_exit_to_usermode | |
2601e64d | 602 | TRACE_IRQS_IRETQ |
26c4ef9c | 603 | |
8a055d7f | 604 | GLOBAL(swapgs_restore_regs_and_return_to_usermode) |
26c4ef9c AL |
605 | #ifdef CONFIG_DEBUG_ENTRY |
606 | /* Assert that pt_regs indicates user mode. */ | |
1e4c4f61 | 607 | testb $3, CS(%rsp) |
26c4ef9c AL |
608 | jnz 1f |
609 | ud2 | |
610 | 1: | |
611 | #endif | |
502af0d7 | 612 | POP_REGS pop_rdi=0 |
3e3b9293 AL |
613 | |
614 | /* | |
615 | * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. | |
616 | * Save old stack pointer and switch to trampoline stack. | |
617 | */ | |
618 | movq %rsp, %rdi | |
c482feef | 619 | movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp |
3e3b9293 AL |
620 | |
621 | /* Copy the IRET frame to the trampoline stack. */ | |
622 | pushq 6*8(%rdi) /* SS */ | |
623 | pushq 5*8(%rdi) /* RSP */ | |
624 | pushq 4*8(%rdi) /* EFLAGS */ | |
625 | pushq 3*8(%rdi) /* CS */ | |
626 | pushq 2*8(%rdi) /* RIP */ | |
627 | ||
628 | /* Push user RDI on the trampoline stack. */ | |
629 | pushq (%rdi) | |
630 | ||
631 | /* | |
632 | * We are on the trampoline stack. All regs except RDI are live. | |
633 | * We can do future final exit work right here. | |
634 | */ | |
afaef01c | 635 | STACKLEAK_ERASE_NOCLOBBER |
3e3b9293 | 636 | |
6fd166aa | 637 | SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi |
8a09317b | 638 | |
3e3b9293 AL |
639 | /* Restore RDI. */ |
640 | popq %rdi | |
641 | SWAPGS | |
26c4ef9c AL |
642 | INTERRUPT_RETURN |
643 | ||
2601e64d | 644 | |
627276cb | 645 | /* Returning to kernel space */ |
6ba71b76 | 646 | retint_kernel: |
627276cb DV |
647 | #ifdef CONFIG_PREEMPT |
648 | /* Interrupts are off */ | |
649 | /* Check if we need preemption */ | |
6709812f | 650 | btl $9, EFLAGS(%rsp) /* were interrupts off? */ |
6ba71b76 | 651 | jnc 1f |
4d732138 | 652 | 0: cmpl $0, PER_CPU_VAR(__preempt_count) |
36acef25 | 653 | jnz 1f |
627276cb | 654 | call preempt_schedule_irq |
36acef25 | 655 | jmp 0b |
6ba71b76 | 656 | 1: |
627276cb | 657 | #endif |
2601e64d IM |
658 | /* |
659 | * The iretq could re-enable interrupts: | |
660 | */ | |
661 | TRACE_IRQS_IRETQ | |
fffbb5dc | 662 | |
26c4ef9c AL |
663 | GLOBAL(restore_regs_and_return_to_kernel) |
664 | #ifdef CONFIG_DEBUG_ENTRY | |
665 | /* Assert that pt_regs indicates kernel mode. */ | |
1e4c4f61 | 666 | testb $3, CS(%rsp) |
26c4ef9c AL |
667 | jz 1f |
668 | ud2 | |
669 | 1: | |
670 | #endif | |
502af0d7 | 671 | POP_REGS |
e872045b | 672 | addq $8, %rsp /* skip regs->orig_ax */ |
10bcc80e MD |
673 | /* |
674 | * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization | |
675 | * when returning from IPI handler. | |
676 | */ | |
7209a75d AL |
677 | INTERRUPT_RETURN |
678 | ||
679 | ENTRY(native_iret) | |
8c1f7558 | 680 | UNWIND_HINT_IRET_REGS |
3891a04a PA |
681 | /* |
682 | * Are we returning to a stack segment from the LDT? Note: in | |
683 | * 64-bit mode SS:RSP on the exception stack is always valid. | |
684 | */ | |
34273f41 | 685 | #ifdef CONFIG_X86_ESPFIX64 |
4d732138 IM |
686 | testb $4, (SS-RIP)(%rsp) |
687 | jnz native_irq_return_ldt | |
34273f41 | 688 | #endif |
3891a04a | 689 | |
af726f21 | 690 | .global native_irq_return_iret |
7209a75d | 691 | native_irq_return_iret: |
b645af2d AL |
692 | /* |
693 | * This may fault. Non-paranoid faults on return to userspace are | |
694 | * handled by fixup_bad_iret. These include #SS, #GP, and #NP. | |
695 | * Double-faults due to espfix64 are handled in do_double_fault. | |
696 | * Other faults here are fatal. | |
697 | */ | |
1da177e4 | 698 | iretq |
3701d863 | 699 | |
34273f41 | 700 | #ifdef CONFIG_X86_ESPFIX64 |
7209a75d | 701 | native_irq_return_ldt: |
85063fac AL |
702 | /* |
703 | * We are running with user GSBASE. All GPRs contain their user | |
704 | * values. We have a percpu ESPFIX stack that is eight slots | |
705 | * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom | |
706 | * of the ESPFIX stack. | |
707 | * | |
708 | * We clobber RAX and RDI in this code. We stash RDI on the | |
709 | * normal stack and RAX on the ESPFIX stack. | |
710 | * | |
711 | * The ESPFIX stack layout we set up looks like this: | |
712 | * | |
713 | * --- top of ESPFIX stack --- | |
714 | * SS | |
715 | * RSP | |
716 | * RFLAGS | |
717 | * CS | |
718 | * RIP <-- RSP points here when we're done | |
719 | * RAX <-- espfix_waddr points here | |
720 | * --- bottom of ESPFIX stack --- | |
721 | */ | |
722 | ||
723 | pushq %rdi /* Stash user RDI */ | |
8a09317b DH |
724 | SWAPGS /* to kernel GS */ |
725 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ | |
726 | ||
4d732138 | 727 | movq PER_CPU_VAR(espfix_waddr), %rdi |
85063fac AL |
728 | movq %rax, (0*8)(%rdi) /* user RAX */ |
729 | movq (1*8)(%rsp), %rax /* user RIP */ | |
4d732138 | 730 | movq %rax, (1*8)(%rdi) |
85063fac | 731 | movq (2*8)(%rsp), %rax /* user CS */ |
4d732138 | 732 | movq %rax, (2*8)(%rdi) |
85063fac | 733 | movq (3*8)(%rsp), %rax /* user RFLAGS */ |
4d732138 | 734 | movq %rax, (3*8)(%rdi) |
85063fac | 735 | movq (5*8)(%rsp), %rax /* user SS */ |
4d732138 | 736 | movq %rax, (5*8)(%rdi) |
85063fac | 737 | movq (4*8)(%rsp), %rax /* user RSP */ |
4d732138 | 738 | movq %rax, (4*8)(%rdi) |
85063fac AL |
739 | /* Now RAX == RSP. */ |
740 | ||
741 | andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ | |
85063fac AL |
742 | |
743 | /* | |
744 | * espfix_stack[31:16] == 0. The page tables are set up such that | |
745 | * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of | |
746 | * espfix_waddr for any X. That is, there are 65536 RO aliases of | |
747 | * the same page. Set up RSP so that RSP[31:16] contains the | |
748 | * respective 16 bits of the /userspace/ RSP and RSP nonetheless | |
749 | * still points to an RO alias of the ESPFIX stack. | |
750 | */ | |
4d732138 | 751 | orq PER_CPU_VAR(espfix_stack), %rax |
8a09317b | 752 | |
6fd166aa | 753 | SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi |
8a09317b DH |
754 | SWAPGS /* to user GS */ |
755 | popq %rdi /* Restore user RDI */ | |
756 | ||
4d732138 | 757 | movq %rax, %rsp |
8c1f7558 | 758 | UNWIND_HINT_IRET_REGS offset=8 |
85063fac AL |
759 | |
760 | /* | |
761 | * At this point, we cannot write to the stack any more, but we can | |
762 | * still read. | |
763 | */ | |
764 | popq %rax /* Restore user RAX */ | |
765 | ||
766 | /* | |
767 | * RSP now points to an ordinary IRET frame, except that the page | |
768 | * is read-only and RSP[31:16] are preloaded with the userspace | |
769 | * values. We can now IRET back to userspace. | |
770 | */ | |
4d732138 | 771 | jmp native_irq_return_iret |
34273f41 | 772 | #endif |
4b787e0b | 773 | END(common_interrupt) |
a50480cb | 774 | _ASM_NOKPROBE(common_interrupt) |
3891a04a | 775 | |
1da177e4 LT |
776 | /* |
777 | * APIC interrupts. | |
0bd7b798 | 778 | */ |
cf910e83 | 779 | .macro apicinterrupt3 num sym do_sym |
322648d1 | 780 | ENTRY(\sym) |
8c1f7558 | 781 | UNWIND_HINT_IRET_REGS |
4d732138 | 782 | pushq $~(\num) |
39e95433 | 783 | .Lcommon_\sym: |
3aa99fc3 DB |
784 | call interrupt_entry |
785 | UNWIND_HINT_REGS indirect=1 | |
786 | call \do_sym /* rdi points to pt_regs */ | |
4d732138 | 787 | jmp ret_from_intr |
322648d1 | 788 | END(\sym) |
a50480cb | 789 | _ASM_NOKPROBE(\sym) |
322648d1 | 790 | .endm |
1da177e4 | 791 | |
469f0023 | 792 | /* Make sure APIC interrupt handlers end up in the irqentry section: */ |
229a7186 MH |
793 | #define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" |
794 | #define POP_SECTION_IRQENTRY .popsection | |
469f0023 | 795 | |
cf910e83 | 796 | .macro apicinterrupt num sym do_sym |
469f0023 | 797 | PUSH_SECTION_IRQENTRY |
cf910e83 | 798 | apicinterrupt3 \num \sym \do_sym |
469f0023 | 799 | POP_SECTION_IRQENTRY |
cf910e83 SA |
800 | .endm |
801 | ||
322648d1 | 802 | #ifdef CONFIG_SMP |
4d732138 IM |
803 | apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt |
804 | apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt | |
322648d1 | 805 | #endif |
1da177e4 | 806 | |
03b48632 | 807 | #ifdef CONFIG_X86_UV |
4d732138 | 808 | apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt |
03b48632 | 809 | #endif |
4d732138 IM |
810 | |
811 | apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt | |
812 | apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi | |
89b831ef | 813 | |
d78f2664 | 814 | #ifdef CONFIG_HAVE_KVM |
4d732138 IM |
815 | apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi |
816 | apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi | |
210f84b0 | 817 | apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi |
d78f2664 YZ |
818 | #endif |
819 | ||
33e5ff63 | 820 | #ifdef CONFIG_X86_MCE_THRESHOLD |
4d732138 | 821 | apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt |
33e5ff63 SA |
822 | #endif |
823 | ||
24fd78a8 | 824 | #ifdef CONFIG_X86_MCE_AMD |
4d732138 | 825 | apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt |
24fd78a8 AG |
826 | #endif |
827 | ||
33e5ff63 | 828 | #ifdef CONFIG_X86_THERMAL_VECTOR |
4d732138 | 829 | apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt |
33e5ff63 | 830 | #endif |
1812924b | 831 | |
322648d1 | 832 | #ifdef CONFIG_SMP |
4d732138 IM |
833 | apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt |
834 | apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt | |
835 | apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt | |
322648d1 | 836 | #endif |
1da177e4 | 837 | |
4d732138 IM |
838 | apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt |
839 | apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt | |
0bd7b798 | 840 | |
e360adbe | 841 | #ifdef CONFIG_IRQ_WORK |
4d732138 | 842 | apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt |
241771ef IM |
843 | #endif |
844 | ||
1da177e4 LT |
845 | /* |
846 | * Exception entry points. | |
0bd7b798 | 847 | */ |
c482feef | 848 | #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8) |
577ed45e | 849 | |
bd7b1f7c AL |
850 | /** |
851 | * idtentry - Generate an IDT entry stub | |
852 | * @sym: Name of the generated entry point | |
853 | * @do_sym: C function to be called | |
854 | * @has_error_code: True if this IDT vector has an error code on the stack | |
855 | * @paranoid: non-zero means that this vector may be invoked from | |
856 | * kernel mode with user GSBASE and/or user CR3. | |
857 | * 2 is special -- see below. | |
858 | * @shift_ist: Set to an IST index if entries from kernel mode should | |
859 | * decrement the IST stack so that nested entries get a | |
860 | * fresh stack. (This is for #DB, which has a nasty habit | |
861 | * of recursing.) | |
862 | * | |
863 | * idtentry generates an IDT stub that sets up a usable kernel context, | |
864 | * creates struct pt_regs, and calls @do_sym. The stub has the following | |
865 | * special behaviors: | |
866 | * | |
867 | * On an entry from user mode, the stub switches from the trampoline or | |
868 | * IST stack to the normal thread stack. On an exit to user mode, the | |
869 | * normal exit-to-usermode path is invoked. | |
870 | * | |
871 | * On an exit to kernel mode, if @paranoid == 0, we check for preemption, | |
872 | * whereas we omit the preemption check if @paranoid != 0. This is purely | |
873 | * because the implementation is simpler this way. The kernel only needs | |
874 | * to check for asynchronous kernel preemption when IRQ handlers return. | |
875 | * | |
876 | * If @paranoid == 0, then the stub will handle IRET faults by pretending | |
877 | * that the fault came from user mode. It will handle gs_change faults by | |
878 | * pretending that the fault happened with kernel GSBASE. Since this handling | |
879 | * is omitted for @paranoid != 0, the #GP, #SS, and #NP stubs must have | |
880 | * @paranoid == 0. This special handling will do the wrong thing for | |
881 | * espfix-induced #DF on IRET, so #DF must not use @paranoid == 0. | |
882 | * | |
883 | * @paranoid == 2 is special: the stub will never switch stacks. This is for | |
884 | * #DF: if the thread stack is somehow unusable, we'll still get a useful OOPS. | |
885 | */ | |
aec40798 | 886 | .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 create_gap=0 |
322648d1 | 887 | ENTRY(\sym) |
98990a33 | 888 | UNWIND_HINT_IRET_REGS offset=\has_error_code*8 |
8c1f7558 | 889 | |
577ed45e AL |
890 | /* Sanity check */ |
891 | .if \shift_ist != -1 && \paranoid == 0 | |
892 | .error "using shift_ist requires paranoid=1" | |
893 | .endif | |
894 | ||
ee4eb87b | 895 | ASM_CLAC |
cb5dd2c5 | 896 | |
82c62fa0 | 897 | .if \has_error_code == 0 |
4d732138 | 898 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
cb5dd2c5 AL |
899 | .endif |
900 | ||
071ccc96 | 901 | .if \paranoid == 1 |
9e809d15 | 902 | testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */ |
7f2590a1 | 903 | jnz .Lfrom_usermode_switch_stack_\@ |
48e08d0f | 904 | .endif |
7f2590a1 | 905 | |
aec40798 JP |
906 | .if \create_gap == 1 |
907 | /* | |
908 | * If coming from kernel space, create a 6-word gap to allow the | |
909 | * int3 handler to emulate a call instruction. | |
910 | */ | |
911 | testb $3, CS-ORIG_RAX(%rsp) | |
912 | jnz .Lfrom_usermode_no_gap_\@ | |
913 | .rept 6 | |
914 | pushq 5*8(%rsp) | |
915 | .endr | |
916 | UNWIND_HINT_IRET_REGS offset=8 | |
917 | .Lfrom_usermode_no_gap_\@: | |
918 | .endif | |
919 | ||
7f2590a1 | 920 | .if \paranoid |
4d732138 | 921 | call paranoid_entry |
cb5dd2c5 | 922 | .else |
4d732138 | 923 | call error_entry |
cb5dd2c5 | 924 | .endif |
8c1f7558 | 925 | UNWIND_HINT_REGS |
ebfc453e | 926 | /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ |
cb5dd2c5 | 927 | |
cb5dd2c5 | 928 | .if \paranoid |
577ed45e | 929 | .if \shift_ist != -1 |
4d732138 | 930 | TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ |
577ed45e | 931 | .else |
b8b1d08b | 932 | TRACE_IRQS_OFF |
cb5dd2c5 | 933 | .endif |
577ed45e | 934 | .endif |
cb5dd2c5 | 935 | |
4d732138 | 936 | movq %rsp, %rdi /* pt_regs pointer */ |
cb5dd2c5 AL |
937 | |
938 | .if \has_error_code | |
4d732138 IM |
939 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
940 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
cb5dd2c5 | 941 | .else |
4d732138 | 942 | xorl %esi, %esi /* no error code */ |
cb5dd2c5 AL |
943 | .endif |
944 | ||
577ed45e | 945 | .if \shift_ist != -1 |
4d732138 | 946 | subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
947 | .endif |
948 | ||
4d732138 | 949 | call \do_sym |
cb5dd2c5 | 950 | |
577ed45e | 951 | .if \shift_ist != -1 |
4d732138 | 952 | addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
953 | .endif |
954 | ||
ebfc453e | 955 | /* these procedures expect "no swapgs" flag in ebx */ |
cb5dd2c5 | 956 | .if \paranoid |
4d732138 | 957 | jmp paranoid_exit |
cb5dd2c5 | 958 | .else |
4d732138 | 959 | jmp error_exit |
cb5dd2c5 AL |
960 | .endif |
961 | ||
071ccc96 | 962 | .if \paranoid == 1 |
48e08d0f | 963 | /* |
7f2590a1 | 964 | * Entry from userspace. Switch stacks and treat it |
48e08d0f AL |
965 | * as a normal entry. This means that paranoid handlers |
966 | * run in real process context if user_mode(regs). | |
967 | */ | |
7f2590a1 | 968 | .Lfrom_usermode_switch_stack_\@: |
4d732138 | 969 | call error_entry |
48e08d0f | 970 | |
4d732138 | 971 | movq %rsp, %rdi /* pt_regs pointer */ |
48e08d0f AL |
972 | |
973 | .if \has_error_code | |
4d732138 IM |
974 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
975 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
48e08d0f | 976 | .else |
4d732138 | 977 | xorl %esi, %esi /* no error code */ |
48e08d0f AL |
978 | .endif |
979 | ||
4d732138 | 980 | call \do_sym |
48e08d0f | 981 | |
b3681dd5 | 982 | jmp error_exit |
48e08d0f | 983 | .endif |
a50480cb | 984 | _ASM_NOKPROBE(\sym) |
ddeb8f21 | 985 | END(\sym) |
322648d1 | 986 | .endm |
b8b1d08b | 987 | |
4d732138 IM |
988 | idtentry divide_error do_divide_error has_error_code=0 |
989 | idtentry overflow do_overflow has_error_code=0 | |
990 | idtentry bounds do_bounds has_error_code=0 | |
991 | idtentry invalid_op do_invalid_op has_error_code=0 | |
992 | idtentry device_not_available do_device_not_available has_error_code=0 | |
993 | idtentry double_fault do_double_fault has_error_code=1 paranoid=2 | |
994 | idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 | |
995 | idtentry invalid_TSS do_invalid_TSS has_error_code=1 | |
996 | idtentry segment_not_present do_segment_not_present has_error_code=1 | |
997 | idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 | |
998 | idtentry coprocessor_error do_coprocessor_error has_error_code=0 | |
999 | idtentry alignment_check do_alignment_check has_error_code=1 | |
1000 | idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 | |
1001 | ||
1002 | ||
1003 | /* | |
1004 | * Reload gs selector with exception handling | |
1005 | * edi: new selector | |
1006 | */ | |
9f9d489a | 1007 | ENTRY(native_load_gs_index) |
8c1f7558 | 1008 | FRAME_BEGIN |
131484c8 | 1009 | pushfq |
b8aa287f | 1010 | DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) |
ca37e57b | 1011 | TRACE_IRQS_OFF |
9f1e87ea | 1012 | SWAPGS |
42c748bb | 1013 | .Lgs_change: |
4d732138 | 1014 | movl %edi, %gs |
96e5d28a | 1015 | 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE |
72fe4858 | 1016 | SWAPGS |
ca37e57b | 1017 | TRACE_IRQS_FLAGS (%rsp) |
131484c8 | 1018 | popfq |
8c1f7558 | 1019 | FRAME_END |
9f1e87ea | 1020 | ret |
8c1f7558 | 1021 | ENDPROC(native_load_gs_index) |
784d5699 | 1022 | EXPORT_SYMBOL(native_load_gs_index) |
0bd7b798 | 1023 | |
42c748bb | 1024 | _ASM_EXTABLE(.Lgs_change, bad_gs) |
4d732138 | 1025 | .section .fixup, "ax" |
1da177e4 | 1026 | /* running with kernelgs */ |
0bd7b798 | 1027 | bad_gs: |
4d732138 | 1028 | SWAPGS /* switch back to user gs */ |
b038c842 AL |
1029 | .macro ZAP_GS |
1030 | /* This can't be a string because the preprocessor needs to see it. */ | |
1031 | movl $__USER_DS, %eax | |
1032 | movl %eax, %gs | |
1033 | .endm | |
1034 | ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG | |
4d732138 IM |
1035 | xorl %eax, %eax |
1036 | movl %eax, %gs | |
1037 | jmp 2b | |
9f1e87ea | 1038 | .previous |
0bd7b798 | 1039 | |
2699500b | 1040 | /* Call softirq on interrupt stack. Interrupts are off. */ |
7d65f4a6 | 1041 | ENTRY(do_softirq_own_stack) |
4d732138 IM |
1042 | pushq %rbp |
1043 | mov %rsp, %rbp | |
8c1f7558 | 1044 | ENTER_IRQ_STACK regs=0 old_rsp=%r11 |
4d732138 | 1045 | call __do_softirq |
8c1f7558 | 1046 | LEAVE_IRQ_STACK regs=0 |
2699500b | 1047 | leaveq |
ed6b676c | 1048 | ret |
8c1f7558 | 1049 | ENDPROC(do_softirq_own_stack) |
75154f40 | 1050 | |
28c11b0f | 1051 | #ifdef CONFIG_XEN_PV |
5878d5d6 | 1052 | idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0 |
3d75e1b8 JF |
1053 | |
1054 | /* | |
9f1e87ea CG |
1055 | * A note on the "critical region" in our callback handler. |
1056 | * We want to avoid stacking callback handlers due to events occurring | |
1057 | * during handling of the last event. To do this, we keep events disabled | |
1058 | * until we've done all processing. HOWEVER, we must enable events before | |
1059 | * popping the stack frame (can't be done atomically) and so it would still | |
1060 | * be possible to get enough handler activations to overflow the stack. | |
1061 | * Although unlikely, bugs of that kind are hard to track down, so we'd | |
1062 | * like to avoid the possibility. | |
1063 | * So, on entry to the handler we detect whether we interrupted an | |
1064 | * existing activation in its critical region -- if so, we pop the current | |
1065 | * activation and restart the handler using the previous one. | |
1066 | */ | |
4d732138 IM |
1067 | ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ |
1068 | ||
9f1e87ea CG |
1069 | /* |
1070 | * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will | |
1071 | * see the correct pointer to the pt_regs | |
1072 | */ | |
8c1f7558 | 1073 | UNWIND_HINT_FUNC |
4d732138 | 1074 | movq %rdi, %rsp /* we don't return, adjust the stack frame */ |
8c1f7558 | 1075 | UNWIND_HINT_REGS |
1d3e53e8 AL |
1076 | |
1077 | ENTER_IRQ_STACK old_rsp=%r10 | |
4d732138 | 1078 | call xen_evtchn_do_upcall |
1d3e53e8 AL |
1079 | LEAVE_IRQ_STACK |
1080 | ||
fdfd811d | 1081 | #ifndef CONFIG_PREEMPT |
4d732138 | 1082 | call xen_maybe_preempt_hcall |
fdfd811d | 1083 | #endif |
4d732138 | 1084 | jmp error_exit |
371c394a | 1085 | END(xen_do_hypervisor_callback) |
3d75e1b8 JF |
1086 | |
1087 | /* | |
9f1e87ea CG |
1088 | * Hypervisor uses this for application faults while it executes. |
1089 | * We get here for two reasons: | |
1090 | * 1. Fault while reloading DS, ES, FS or GS | |
1091 | * 2. Fault while executing IRET | |
1092 | * Category 1 we do not need to fix up as Xen has already reloaded all segment | |
1093 | * registers that could be reloaded and zeroed the others. | |
1094 | * Category 2 we fix up by killing the current process. We cannot use the | |
1095 | * normal Linux return path in this case because if we use the IRET hypercall | |
1096 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
1097 | * We distinguish between categories by comparing each saved segment register | |
1098 | * with its current contents: any discrepancy means we in category 1. | |
1099 | */ | |
3d75e1b8 | 1100 | ENTRY(xen_failsafe_callback) |
8c1f7558 | 1101 | UNWIND_HINT_EMPTY |
4d732138 IM |
1102 | movl %ds, %ecx |
1103 | cmpw %cx, 0x10(%rsp) | |
1104 | jne 1f | |
1105 | movl %es, %ecx | |
1106 | cmpw %cx, 0x18(%rsp) | |
1107 | jne 1f | |
1108 | movl %fs, %ecx | |
1109 | cmpw %cx, 0x20(%rsp) | |
1110 | jne 1f | |
1111 | movl %gs, %ecx | |
1112 | cmpw %cx, 0x28(%rsp) | |
1113 | jne 1f | |
3d75e1b8 | 1114 | /* All segments match their saved values => Category 2 (Bad IRET). */ |
4d732138 IM |
1115 | movq (%rsp), %rcx |
1116 | movq 8(%rsp), %r11 | |
1117 | addq $0x30, %rsp | |
1118 | pushq $0 /* RIP */ | |
8c1f7558 | 1119 | UNWIND_HINT_IRET_REGS offset=8 |
4d732138 | 1120 | jmp general_protection |
3d75e1b8 | 1121 | 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ |
4d732138 IM |
1122 | movq (%rsp), %rcx |
1123 | movq 8(%rsp), %r11 | |
1124 | addq $0x30, %rsp | |
8c1f7558 | 1125 | UNWIND_HINT_IRET_REGS |
4d732138 | 1126 | pushq $-1 /* orig_ax = -1 => not a system call */ |
3f01daec | 1127 | PUSH_AND_CLEAR_REGS |
946c1911 | 1128 | ENCODE_FRAME_POINTER |
4d732138 | 1129 | jmp error_exit |
3d75e1b8 | 1130 | END(xen_failsafe_callback) |
28c11b0f | 1131 | #endif /* CONFIG_XEN_PV */ |
3d75e1b8 | 1132 | |
28c11b0f | 1133 | #ifdef CONFIG_XEN_PVHVM |
cf910e83 | 1134 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
38e20b07 | 1135 | xen_hvm_callback_vector xen_evtchn_do_upcall |
28c11b0f | 1136 | #endif |
38e20b07 | 1137 | |
ddeb8f21 | 1138 | |
bc2b0331 | 1139 | #if IS_ENABLED(CONFIG_HYPERV) |
cf910e83 | 1140 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
bc2b0331 | 1141 | hyperv_callback_vector hyperv_vector_handler |
93286261 VK |
1142 | |
1143 | apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \ | |
1144 | hyperv_reenlightenment_vector hyperv_reenlightenment_intr | |
248e742a MK |
1145 | |
1146 | apicinterrupt3 HYPERV_STIMER0_VECTOR \ | |
1147 | hv_stimer0_callback_vector hv_stimer0_vector_handler | |
bc2b0331 S |
1148 | #endif /* CONFIG_HYPERV */ |
1149 | ||
4d732138 | 1150 | idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK |
aec40798 | 1151 | idtentry int3 do_int3 has_error_code=0 create_gap=1 |
4d732138 IM |
1152 | idtentry stack_segment do_stack_segment has_error_code=1 |
1153 | ||
28c11b0f | 1154 | #ifdef CONFIG_XEN_PV |
43e41110 | 1155 | idtentry xennmi do_nmi has_error_code=0 |
5878d5d6 JG |
1156 | idtentry xendebug do_debug has_error_code=0 |
1157 | idtentry xenint3 do_int3 has_error_code=0 | |
6cac5a92 | 1158 | #endif |
4d732138 IM |
1159 | |
1160 | idtentry general_protection do_general_protection has_error_code=1 | |
11a7ffb0 | 1161 | idtentry page_fault do_page_fault has_error_code=1 |
4d732138 | 1162 | |
631bc487 | 1163 | #ifdef CONFIG_KVM_GUEST |
4d732138 | 1164 | idtentry async_page_fault do_async_page_fault has_error_code=1 |
631bc487 | 1165 | #endif |
4d732138 | 1166 | |
ddeb8f21 | 1167 | #ifdef CONFIG_X86_MCE |
6f41c34d | 1168 | idtentry machine_check do_mce has_error_code=0 paranoid=1 |
ddeb8f21 AH |
1169 | #endif |
1170 | ||
ebfc453e | 1171 | /* |
9e809d15 | 1172 | * Save all registers in pt_regs, and switch gs if needed. |
ebfc453e DV |
1173 | * Use slow, but surefire "are we in kernel?" check. |
1174 | * Return: ebx=0: need swapgs on exit, ebx=1: otherwise | |
1175 | */ | |
1176 | ENTRY(paranoid_entry) | |
8c1f7558 | 1177 | UNWIND_HINT_FUNC |
1eeb207f | 1178 | cld |
9e809d15 DB |
1179 | PUSH_AND_CLEAR_REGS save_ret=1 |
1180 | ENCODE_FRAME_POINTER 8 | |
4d732138 IM |
1181 | movl $1, %ebx |
1182 | movl $MSR_GS_BASE, %ecx | |
1eeb207f | 1183 | rdmsr |
4d732138 IM |
1184 | testl %edx, %edx |
1185 | js 1f /* negative -> in kernel */ | |
1eeb207f | 1186 | SWAPGS |
4d732138 | 1187 | xorl %ebx, %ebx |
8a09317b DH |
1188 | |
1189 | 1: | |
16561f27 DH |
1190 | /* |
1191 | * Always stash CR3 in %r14. This value will be restored, | |
ae852495 AL |
1192 | * verbatim, at exit. Needed if paranoid_entry interrupted |
1193 | * another entry that already switched to the user CR3 value | |
1194 | * but has not yet returned to userspace. | |
16561f27 DH |
1195 | * |
1196 | * This is also why CS (stashed in the "iret frame" by the | |
1197 | * hardware at entry) can not be used: this may be a return | |
ae852495 | 1198 | * to kernel code, but with a user CR3 value. |
16561f27 | 1199 | */ |
8a09317b DH |
1200 | SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 |
1201 | ||
1b4e3ce4 JP |
1202 | /* |
1203 | * The above SAVE_AND_SWITCH_TO_KERNEL_CR3 macro doesn't do an | |
1204 | * unconditional CR3 write, even in the PTI case. So do an lfence | |
1205 | * to prevent GS speculation, regardless of whether PTI is enabled. | |
1206 | */ | |
1207 | FENCE_SWAPGS_KERNEL_ENTRY | |
1208 | ||
8a09317b | 1209 | ret |
ebfc453e | 1210 | END(paranoid_entry) |
ddeb8f21 | 1211 | |
ebfc453e DV |
1212 | /* |
1213 | * "Paranoid" exit path from exception stack. This is invoked | |
1214 | * only on return from non-NMI IST interrupts that came | |
1215 | * from kernel space. | |
1216 | * | |
1217 | * We may be returning to very strange contexts (e.g. very early | |
1218 | * in syscall entry), so checking for preemption here would | |
1219 | * be complicated. Fortunately, we there's no good reason | |
1220 | * to try to handle preemption here. | |
4d732138 IM |
1221 | * |
1222 | * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) | |
ebfc453e | 1223 | */ |
ddeb8f21 | 1224 | ENTRY(paranoid_exit) |
8c1f7558 | 1225 | UNWIND_HINT_REGS |
2140a994 | 1226 | DISABLE_INTERRUPTS(CLBR_ANY) |
5963e317 | 1227 | TRACE_IRQS_OFF_DEBUG |
4d732138 | 1228 | testl %ebx, %ebx /* swapgs needed? */ |
e5317832 | 1229 | jnz .Lparanoid_exit_no_swapgs |
f2db9382 | 1230 | TRACE_IRQS_IRETQ |
16561f27 | 1231 | /* Always restore stashed CR3 value (see paranoid_entry) */ |
21e94459 | 1232 | RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 |
ddeb8f21 | 1233 | SWAPGS_UNSAFE_STACK |
e5317832 AL |
1234 | jmp .Lparanoid_exit_restore |
1235 | .Lparanoid_exit_no_swapgs: | |
f2db9382 | 1236 | TRACE_IRQS_IRETQ_DEBUG |
16561f27 | 1237 | /* Always restore stashed CR3 value (see paranoid_entry) */ |
e4865757 | 1238 | RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 |
e5317832 AL |
1239 | .Lparanoid_exit_restore: |
1240 | jmp restore_regs_and_return_to_kernel | |
ddeb8f21 AH |
1241 | END(paranoid_exit) |
1242 | ||
1243 | /* | |
9e809d15 | 1244 | * Save all registers in pt_regs, and switch GS if needed. |
ddeb8f21 AH |
1245 | */ |
1246 | ENTRY(error_entry) | |
9e809d15 | 1247 | UNWIND_HINT_FUNC |
ddeb8f21 | 1248 | cld |
9e809d15 DB |
1249 | PUSH_AND_CLEAR_REGS save_ret=1 |
1250 | ENCODE_FRAME_POINTER 8 | |
03335e95 | 1251 | testb $3, CS+8(%rsp) |
cb6f64ed | 1252 | jz .Lerror_kernelspace |
539f5113 | 1253 | |
cb6f64ed AL |
1254 | /* |
1255 | * We entered from user mode or we're pretending to have entered | |
1256 | * from user mode due to an IRET fault. | |
1257 | */ | |
ddeb8f21 | 1258 | SWAPGS |
1b4e3ce4 | 1259 | FENCE_SWAPGS_USER_ENTRY |
8a09317b DH |
1260 | /* We have user CR3. Change to kernel CR3. */ |
1261 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax | |
539f5113 | 1262 | |
cb6f64ed | 1263 | .Lerror_entry_from_usermode_after_swapgs: |
7f2590a1 AL |
1264 | /* Put us onto the real thread stack. */ |
1265 | popq %r12 /* save return addr in %12 */ | |
1266 | movq %rsp, %rdi /* arg0 = pt_regs pointer */ | |
1267 | call sync_regs | |
1268 | movq %rax, %rsp /* switch stack */ | |
1269 | ENCODE_FRAME_POINTER | |
1270 | pushq %r12 | |
1271 | ||
f1075053 AL |
1272 | /* |
1273 | * We need to tell lockdep that IRQs are off. We can't do this until | |
1274 | * we fix gsbase, and we should do it before enter_from_user_mode | |
1275 | * (which can take locks). | |
1276 | */ | |
1277 | TRACE_IRQS_OFF | |
478dc89c | 1278 | CALL_enter_from_user_mode |
f1075053 | 1279 | ret |
02bc7768 | 1280 | |
1b4e3ce4 JP |
1281 | .Lerror_entry_done_lfence: |
1282 | FENCE_SWAPGS_KERNEL_ENTRY | |
cb6f64ed | 1283 | .Lerror_entry_done: |
ddeb8f21 AH |
1284 | TRACE_IRQS_OFF |
1285 | ret | |
ddeb8f21 | 1286 | |
ebfc453e DV |
1287 | /* |
1288 | * There are two places in the kernel that can potentially fault with | |
1289 | * usergs. Handle them here. B stepping K8s sometimes report a | |
1290 | * truncated RIP for IRET exceptions returning to compat mode. Check | |
1291 | * for these here too. | |
1292 | */ | |
cb6f64ed | 1293 | .Lerror_kernelspace: |
4d732138 IM |
1294 | leaq native_irq_return_iret(%rip), %rcx |
1295 | cmpq %rcx, RIP+8(%rsp) | |
cb6f64ed | 1296 | je .Lerror_bad_iret |
4d732138 IM |
1297 | movl %ecx, %eax /* zero extend */ |
1298 | cmpq %rax, RIP+8(%rsp) | |
cb6f64ed | 1299 | je .Lbstep_iret |
42c748bb | 1300 | cmpq $.Lgs_change, RIP+8(%rsp) |
1b4e3ce4 | 1301 | jne .Lerror_entry_done_lfence |
539f5113 AL |
1302 | |
1303 | /* | |
42c748bb | 1304 | * hack: .Lgs_change can fail with user gsbase. If this happens, fix up |
539f5113 | 1305 | * gsbase and proceed. We'll fix up the exception and land in |
42c748bb | 1306 | * .Lgs_change's error handler with kernel gsbase. |
539f5113 | 1307 | */ |
2fa5f04f | 1308 | SWAPGS |
1b4e3ce4 | 1309 | FENCE_SWAPGS_USER_ENTRY |
8a09317b | 1310 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax |
2fa5f04f | 1311 | jmp .Lerror_entry_done |
ae24ffe5 | 1312 | |
cb6f64ed | 1313 | .Lbstep_iret: |
ae24ffe5 | 1314 | /* Fix truncated RIP */ |
4d732138 | 1315 | movq %rcx, RIP+8(%rsp) |
b645af2d AL |
1316 | /* fall through */ |
1317 | ||
cb6f64ed | 1318 | .Lerror_bad_iret: |
539f5113 | 1319 | /* |
8a09317b DH |
1320 | * We came from an IRET to user mode, so we have user |
1321 | * gsbase and CR3. Switch to kernel gsbase and CR3: | |
539f5113 | 1322 | */ |
b645af2d | 1323 | SWAPGS |
1b4e3ce4 | 1324 | FENCE_SWAPGS_USER_ENTRY |
8a09317b | 1325 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax |
539f5113 AL |
1326 | |
1327 | /* | |
1328 | * Pretend that the exception came from user mode: set up pt_regs | |
b3681dd5 | 1329 | * as if we faulted immediately after IRET. |
539f5113 | 1330 | */ |
4d732138 IM |
1331 | mov %rsp, %rdi |
1332 | call fixup_bad_iret | |
1333 | mov %rax, %rsp | |
cb6f64ed | 1334 | jmp .Lerror_entry_from_usermode_after_swapgs |
ddeb8f21 AH |
1335 | END(error_entry) |
1336 | ||
ddeb8f21 | 1337 | ENTRY(error_exit) |
8c1f7558 | 1338 | UNWIND_HINT_REGS |
2140a994 | 1339 | DISABLE_INTERRUPTS(CLBR_ANY) |
ddeb8f21 | 1340 | TRACE_IRQS_OFF |
b3681dd5 AL |
1341 | testb $3, CS(%rsp) |
1342 | jz retint_kernel | |
4d732138 | 1343 | jmp retint_user |
ddeb8f21 AH |
1344 | END(error_exit) |
1345 | ||
929bacec AL |
1346 | /* |
1347 | * Runs on exception stack. Xen PV does not go through this path at all, | |
1348 | * so we can use real assembly here. | |
8a09317b DH |
1349 | * |
1350 | * Registers: | |
1351 | * %r14: Used to save/restore the CR3 of the interrupted context | |
1352 | * when PAGE_TABLE_ISOLATION is in use. Do not clobber. | |
929bacec | 1353 | */ |
ddeb8f21 | 1354 | ENTRY(nmi) |
8c1f7558 | 1355 | UNWIND_HINT_IRET_REGS |
929bacec | 1356 | |
3f3c8b8c SR |
1357 | /* |
1358 | * We allow breakpoints in NMIs. If a breakpoint occurs, then | |
1359 | * the iretq it performs will take us out of NMI context. | |
1360 | * This means that we can have nested NMIs where the next | |
1361 | * NMI is using the top of the stack of the previous NMI. We | |
1362 | * can't let it execute because the nested NMI will corrupt the | |
1363 | * stack of the previous NMI. NMI handlers are not re-entrant | |
1364 | * anyway. | |
1365 | * | |
1366 | * To handle this case we do the following: | |
1367 | * Check the a special location on the stack that contains | |
1368 | * a variable that is set when NMIs are executing. | |
1369 | * The interrupted task's stack is also checked to see if it | |
1370 | * is an NMI stack. | |
1371 | * If the variable is not set and the stack is not the NMI | |
1372 | * stack then: | |
1373 | * o Set the special variable on the stack | |
0b22930e AL |
1374 | * o Copy the interrupt frame into an "outermost" location on the |
1375 | * stack | |
1376 | * o Copy the interrupt frame into an "iret" location on the stack | |
3f3c8b8c SR |
1377 | * o Continue processing the NMI |
1378 | * If the variable is set or the previous stack is the NMI stack: | |
0b22930e | 1379 | * o Modify the "iret" location to jump to the repeat_nmi |
3f3c8b8c SR |
1380 | * o return back to the first NMI |
1381 | * | |
1382 | * Now on exit of the first NMI, we first clear the stack variable | |
1383 | * The NMI stack will tell any nested NMIs at that point that it is | |
1384 | * nested. Then we pop the stack normally with iret, and if there was | |
1385 | * a nested NMI that updated the copy interrupt stack frame, a | |
1386 | * jump will be made to the repeat_nmi code that will handle the second | |
1387 | * NMI. | |
9b6e6a83 AL |
1388 | * |
1389 | * However, espfix prevents us from directly returning to userspace | |
1390 | * with a single IRET instruction. Similarly, IRET to user mode | |
1391 | * can fault. We therefore handle NMIs from user space like | |
1392 | * other IST entries. | |
3f3c8b8c SR |
1393 | */ |
1394 | ||
e93c1730 AL |
1395 | ASM_CLAC |
1396 | ||
146b2b09 | 1397 | /* Use %rdx as our temp variable throughout */ |
4d732138 | 1398 | pushq %rdx |
3f3c8b8c | 1399 | |
9b6e6a83 AL |
1400 | testb $3, CS-RIP+8(%rsp) |
1401 | jz .Lnmi_from_kernel | |
1402 | ||
1403 | /* | |
1404 | * NMI from user mode. We need to run on the thread stack, but we | |
1405 | * can't go through the normal entry paths: NMIs are masked, and | |
1406 | * we don't want to enable interrupts, because then we'll end | |
1407 | * up in an awkward situation in which IRQs are on but NMIs | |
1408 | * are off. | |
83c133cf AL |
1409 | * |
1410 | * We also must not push anything to the stack before switching | |
1411 | * stacks lest we corrupt the "NMI executing" variable. | |
9b6e6a83 AL |
1412 | */ |
1413 | ||
929bacec | 1414 | swapgs |
9b6e6a83 | 1415 | cld |
1b4e3ce4 | 1416 | FENCE_SWAPGS_USER_ENTRY |
8a09317b | 1417 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx |
9b6e6a83 AL |
1418 | movq %rsp, %rdx |
1419 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
8c1f7558 | 1420 | UNWIND_HINT_IRET_REGS base=%rdx offset=8 |
9b6e6a83 AL |
1421 | pushq 5*8(%rdx) /* pt_regs->ss */ |
1422 | pushq 4*8(%rdx) /* pt_regs->rsp */ | |
1423 | pushq 3*8(%rdx) /* pt_regs->flags */ | |
1424 | pushq 2*8(%rdx) /* pt_regs->cs */ | |
1425 | pushq 1*8(%rdx) /* pt_regs->rip */ | |
8c1f7558 | 1426 | UNWIND_HINT_IRET_REGS |
9b6e6a83 | 1427 | pushq $-1 /* pt_regs->orig_ax */ |
30907fd1 | 1428 | PUSH_AND_CLEAR_REGS rdx=(%rdx) |
946c1911 | 1429 | ENCODE_FRAME_POINTER |
9b6e6a83 AL |
1430 | |
1431 | /* | |
1432 | * At this point we no longer need to worry about stack damage | |
1433 | * due to nesting -- we're on the normal thread stack and we're | |
1434 | * done with the NMI stack. | |
1435 | */ | |
1436 | ||
1437 | movq %rsp, %rdi | |
1438 | movq $-1, %rsi | |
1439 | call do_nmi | |
1440 | ||
45d5a168 | 1441 | /* |
9b6e6a83 | 1442 | * Return back to user mode. We must *not* do the normal exit |
946c1911 | 1443 | * work, because we don't want to enable interrupts. |
45d5a168 | 1444 | */ |
8a055d7f | 1445 | jmp swapgs_restore_regs_and_return_to_usermode |
45d5a168 | 1446 | |
9b6e6a83 | 1447 | .Lnmi_from_kernel: |
3f3c8b8c | 1448 | /* |
0b22930e AL |
1449 | * Here's what our stack frame will look like: |
1450 | * +---------------------------------------------------------+ | |
1451 | * | original SS | | |
1452 | * | original Return RSP | | |
1453 | * | original RFLAGS | | |
1454 | * | original CS | | |
1455 | * | original RIP | | |
1456 | * +---------------------------------------------------------+ | |
1457 | * | temp storage for rdx | | |
1458 | * +---------------------------------------------------------+ | |
1459 | * | "NMI executing" variable | | |
1460 | * +---------------------------------------------------------+ | |
1461 | * | iret SS } Copied from "outermost" frame | | |
1462 | * | iret Return RSP } on each loop iteration; overwritten | | |
1463 | * | iret RFLAGS } by a nested NMI to force another | | |
1464 | * | iret CS } iteration if needed. | | |
1465 | * | iret RIP } | | |
1466 | * +---------------------------------------------------------+ | |
1467 | * | outermost SS } initialized in first_nmi; | | |
1468 | * | outermost Return RSP } will not be changed before | | |
1469 | * | outermost RFLAGS } NMI processing is done. | | |
1470 | * | outermost CS } Copied to "iret" frame on each | | |
1471 | * | outermost RIP } iteration. | | |
1472 | * +---------------------------------------------------------+ | |
1473 | * | pt_regs | | |
1474 | * +---------------------------------------------------------+ | |
1475 | * | |
1476 | * The "original" frame is used by hardware. Before re-enabling | |
1477 | * NMIs, we need to be done with it, and we need to leave enough | |
1478 | * space for the asm code here. | |
1479 | * | |
1480 | * We return by executing IRET while RSP points to the "iret" frame. | |
1481 | * That will either return for real or it will loop back into NMI | |
1482 | * processing. | |
1483 | * | |
1484 | * The "outermost" frame is copied to the "iret" frame on each | |
1485 | * iteration of the loop, so each iteration starts with the "iret" | |
1486 | * frame pointing to the final return target. | |
1487 | */ | |
1488 | ||
45d5a168 | 1489 | /* |
0b22930e AL |
1490 | * Determine whether we're a nested NMI. |
1491 | * | |
a27507ca AL |
1492 | * If we interrupted kernel code between repeat_nmi and |
1493 | * end_repeat_nmi, then we are a nested NMI. We must not | |
1494 | * modify the "iret" frame because it's being written by | |
1495 | * the outer NMI. That's okay; the outer NMI handler is | |
1496 | * about to about to call do_nmi anyway, so we can just | |
1497 | * resume the outer NMI. | |
45d5a168 | 1498 | */ |
a27507ca AL |
1499 | |
1500 | movq $repeat_nmi, %rdx | |
1501 | cmpq 8(%rsp), %rdx | |
1502 | ja 1f | |
1503 | movq $end_repeat_nmi, %rdx | |
1504 | cmpq 8(%rsp), %rdx | |
1505 | ja nested_nmi_out | |
1506 | 1: | |
45d5a168 | 1507 | |
3f3c8b8c | 1508 | /* |
a27507ca | 1509 | * Now check "NMI executing". If it's set, then we're nested. |
0b22930e AL |
1510 | * This will not detect if we interrupted an outer NMI just |
1511 | * before IRET. | |
3f3c8b8c | 1512 | */ |
4d732138 IM |
1513 | cmpl $1, -8(%rsp) |
1514 | je nested_nmi | |
3f3c8b8c SR |
1515 | |
1516 | /* | |
0b22930e AL |
1517 | * Now test if the previous stack was an NMI stack. This covers |
1518 | * the case where we interrupt an outer NMI after it clears | |
810bc075 AL |
1519 | * "NMI executing" but before IRET. We need to be careful, though: |
1520 | * there is one case in which RSP could point to the NMI stack | |
1521 | * despite there being no NMI active: naughty userspace controls | |
1522 | * RSP at the very beginning of the SYSCALL targets. We can | |
1523 | * pull a fast one on naughty userspace, though: we program | |
1524 | * SYSCALL to mask DF, so userspace cannot cause DF to be set | |
1525 | * if it controls the kernel's RSP. We set DF before we clear | |
1526 | * "NMI executing". | |
3f3c8b8c | 1527 | */ |
0784b364 DV |
1528 | lea 6*8(%rsp), %rdx |
1529 | /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ | |
1530 | cmpq %rdx, 4*8(%rsp) | |
1531 | /* If the stack pointer is above the NMI stack, this is a normal NMI */ | |
1532 | ja first_nmi | |
4d732138 | 1533 | |
0784b364 DV |
1534 | subq $EXCEPTION_STKSZ, %rdx |
1535 | cmpq %rdx, 4*8(%rsp) | |
1536 | /* If it is below the NMI stack, it is a normal NMI */ | |
1537 | jb first_nmi | |
810bc075 AL |
1538 | |
1539 | /* Ah, it is within the NMI stack. */ | |
1540 | ||
1541 | testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) | |
1542 | jz first_nmi /* RSP was user controlled. */ | |
1543 | ||
1544 | /* This is a nested NMI. */ | |
0784b364 | 1545 | |
3f3c8b8c SR |
1546 | nested_nmi: |
1547 | /* | |
0b22930e AL |
1548 | * Modify the "iret" frame to point to repeat_nmi, forcing another |
1549 | * iteration of NMI handling. | |
3f3c8b8c | 1550 | */ |
23a781e9 | 1551 | subq $8, %rsp |
4d732138 IM |
1552 | leaq -10*8(%rsp), %rdx |
1553 | pushq $__KERNEL_DS | |
1554 | pushq %rdx | |
131484c8 | 1555 | pushfq |
4d732138 IM |
1556 | pushq $__KERNEL_CS |
1557 | pushq $repeat_nmi | |
3f3c8b8c SR |
1558 | |
1559 | /* Put stack back */ | |
4d732138 | 1560 | addq $(6*8), %rsp |
3f3c8b8c SR |
1561 | |
1562 | nested_nmi_out: | |
4d732138 | 1563 | popq %rdx |
3f3c8b8c | 1564 | |
0b22930e | 1565 | /* We are returning to kernel mode, so this cannot result in a fault. */ |
929bacec | 1566 | iretq |
3f3c8b8c SR |
1567 | |
1568 | first_nmi: | |
0b22930e | 1569 | /* Restore rdx. */ |
4d732138 | 1570 | movq (%rsp), %rdx |
62610913 | 1571 | |
36f1a77b AL |
1572 | /* Make room for "NMI executing". */ |
1573 | pushq $0 | |
3f3c8b8c | 1574 | |
0b22930e | 1575 | /* Leave room for the "iret" frame */ |
4d732138 | 1576 | subq $(5*8), %rsp |
28696f43 | 1577 | |
0b22930e | 1578 | /* Copy the "original" frame to the "outermost" frame */ |
3f3c8b8c | 1579 | .rept 5 |
4d732138 | 1580 | pushq 11*8(%rsp) |
3f3c8b8c | 1581 | .endr |
8c1f7558 | 1582 | UNWIND_HINT_IRET_REGS |
62610913 | 1583 | |
79fb4ad6 SR |
1584 | /* Everything up to here is safe from nested NMIs */ |
1585 | ||
a97439aa AL |
1586 | #ifdef CONFIG_DEBUG_ENTRY |
1587 | /* | |
1588 | * For ease of testing, unmask NMIs right away. Disabled by | |
1589 | * default because IRET is very expensive. | |
1590 | */ | |
1591 | pushq $0 /* SS */ | |
1592 | pushq %rsp /* RSP (minus 8 because of the previous push) */ | |
1593 | addq $8, (%rsp) /* Fix up RSP */ | |
1594 | pushfq /* RFLAGS */ | |
1595 | pushq $__KERNEL_CS /* CS */ | |
1596 | pushq $1f /* RIP */ | |
929bacec | 1597 | iretq /* continues at repeat_nmi below */ |
8c1f7558 | 1598 | UNWIND_HINT_IRET_REGS |
a97439aa AL |
1599 | 1: |
1600 | #endif | |
1601 | ||
0b22930e | 1602 | repeat_nmi: |
62610913 JB |
1603 | /* |
1604 | * If there was a nested NMI, the first NMI's iret will return | |
1605 | * here. But NMIs are still enabled and we can take another | |
1606 | * nested NMI. The nested NMI checks the interrupted RIP to see | |
1607 | * if it is between repeat_nmi and end_repeat_nmi, and if so | |
1608 | * it will just return, as we are about to repeat an NMI anyway. | |
1609 | * This makes it safe to copy to the stack frame that a nested | |
1610 | * NMI will update. | |
0b22930e AL |
1611 | * |
1612 | * RSP is pointing to "outermost RIP". gsbase is unknown, but, if | |
1613 | * we're repeating an NMI, gsbase has the same value that it had on | |
1614 | * the first iteration. paranoid_entry will load the kernel | |
36f1a77b AL |
1615 | * gsbase if needed before we call do_nmi. "NMI executing" |
1616 | * is zero. | |
62610913 | 1617 | */ |
36f1a77b | 1618 | movq $1, 10*8(%rsp) /* Set "NMI executing". */ |
3f3c8b8c | 1619 | |
62610913 | 1620 | /* |
0b22930e AL |
1621 | * Copy the "outermost" frame to the "iret" frame. NMIs that nest |
1622 | * here must not modify the "iret" frame while we're writing to | |
1623 | * it or it will end up containing garbage. | |
62610913 | 1624 | */ |
4d732138 | 1625 | addq $(10*8), %rsp |
3f3c8b8c | 1626 | .rept 5 |
4d732138 | 1627 | pushq -6*8(%rsp) |
3f3c8b8c | 1628 | .endr |
4d732138 | 1629 | subq $(5*8), %rsp |
62610913 | 1630 | end_repeat_nmi: |
3f3c8b8c SR |
1631 | |
1632 | /* | |
0b22930e AL |
1633 | * Everything below this point can be preempted by a nested NMI. |
1634 | * If this happens, then the inner NMI will change the "iret" | |
1635 | * frame to point back to repeat_nmi. | |
3f3c8b8c | 1636 | */ |
4d732138 | 1637 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
76f5df43 | 1638 | |
1fd466ef | 1639 | /* |
ebfc453e | 1640 | * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit |
1fd466ef SR |
1641 | * as we should not be calling schedule in NMI context. |
1642 | * Even with normal interrupts enabled. An NMI should not be | |
1643 | * setting NEED_RESCHED or anything that normal interrupts and | |
1644 | * exceptions might do. | |
1645 | */ | |
4d732138 | 1646 | call paranoid_entry |
8c1f7558 | 1647 | UNWIND_HINT_REGS |
7fbb98c5 | 1648 | |
ddeb8f21 | 1649 | /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ |
4d732138 IM |
1650 | movq %rsp, %rdi |
1651 | movq $-1, %rsi | |
1652 | call do_nmi | |
7fbb98c5 | 1653 | |
16561f27 | 1654 | /* Always restore stashed CR3 value (see paranoid_entry) */ |
21e94459 | 1655 | RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 |
8a09317b | 1656 | |
4d732138 IM |
1657 | testl %ebx, %ebx /* swapgs needed? */ |
1658 | jnz nmi_restore | |
ddeb8f21 AH |
1659 | nmi_swapgs: |
1660 | SWAPGS_UNSAFE_STACK | |
1661 | nmi_restore: | |
502af0d7 | 1662 | POP_REGS |
0b22930e | 1663 | |
471ee483 AL |
1664 | /* |
1665 | * Skip orig_ax and the "outermost" frame to point RSP at the "iret" | |
1666 | * at the "iret" frame. | |
1667 | */ | |
1668 | addq $6*8, %rsp | |
28696f43 | 1669 | |
810bc075 AL |
1670 | /* |
1671 | * Clear "NMI executing". Set DF first so that we can easily | |
1672 | * distinguish the remaining code between here and IRET from | |
929bacec AL |
1673 | * the SYSCALL entry and exit paths. |
1674 | * | |
1675 | * We arguably should just inspect RIP instead, but I (Andy) wrote | |
1676 | * this code when I had the misapprehension that Xen PV supported | |
1677 | * NMIs, and Xen PV would break that approach. | |
810bc075 AL |
1678 | */ |
1679 | std | |
1680 | movq $0, 5*8(%rsp) /* clear "NMI executing" */ | |
0b22930e AL |
1681 | |
1682 | /* | |
929bacec AL |
1683 | * iretq reads the "iret" frame and exits the NMI stack in a |
1684 | * single instruction. We are returning to kernel mode, so this | |
1685 | * cannot result in a fault. Similarly, we don't need to worry | |
1686 | * about espfix64 on the way back to kernel mode. | |
0b22930e | 1687 | */ |
929bacec | 1688 | iretq |
ddeb8f21 AH |
1689 | END(nmi) |
1690 | ||
1691 | ENTRY(ignore_sysret) | |
8c1f7558 | 1692 | UNWIND_HINT_EMPTY |
4d732138 | 1693 | mov $-ENOSYS, %eax |
ddeb8f21 | 1694 | sysret |
ddeb8f21 | 1695 | END(ignore_sysret) |
2deb4be2 AL |
1696 | |
1697 | ENTRY(rewind_stack_do_exit) | |
8c1f7558 | 1698 | UNWIND_HINT_FUNC |
2deb4be2 AL |
1699 | /* Prevent any naive code from trying to unwind to our caller. */ |
1700 | xorl %ebp, %ebp | |
1701 | ||
1702 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rax | |
8c1f7558 JP |
1703 | leaq -PTREGS_SIZE(%rax), %rsp |
1704 | UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE | |
2deb4be2 AL |
1705 | |
1706 | call do_exit | |
2deb4be2 | 1707 | END(rewind_stack_do_exit) |