]>
Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
05830204 VS |
2 | #ifndef _ASM_X86_INTEL_RDT_SCHED_H |
3 | #define _ASM_X86_INTEL_RDT_SCHED_H | |
4 | ||
5 | #ifdef CONFIG_INTEL_RDT | |
6 | ||
7 | #include <linux/sched.h> | |
8 | #include <linux/jump_label.h> | |
9 | ||
10 | #define IA32_PQR_ASSOC 0x0c8f | |
11 | ||
12 | /** | |
13 | * struct intel_pqr_state - State cache for the PQR MSR | |
a9110b55 VS |
14 | * @cur_rmid: The cached Resource Monitoring ID |
15 | * @cur_closid: The cached Class Of Service ID | |
16 | * @default_rmid: The user assigned Resource Monitoring ID | |
17 | * @default_closid: The user assigned cached Class Of Service ID | |
05830204 VS |
18 | * |
19 | * The upper 32 bits of IA32_PQR_ASSOC contain closid and the | |
20 | * lower 10 bits rmid. The update to IA32_PQR_ASSOC always | |
748b6b88 VS |
21 | * contains both parts, so we need to cache them. This also |
22 | * stores the user configured per cpu CLOSID and RMID. | |
05830204 VS |
23 | * |
24 | * The cache also helps to avoid pointless updates if the value does | |
25 | * not change. | |
26 | */ | |
27 | struct intel_pqr_state { | |
a9110b55 VS |
28 | u32 cur_rmid; |
29 | u32 cur_closid; | |
30 | u32 default_rmid; | |
31 | u32 default_closid; | |
05830204 VS |
32 | }; |
33 | ||
34 | DECLARE_PER_CPU(struct intel_pqr_state, pqr_state); | |
4be6c078 VS |
35 | |
36 | DECLARE_STATIC_KEY_FALSE(rdt_enable_key); | |
1b5c0b75 | 37 | DECLARE_STATIC_KEY_FALSE(rdt_alloc_enable_key); |
748b6b88 | 38 | DECLARE_STATIC_KEY_FALSE(rdt_mon_enable_key); |
05830204 VS |
39 | |
40 | /* | |
748b6b88 | 41 | * __intel_rdt_sched_in() - Writes the task's CLOSid/RMID to IA32_PQR_MSR |
05830204 VS |
42 | * |
43 | * Following considerations are made so that this has minimal impact | |
44 | * on scheduler hot path: | |
45 | * - This will stay as no-op unless we are running on an Intel SKU | |
748b6b88 VS |
46 | * which supports resource control or monitoring and we enable by |
47 | * mounting the resctrl file system. | |
48 | * - Caches the per cpu CLOSid/RMID values and does the MSR write only | |
49 | * when a task with a different CLOSid/RMID is scheduled in. | |
50 | * - We allocate RMIDs/CLOSids globally in order to keep this as | |
51 | * simple as possible. | |
05830204 VS |
52 | * Must be called with preemption disabled. |
53 | */ | |
748b6b88 | 54 | static void __intel_rdt_sched_in(void) |
05830204 | 55 | { |
a9110b55 VS |
56 | struct intel_pqr_state *state = this_cpu_ptr(&pqr_state); |
57 | u32 closid = state->default_closid; | |
58 | u32 rmid = state->default_rmid; | |
748b6b88 VS |
59 | |
60 | /* | |
61 | * If this task has a closid/rmid assigned, use it. | |
62 | * Else use the closid/rmid assigned to this cpu. | |
63 | */ | |
1b5c0b75 | 64 | if (static_branch_likely(&rdt_alloc_enable_key)) { |
748b6b88 | 65 | if (current->closid) |
a9110b55 | 66 | closid = current->closid; |
748b6b88 | 67 | } |
05830204 | 68 | |
748b6b88 VS |
69 | if (static_branch_likely(&rdt_mon_enable_key)) { |
70 | if (current->rmid) | |
a9110b55 | 71 | rmid = current->rmid; |
748b6b88 | 72 | } |
05830204 | 73 | |
a9110b55 VS |
74 | if (closid != state->cur_closid || rmid != state->cur_rmid) { |
75 | state->cur_closid = closid; | |
76 | state->cur_rmid = rmid; | |
77 | wrmsr(IA32_PQR_ASSOC, rmid, closid); | |
05830204 VS |
78 | } |
79 | } | |
80 | ||
4be6c078 VS |
81 | static inline void intel_rdt_sched_in(void) |
82 | { | |
83 | if (static_branch_likely(&rdt_enable_key)) | |
84 | __intel_rdt_sched_in(); | |
85 | } | |
86 | ||
05830204 VS |
87 | #else |
88 | ||
89 | static inline void intel_rdt_sched_in(void) {} | |
90 | ||
91 | #endif /* CONFIG_INTEL_RDT */ | |
92 | ||
93 | #endif /* _ASM_X86_INTEL_RDT_SCHED_H */ |