[mirror_ubuntu-disco-kernel.git] / arch / x86 / include / asm / io.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_IO_H
#define _ASM_X86_IO_H

/*
 * This file contains the definitions for the x86 IO instructions
 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
 * versions of the single-IO instructions (inb_p/inw_p/..).
 *
 * This file is not meant to be obfuscating: it's just complicated
 * to (a) handle it all in a way that makes gcc able to optimize it
 * as well as possible and (b) trying to avoid writing the same thing
 * over and over again with slight variations and possibly making a
 * mistake somewhere.
 */

/*
 * Thanks to James van Artsdalen for a better timing-fix than
 * the two short jumps: using outb's to a nonexistent port seems
 * to guarantee better timings even on fast machines.
 *
 * On the other hand, I'd like to be sure of a non-existent port:
 * I feel a bit unsafe about using 0x80 (should be safe, though)
 *
 *		Linus
 */

 /*
  *  Bit simplified and optimized by Jan Hubicka
  *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
  *
  *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
  *  isa_read[wl] and isa_write[wl] fixed
  *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
  */

#define ARCH_HAS_IOREMAP_WC
#define ARCH_HAS_IOREMAP_WT

#include <linux/string.h>
#include <linux/compiler.h>
#include <asm/page.h>
#include <asm/early_ioremap.h>
#include <asm/pgtable_types.h>

#define build_mmio_read(name, size, type, reg, barrier) \
static inline type name(const volatile void __iomem *addr) \
{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \
:"m" (*(volatile type __force *)addr) barrier); return ret; }

#define build_mmio_write(name, size, type, reg, barrier) \
static inline void name(type val, volatile void __iomem *addr) \
{ asm volatile("mov" size " %0,%1": :reg (val), \
"m" (*(volatile type __force *)addr) barrier); }

build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
build_mmio_read(readl, "l", unsigned int, "=r", :"memory")

build_mmio_read(__readb, "b", unsigned char, "=q", )
build_mmio_read(__readw, "w", unsigned short, "=r", )
build_mmio_read(__readl, "l", unsigned int, "=r", )

build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
build_mmio_write(writew, "w", unsigned short, "r", :"memory")
build_mmio_write(writel, "l", unsigned int, "r", :"memory")

build_mmio_write(__writeb, "b", unsigned char, "q", )
build_mmio_write(__writew, "w", unsigned short, "r", )
build_mmio_write(__writel, "l", unsigned int, "r", )

#define readb readb
#define readw readw
#define readl readl
#define readb_relaxed(a) __readb(a)
#define readw_relaxed(a) __readw(a)
#define readl_relaxed(a) __readl(a)
#define __raw_readb __readb
#define __raw_readw __readw
#define __raw_readl __readl

#define writeb writeb
#define writew writew
#define writel writel
#define writeb_relaxed(v, a) __writeb(v, a)
#define writew_relaxed(v, a) __writew(v, a)
#define writel_relaxed(v, a) __writel(v, a)
#define __raw_writeb __writeb
#define __raw_writew __writew
#define __raw_writel __writel

#define mmiowb() barrier()

#ifdef CONFIG_X86_64

build_mmio_read(readq, "q", u64, "=r", :"memory")
build_mmio_read(__readq, "q", u64, "=r", )
build_mmio_write(writeq, "q", u64, "r", :"memory")
build_mmio_write(__writeq, "q", u64, "r", )

#define readq_relaxed(a)	__readq(a)
#define writeq_relaxed(v, a)	__writeq(v, a)

#define __raw_readq		__readq
#define __raw_writeq		__writeq

/* Let people know that we have them */
#define readq			readq
#define writeq			writeq

#endif

#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);

/**
 *	virt_to_phys	-	map virtual addresses to physical
 *	@address: address to remap
 *
 *	The returned physical address is the physical (CPU) mapping for
 *	the memory address given. It is only valid to use this function on
 *	addresses directly mapped or allocated via kmalloc.
 *
 *	This function does not give bus mappings for DMA transfers. In
 *	almost all conceivable cases a device driver should not be using
 *	this function
 */

static inline phys_addr_t virt_to_phys(volatile void *address)
{
	return __pa(address);
}
#define virt_to_phys virt_to_phys

/**
 *	phys_to_virt	-	map physical address to virtual
 *	@address: address to remap
 *
 *	The returned virtual address is a current CPU mapping for
 *	the memory address given. It is only valid to use this function on
 *	addresses that have a kernel mapping
 *
 *	This function does not handle bus mappings for DMA transfers. In
 *	almost all conceivable cases a device driver should not be using
 *	this function
 */

static inline void *phys_to_virt(phys_addr_t address)
{
	return __va(address);
}
#define phys_to_virt phys_to_virt

/*
 * Change "struct page" to physical address.
 */
#define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)

/*
 * ISA I/O bus memory addresses are 1:1 with the physical address.
 * However, we truncate the address to unsigned int to avoid undesirable
 * promitions in legacy drivers.
 */
static inline unsigned int isa_virt_to_bus(volatile void *address)
{
	return (unsigned int)virt_to_phys(address);
}
#define isa_page_to_bus(page)	((unsigned int)page_to_phys(page))
#define isa_bus_to_virt		phys_to_virt

/*
 * However PCI ones are not necessarily 1:1 and therefore these interfaces
 * are forbidden in portable PCI drivers.
 *
 * Allow them on x86 for legacy drivers, though.
 */
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt

/*
 * The default ioremap() behavior is non-cached; if you need something
 * else, you probably want one of the following.
 */
extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
#define ioremap_nocache ioremap_nocache
extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size);
#define ioremap_uc ioremap_uc
extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
#define ioremap_cache ioremap_cache
extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val);
#define ioremap_prot ioremap_prot
extern void __iomem *ioremap_encrypted(resource_size_t phys_addr, unsigned long size);
#define ioremap_encrypted ioremap_encrypted

/**
 * ioremap     -   map bus memory into CPU space
 * @offset:    bus address of the memory
 * @size:      size of the resource to map
 *
 * ioremap performs a platform specific sequence of operations to
 * make bus memory CPU accessible via the readb/readw/readl/writeb/
 * writew/writel functions and the other mmio helpers. The returned
 * address is not guaranteed to be usable directly as a virtual
 * address.
 *
 * If the area you are trying to map is a PCI BAR you should have a
 * look at pci_iomap().
 */
static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
{
	return ioremap_nocache(offset, size);
}
#define ioremap ioremap

extern void iounmap(volatile void __iomem *addr);
#define iounmap iounmap

extern void set_iounmap_nonlazy(void);

#ifdef __KERNEL__

void memcpy_fromio(void *, const volatile void __iomem *, size_t);
void memcpy_toio(volatile void __iomem *, const void *, size_t);
void memset_io(volatile void __iomem *, int, size_t);

#define memcpy_fromio memcpy_fromio
#define memcpy_toio memcpy_toio
#define memset_io memset_io

#include <asm-generic/iomap.h>

/*
 * ISA space is 'always mapped' on a typical x86 system, no need to
 * explicitly ioremap() it. The fact that the ISA IO space is mapped
 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
 * are physical addresses. The following constant pointer can be
 * used as the IO-area pointer (it can be iounmapped as well, so the
 * analogy with PCI is quite large):
 */
#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))

#endif /* __KERNEL__ */

extern void native_io_delay(void);

extern int io_delay_type;
extern void io_delay_init(void);

#if defined(CONFIG_PARAVIRT)
#include <asm/paravirt.h>
#else

static inline void slow_down_io(void)
{
	native_io_delay();
#ifdef REALLY_SLOW_IO
	native_io_delay();
	native_io_delay();
	native_io_delay();
#endif
}

#endif

#ifdef CONFIG_AMD_MEM_ENCRYPT
#include <linux/jump_label.h>

extern struct static_key_false sev_enable_key;
static inline bool sev_key_active(void)
{
	return static_branch_unlikely(&sev_enable_key);
}

#else /* !CONFIG_AMD_MEM_ENCRYPT */

static inline bool sev_key_active(void) { return false; }

#endif /* CONFIG_AMD_MEM_ENCRYPT */

#define BUILDIO(bwl, bw, type)						\
static inline void out##bwl(unsigned type value, int port)		\
{									\
	asm volatile("out" #bwl " %" #bw "0, %w1"			\
		     : : "a"(value), "Nd"(port));			\
}									\
									\
static inline unsigned type in##bwl(int port)				\
{									\
	unsigned type value;						\
	asm volatile("in" #bwl " %w1, %" #bw "0"			\
		     : "=a"(value) : "Nd"(port));			\
	return value;							\
}									\
									\
static inline void out##bwl##_p(unsigned type value, int port)		\
{									\
	out##bwl(value, port);						\
	slow_down_io();							\
}									\
									\
static inline unsigned type in##bwl##_p(int port)			\
{									\
	unsigned type value = in##bwl(port);				\
	slow_down_io();							\
	return value;							\
}									\
									\
static inline void outs##bwl(int port, const void *addr, unsigned long count) \
{									\
	if (sev_key_active()) {						\
		unsigned type *value = (unsigned type *)addr;		\
		while (count) {						\
			out##bwl(*value, port);				\
			value++;					\
			count--;					\
		}							\
	} else {							\
		asm volatile("rep; outs" #bwl				\
			     : "+S"(addr), "+c"(count)			\
			     : "d"(port) : "memory");			\
	}								\
}									\
									\
static inline void ins##bwl(int port, void *addr, unsigned long count)	\
{									\
	if (sev_key_active()) {						\
		unsigned type *value = (unsigned type *)addr;		\
		while (count) {						\
			*value = in##bwl(port);				\
			value++;					\
			count--;					\
		}							\
	} else {							\
		asm volatile("rep; ins" #bwl				\
			     : "+D"(addr), "+c"(count)			\
			     : "d"(port) : "memory");			\
	}								\
}

BUILDIO(b, b, char)
BUILDIO(w, w, short)
BUILDIO(l, , int)

#define inb inb
#define inw inw
#define inl inl
#define inb_p inb_p
#define inw_p inw_p
#define inl_p inl_p
#define insb insb
#define insw insw
#define insl insl

#define outb outb
#define outw outw
#define outl outl
#define outb_p outb_p
#define outw_p outw_p
#define outl_p outl_p
#define outsb outsb
#define outsw outsw
#define outsl outsl

extern void *xlate_dev_mem_ptr(phys_addr_t phys);
extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);

#define xlate_dev_mem_ptr xlate_dev_mem_ptr
#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr

extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
				enum page_cache_mode pcm);
extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
#define ioremap_wc ioremap_wc
extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size);
#define ioremap_wt ioremap_wt

extern bool is_early_ioremap_ptep(pte_t *ptep);

#define IO_SPACE_LIMIT 0xffff

#include <asm-generic/io.h>
#undef PCI_IOBASE

#ifdef CONFIG_MTRR
extern int __must_check arch_phys_wc_index(int handle);
#define arch_phys_wc_index arch_phys_wc_index

extern int __must_check arch_phys_wc_add(unsigned long base,
					 unsigned long size);
extern void arch_phys_wc_del(int handle);
#define arch_phys_wc_add arch_phys_wc_add
#endif

#ifdef CONFIG_X86_PAT
extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size);
extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size);
#define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc
#endif

extern bool arch_memremap_can_ram_remap(resource_size_t offset,
					unsigned long size,
					unsigned long flags);
#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap

extern bool phys_mem_access_encrypted(unsigned long phys_addr,
				      unsigned long size);

#endif /* _ASM_X86_IO_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1965aae3 PA	2	#ifndef _ASM_X86_IO_H
1965aae3 PA	3	#define _ASM_X86_IO_H
e045fb2a	4
1c5b9069 BG	5	/*
	6	* This file contains the definitions for the x86 IO instructions
	7	* inb/inw/inl/outb/outw/outl and the "string versions" of the same
	8	* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
	9	* versions of the single-IO instructions (inb_p/inw_p/..).
	10	*
	11	* This file is not meant to be obfuscating: it's just complicated
	12	* to (a) handle it all in a way that makes gcc able to optimize it
	13	* as well as possible and (b) trying to avoid writing the same thing
	14	* over and over again with slight variations and possibly making a
	15	* mistake somewhere.
	16	*/
	17
	18	/*
	19	* Thanks to James van Artsdalen for a better timing-fix than
	20	* the two short jumps: using outb's to a nonexistent port seems
	21	* to guarantee better timings even on fast machines.
	22	*
	23	* On the other hand, I'd like to be sure of a non-existent port:
	24	* I feel a bit unsafe about using 0x80 (should be safe, though)
	25	*
	26	* Linus
	27	*/
	28
	29	/*
	30	* Bit simplified and optimized by Jan Hubicka
	31	* Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
	32	*
	33	* isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
	34	* isa_read[wl] and isa_write[wl] fixed
	35	* - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
	36	*/
	37
b310f381	38	#define ARCH_HAS_IOREMAP_WC
d838270e	39	#define ARCH_HAS_IOREMAP_WT
b310f381	40
1c5b9069	41	#include <linux/string.h>
c1f64a58	42	#include <linux/compiler.h>
976e8f67	43	#include <asm/page.h>
5b7c73e0	44	#include <asm/early_ioremap.h>
d6472302	45	#include <asm/pgtable_types.h>
c1f64a58 LT	46
	47	#define build_mmio_read(name, size, type, reg, barrier) \
	48	static inline type name(const volatile void __iomem *addr) \
1c5b0eb6	49	{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \
c1f64a58 LT	50	:"m" ((volatile type __force )addr) barrier); return ret; }
	51
	52	#define build_mmio_write(name, size, type, reg, barrier) \
	53	static inline void name(type val, volatile void __iomem *addr) \
	54	{ asm volatile("mov" size " %0,%1": :reg (val), \
	55	"m" ((volatile type __force )addr) barrier); }
	56
1c5b0eb6 MP	57	build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
	58	build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
	59	build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
c1f64a58	60
1c5b0eb6 MP	61	build_mmio_read(__readb, "b", unsigned char, "=q", )
	62	build_mmio_read(__readw, "w", unsigned short, "=r", )
	63	build_mmio_read(__readl, "l", unsigned int, "=r", )
c1f64a58 LT	64
	65	build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
	66	build_mmio_write(writew, "w", unsigned short, "r", :"memory")
	67	build_mmio_write(writel, "l", unsigned int, "r", :"memory")
	68
	69	build_mmio_write(__writeb, "b", unsigned char, "q", )
	70	build_mmio_write(__writew, "w", unsigned short, "r", )
	71	build_mmio_write(__writel, "l", unsigned int, "r", )
	72
80b9ece1 AS	73	#define readb readb
	74	#define readw readw
	75	#define readl readl
c1f64a58 LT	76	#define readb_relaxed(a) __readb(a)
	77	#define readw_relaxed(a) __readw(a)
	78	#define readl_relaxed(a) __readl(a)
	79	#define __raw_readb __readb
	80	#define __raw_readw __readw
	81	#define __raw_readl __readl
	82
80b9ece1 AS	83	#define writeb writeb
	84	#define writew writew
	85	#define writel writel
cbc908ef WD	86	#define writeb_relaxed(v, a) __writeb(v, a)
	87	#define writew_relaxed(v, a) __writew(v, a)
	88	#define writel_relaxed(v, a) __writel(v, a)
c1f64a58 LT	89	#define __raw_writeb __writeb
	90	#define __raw_writew __writew
	91	#define __raw_writel __writel
	92
	93	#define mmiowb() barrier()
	94
	95	#ifdef CONFIG_X86_64
93093d09	96
6469a0ee AS	97	build_mmio_read(readq, "q", u64, "=r", :"memory")
	98	build_mmio_read(__readq, "q", u64, "=r", )
	99	build_mmio_write(writeq, "q", u64, "r", :"memory")
	100	build_mmio_write(__writeq, "q", u64, "r", )
c1f64a58	101
9683a64f AS	102	#define readq_relaxed(a) __readq(a)
9683a64f AS	103	#define writeq_relaxed(v, a) __writeq(v, a)
93093d09	104
9683a64f AS	105	#define __raw_readq __readq
9683a64f AS	106	#define __raw_writeq __writeq
93093d09	107
a0b1131e	108	/* Let people know that we have them */
93093d09 IM	109	#define readq readq
93093d09 IM	110	#define writeq writeq
2c5643b1	111
dbee8a0a RD	112	#endif
dbee8a0a RD	113
be62a320 CB	114	#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
	115	extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
	116	extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
	117
976e8f67 JF	118	/**
	119	* virt_to_phys - map virtual addresses to physical
	120	* @address: address to remap
	121	*
	122	* The returned physical address is the physical (CPU) mapping for
	123	* the memory address given. It is only valid to use this function on
	124	* addresses directly mapped or allocated via kmalloc.
	125	*
	126	* This function does not give bus mappings for DMA transfers. In
	127	* almost all conceivable cases a device driver should not be using
	128	* this function
	129	*/
	130
	131	static inline phys_addr_t virt_to_phys(volatile void *address)
	132	{
	133	return __pa(address);
	134	}
80b9ece1	135	#define virt_to_phys virt_to_phys
976e8f67 JF	136
	137	/**
	138	* phys_to_virt - map physical address to virtual
	139	* @address: address to remap
	140	*
	141	* The returned virtual address is a current CPU mapping for
	142	* the memory address given. It is only valid to use this function on
	143	* addresses that have a kernel mapping
	144	*
	145	* This function does not handle bus mappings for DMA transfers. In
	146	* almost all conceivable cases a device driver should not be using
	147	* this function
	148	*/
	149
	150	static inline void *phys_to_virt(phys_addr_t address)
	151	{
	152	return __va(address);
	153	}
80b9ece1	154	#define phys_to_virt phys_to_virt
976e8f67 JF	155
	156	/*
	157	* Change "struct page" to physical address.
	158	*/
	159	#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
	160
	161	/*
	162	* ISA I/O bus memory addresses are 1:1 with the physical address.
a7eb5189 PA	163	* However, we truncate the address to unsigned int to avoid undesirable
a7eb5189 PA	164	* promitions in legacy drivers.
976e8f67	165	*/
a7eb5189 PA	166	static inline unsigned int isa_virt_to_bus(volatile void *address)
	167	{
	168	return (unsigned int)virt_to_phys(address);
	169	}
	170	#define isa_page_to_bus(page) ((unsigned int)page_to_phys(page))
	171	#define isa_bus_to_virt phys_to_virt
976e8f67 JF	172
	173	/*
	174	* However PCI ones are not necessarily 1:1 and therefore these interfaces
	175	* are forbidden in portable PCI drivers.
	176	*
	177	* Allow them on x86 for legacy drivers, though.
	178	*/
	179	#define virt_to_bus virt_to_phys
	180	#define bus_to_virt phys_to_virt
	181
f5857666 JC	182	/*
	183	* The default ioremap() behavior is non-cached; if you need something
	184	* else, you probably want one of the following.
	185	*/
	186	extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
80b9ece1	187	#define ioremap_nocache ioremap_nocache
f5857666 JC	188	extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size);
f5857666 JC	189	#define ioremap_uc ioremap_uc
f5857666	190	extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
80b9ece1	191	#define ioremap_cache ioremap_cache
f5857666	192	extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val);
80b9ece1	193	#define ioremap_prot ioremap_prot
c3a7a61c LJ	194	extern void __iomem *ioremap_encrypted(resource_size_t phys_addr, unsigned long size);
c3a7a61c LJ	195	#define ioremap_encrypted ioremap_encrypted
f5857666	196
133822c5 JF	197	/**
	198	* ioremap - map bus memory into CPU space
	199	* @offset: bus address of the memory
	200	* @size: size of the resource to map
	201	*
	202	* ioremap performs a platform specific sequence of operations to
	203	* make bus memory CPU accessible via the readb/readw/readl/writeb/
	204	* writew/writel functions and the other mmio helpers. The returned
	205	* address is not guaranteed to be usable directly as a virtual
	206	* address.
	207	*
	208	* If the area you are trying to map is a PCI BAR you should have a
	209	* look at pci_iomap().
	210	*/
133822c5 JF	211	static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
	212	{
	213	return ioremap_nocache(offset, size);
	214	}
80b9ece1	215	#define ioremap ioremap
133822c5 JF	216
133822c5 JF	217	extern void iounmap(volatile void __iomem *addr);
80b9ece1	218	#define iounmap iounmap
133822c5	219
3ee48b6a	220	extern void set_iounmap_nonlazy(void);
9321b8cb	221
1c5b9069 BG	222	#ifdef __KERNEL__
1c5b9069 BG	223
170d13ca LT	224	void memcpy_fromio(void , const volatile void __iomem , size_t);
	225	void memcpy_toio(volatile void __iomem , const void , size_t);
	226	void memset_io(volatile void __iomem *, int, size_t);
	227
	228	#define memcpy_fromio memcpy_fromio
	229	#define memcpy_toio memcpy_toio
	230	#define memset_io memset_io
	231
1c5b9069 BG	232	#include <asm-generic/iomap.h>
1c5b9069 BG	233
1c5b9069 BG	234	/*
	235	* ISA space is 'always mapped' on a typical x86 system, no need to
	236	* explicitly ioremap() it. The fact that the ISA IO space is mapped
	237	* to PAGE_OFFSET is pure coincidence - it does not mean ISA values
	238	* are physical addresses. The following constant pointer can be
	239	* used as the IO-area pointer (it can be iounmapped as well, so the
	240	* analogy with PCI is quite large):
	241	*/
	242	#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
	243
1c5b9069 BG	244	#endif /* __KERNEL__ */
	245
	246	extern void native_io_delay(void);
	247
	248	extern int io_delay_type;
	249	extern void io_delay_init(void);
	250
	251	#if defined(CONFIG_PARAVIRT)
	252	#include <asm/paravirt.h>
96a388de	253	#else
1c5b9069 BG	254
	255	static inline void slow_down_io(void)
	256	{
	257	native_io_delay();
	258	#ifdef REALLY_SLOW_IO
	259	native_io_delay();
	260	native_io_delay();
	261	native_io_delay();
96a388de	262	#endif
1c5b9069 BG	263	}
	264
	265	#endif
	266
606b21d4 TL	267	#ifdef CONFIG_AMD_MEM_ENCRYPT
	268	#include <linux/jump_label.h>
	269
	270	extern struct static_key_false sev_enable_key;
	271	static inline bool sev_key_active(void)
	272	{
	273	return static_branch_unlikely(&sev_enable_key);
	274	}
	275
	276	#else /* !CONFIG_AMD_MEM_ENCRYPT */
	277
	278	static inline bool sev_key_active(void) { return false; }
	279
	280	#endif /* CONFIG_AMD_MEM_ENCRYPT */
	281
1c5b9069 BG	282	#define BUILDIO(bwl, bw, type) \
	283	static inline void out##bwl(unsigned type value, int port) \
	284	{ \
	285	asm volatile("out" #bwl " %" #bw "0, %w1" \
	286	: : "a"(value), "Nd"(port)); \
	287	} \
	288	\
	289	static inline unsigned type in##bwl(int port) \
	290	{ \
	291	unsigned type value; \
	292	asm volatile("in" #bwl " %w1, %" #bw "0" \
	293	: "=a"(value) : "Nd"(port)); \
	294	return value; \
	295	} \
	296	\
	297	static inline void out##bwl##_p(unsigned type value, int port) \
	298	{ \
	299	out##bwl(value, port); \
	300	slow_down_io(); \
	301	} \
	302	\
	303	static inline unsigned type in##bwl##_p(int port) \
	304	{ \
	305	unsigned type value = in##bwl(port); \
	306	slow_down_io(); \
	307	return value; \
	308	} \
	309	\
	310	static inline void outs##bwl(int port, const void *addr, unsigned long count) \
	311	{ \
606b21d4 TL	312	if (sev_key_active()) { \
	313	unsigned type value = (unsigned type )addr; \
	314	while (count) { \
	315	out##bwl(*value, port); \
	316	value++; \
	317	count--; \
	318	} \
	319	} else { \
	320	asm volatile("rep; outs" #bwl \
	321	: "+S"(addr), "+c"(count) \
	322	: "d"(port) : "memory"); \
	323	} \
1c5b9069 BG	324	} \
	325	\
	326	static inline void ins##bwl(int port, void *addr, unsigned long count) \
	327	{ \
606b21d4 TL	328	if (sev_key_active()) { \
	329	unsigned type value = (unsigned type )addr; \
	330	while (count) { \
	331	*value = in##bwl(port); \
	332	value++; \
	333	count--; \
	334	} \
	335	} else { \
	336	asm volatile("rep; ins" #bwl \
	337	: "+D"(addr), "+c"(count) \
	338	: "d"(port) : "memory"); \
	339	} \
1c5b9069 BG	340	}
	341
	342	BUILDIO(b, b, char)
	343	BUILDIO(w, w, short)
	344	BUILDIO(l, , int)
e045fb2a	345
80b9ece1 AS	346	#define inb inb
	347	#define inw inw
	348	#define inl inl
	349	#define inb_p inb_p
	350	#define inw_p inw_p
	351	#define inl_p inl_p
	352	#define insb insb
	353	#define insw insw
	354	#define insl insl
	355
	356	#define outb outb
	357	#define outw outw
	358	#define outl outl
	359	#define outb_p outb_p
	360	#define outw_p outw_p
	361	#define outl_p outl_p
	362	#define outsb outsb
	363	#define outsw outsw
	364	#define outsl outsl
	365
4707a341 TR	366	extern void *xlate_dev_mem_ptr(phys_addr_t phys);
4707a341 TR	367	extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
e045fb2a	368
80b9ece1 AS	369	#define xlate_dev_mem_ptr xlate_dev_mem_ptr
	370	#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
	371
3a96ce8c	372	extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
b14097bd	373	enum page_cache_mode pcm);
d639bab8	374	extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
80b9ece1	375	#define ioremap_wc ioremap_wc
d838270e	376	extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size);
80b9ece1	377	#define ioremap_wt ioremap_wt
3a96ce8c	378
fef5ba79	379	extern bool is_early_ioremap_ptep(pte_t *ptep);
4583ed51	380
a448720c	381	#define IO_SPACE_LIMIT 0xffff
4583ed51	382
31952011 AS	383	#include <asm-generic/io.h>
	384	#undef PCI_IOBASE
	385
d0d98eed	386	#ifdef CONFIG_MTRR
7d010fdf LR	387	extern int __must_check arch_phys_wc_index(int handle);
	388	#define arch_phys_wc_index arch_phys_wc_index
	389
d0d98eed AL	390	extern int __must_check arch_phys_wc_add(unsigned long base,
	391	unsigned long size);
	392	extern void arch_phys_wc_del(int handle);
	393	#define arch_phys_wc_add arch_phys_wc_add
	394	#endif
	395
8ef42276 DA	396	#ifdef CONFIG_X86_PAT
	397	extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size);
	398	extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size);
	399	#define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc
	400	#endif
	401
8f716c9b TL	402	extern bool arch_memremap_can_ram_remap(resource_size_t offset,
	403	unsigned long size,
	404	unsigned long flags);
	405	#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
	406
8458bf94 TL	407	extern bool phys_mem_access_encrypted(unsigned long phys_addr,
	408	unsigned long size);
	409
1965aae3	410	#endif /* _ASM_X86_IO_H */