[mirror_ubuntu-disco-kernel.git] / arch / x86 / include / asm / io_apic.h

#ifndef _ASM_X86_IO_APIC_H
#define _ASM_X86_IO_APIC_H

#include <linux/types.h>
#include <asm/mpspec.h>
#include <asm/apicdef.h>
#include <asm/irq_vectors.h>
#include <asm/x86_init.h>
/*
 * Intel IO-APIC support for SMP and UP systems.
 *
 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
 */

/* I/O Unit Redirection Table */
#define IO_APIC_REDIR_VECTOR_MASK	0x000FF
#define IO_APIC_REDIR_DEST_LOGICAL	0x00800
#define IO_APIC_REDIR_DEST_PHYSICAL	0x00000
#define IO_APIC_REDIR_SEND_PENDING	(1 << 12)
#define IO_APIC_REDIR_REMOTE_IRR	(1 << 14)
#define IO_APIC_REDIR_LEVEL_TRIGGER	(1 << 15)
#define IO_APIC_REDIR_MASKED		(1 << 16)

/*
 * The structure of the IO-APIC:
 */
union IO_APIC_reg_00 {
	u32	raw;
	struct {
		u32	__reserved_2	: 14,
			LTS		:  1,
			delivery_type	:  1,
			__reserved_1	:  8,
			ID		:  8;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_01 {
	u32	raw;
	struct {
		u32	version		:  8,
			__reserved_2	:  7,
			PRQ		:  1,
			entries		:  8,
			__reserved_1	:  8;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_02 {
	u32	raw;
	struct {
		u32	__reserved_2	: 24,
			arbitration	:  4,
			__reserved_1	:  4;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_03 {
	u32	raw;
	struct {
		u32	boot_DT		:  1,
			__reserved_1	: 31;
	} __attribute__ ((packed)) bits;
};

struct IO_APIC_route_entry {
	__u32	vector		:  8,
		delivery_mode	:  3,	/* 000: FIXED
					 * 001: lowest prio
					 * 111: ExtINT
					 */
		dest_mode	:  1,	/* 0: physical, 1: logical */
		delivery_status	:  1,
		polarity	:  1,
		irr		:  1,
		trigger		:  1,	/* 0: edge, 1: level */
		mask		:  1,	/* 0: enabled, 1: disabled */
		__reserved_2	: 15;

	__u32	__reserved_3	: 24,
		dest		:  8;
} __attribute__ ((packed));

struct IR_IO_APIC_route_entry {
	__u64	vector		: 8,
		zero		: 3,
		index2		: 1,
		delivery_status : 1,
		polarity	: 1,
		irr		: 1,
		trigger		: 1,
		mask		: 1,
		reserved	: 31,
		format		: 1,
		index		: 15;
} __attribute__ ((packed));

#define IOAPIC_AUTO     -1
#define IOAPIC_EDGE     0
#define IOAPIC_LEVEL    1

#ifdef CONFIG_X86_IO_APIC

/*
 * # of IO-APICs and # of IRQ routing registers
 */
extern int nr_ioapics;

extern int mpc_ioapic_id(int ioapic);
extern unsigned int mpc_ioapic_addr(int ioapic);
extern struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic);

#define MP_MAX_IOAPIC_PIN 127

/* # of MP IRQ source entries */
extern int mp_irq_entries;

/* MP IRQ source entries */
extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];

/* Older SiS APIC requires we rewrite the index register */
extern int sis_apic_bug;

/* 1 if "noapic" boot option passed */
extern int skip_ioapic_setup;

/* 1 if "noapic" boot option passed */
extern int noioapicquirk;

/* -1 if "noapic" boot option passed */
extern int noioapicreroute;

/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
extern int timer_through_8259;

/*
 * If we use the IO-APIC for IRQ routing, disable automatic
 * assignment of PCI IRQ's.
 */
#define io_apic_assign_pci_irqs \
	(mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)

struct io_apic_irq_attr;
struct irq_cfg;
extern int io_apic_set_pci_routing(struct device *dev, int irq,
		 struct io_apic_irq_attr *irq_attr);
void setup_IO_APIC_irq_extra(u32 gsi);
extern void ioapic_insert_resources(void);

extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *,
				     unsigned int, int,
				     struct io_apic_irq_attr *);
extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *,
				     unsigned int, int,
				     struct io_apic_irq_attr *);
extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg);

extern void native_compose_msi_msg(struct pci_dev *pdev,
				   unsigned int irq, unsigned int dest,
				   struct msi_msg *msg, u8 hpet_id);
extern void native_eoi_ioapic_pin(int apic, int pin, int vector);
int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);

extern int save_ioapic_entries(void);
extern void mask_ioapic_entries(void);
extern int restore_ioapic_entries(void);

extern void setup_ioapic_ids_from_mpc(void);
extern void setup_ioapic_ids_from_mpc_nocheck(void);

struct mp_ioapic_gsi{
	u32 gsi_base;
	u32 gsi_end;
};
extern struct mp_ioapic_gsi  mp_gsi_routing[];
extern u32 gsi_top;
int mp_find_ioapic(u32 gsi);
int mp_find_ioapic_pin(int ioapic, u32 gsi);
void __init mp_register_ioapic(int id, u32 address, u32 gsi_base);
extern void __init pre_init_apic_IRQ0(void);

extern void mp_save_irq(struct mpc_intsrc *m);

extern void disable_ioapic_support(void);

extern void __init native_io_apic_init_mappings(void);
extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
extern void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int val);
extern void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
extern void native_disable_io_apic(void);
extern void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries);
extern void intel_ir_io_apic_print_entries(unsigned int apic, unsigned int nr_entries);
extern int native_ioapic_set_affinity(struct irq_data *,
				      const struct cpumask *,
				      bool);

static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
{
	return x86_io_apic_ops.read(apic, reg);
}

static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
{
	x86_io_apic_ops.write(apic, reg, value);
}
static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
{
	x86_io_apic_ops.modify(apic, reg, value);
}

extern void io_apic_eoi(unsigned int apic, unsigned int vector);

#else  /* !CONFIG_X86_IO_APIC */

#define io_apic_assign_pci_irqs 0
#define setup_ioapic_ids_from_mpc x86_init_noop
static const int timer_through_8259 = 0;
static inline void ioapic_insert_resources(void) { }
#define gsi_top (NR_IRQS_LEGACY)
static inline int mp_find_ioapic(u32 gsi) { return 0; }

struct io_apic_irq_attr;
static inline int io_apic_set_pci_routing(struct device *dev, int irq,
		 struct io_apic_irq_attr *irq_attr) { return 0; }

static inline int save_ioapic_entries(void)
{
	return -ENOMEM;
}

static inline void mask_ioapic_entries(void) { }
static inline int restore_ioapic_entries(void)
{
	return -ENOMEM;
}

static inline void mp_save_irq(struct mpc_intsrc *m) { };
static inline void disable_ioapic_support(void) { }
#define native_io_apic_init_mappings	NULL
#define native_io_apic_read		NULL
#define native_io_apic_write		NULL
#define native_io_apic_modify		NULL
#define native_disable_io_apic		NULL
#define native_io_apic_print_entries	NULL
#define native_ioapic_set_affinity	NULL
#define native_setup_ioapic_entry	NULL
#define native_compose_msi_msg		NULL
#define native_eoi_ioapic_pin		NULL
#endif

#endif /* _ASM_X86_IO_APIC_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_IO_APIC_H
1965aae3 PA	2	#define _ASM_X86_IO_APIC_H
e1d91978	3
a1a33fa3	4	#include <linux/types.h>
e1d91978 TG	5	#include <asm/mpspec.h>
e1d91978 TG	6	#include <asm/apicdef.h>
9d6a4d08	7	#include <asm/irq_vectors.h>
4a8e2a31	8	#include <asm/x86_init.h>
e1d91978 TG	9	/*
	10	* Intel IO-APIC support for SMP and UP systems.
	11	*
	12	* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
	13	*/
	14
d3f020d2 CG	15	/* I/O Unit Redirection Table */
	16	#define IO_APIC_REDIR_VECTOR_MASK 0x000FF
	17	#define IO_APIC_REDIR_DEST_LOGICAL 0x00800
	18	#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
	19	#define IO_APIC_REDIR_SEND_PENDING (1 << 12)
	20	#define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
	21	#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
	22	#define IO_APIC_REDIR_MASKED (1 << 16)
	23
e1d91978 TG	24	/*
	25	* The structure of the IO-APIC:
	26	*/
	27	union IO_APIC_reg_00 {
	28	u32 raw;
	29	struct {
	30	u32 __reserved_2 : 14,
	31	LTS : 1,
	32	delivery_type : 1,
	33	__reserved_1 : 8,
	34	ID : 8;
	35	} __attribute__ ((packed)) bits;
	36	};
	37
	38	union IO_APIC_reg_01 {
	39	u32 raw;
	40	struct {
	41	u32 version : 8,
	42	__reserved_2 : 7,
	43	PRQ : 1,
	44	entries : 8,
	45	__reserved_1 : 8;
	46	} __attribute__ ((packed)) bits;
	47	};
	48
	49	union IO_APIC_reg_02 {
	50	u32 raw;
	51	struct {
	52	u32 __reserved_2 : 24,
	53	arbitration : 4,
	54	__reserved_1 : 4;
	55	} __attribute__ ((packed)) bits;
	56	};
	57
	58	union IO_APIC_reg_03 {
	59	u32 raw;
	60	struct {
	61	u32 boot_DT : 1,
	62	__reserved_1 : 31;
	63	} __attribute__ ((packed)) bits;
	64	};
	65
e1d91978 TG	66	struct IO_APIC_route_entry {
	67	__u32 vector : 8,
	68	delivery_mode : 3, /* 000: FIXED
	69	* 001: lowest prio
	70	* 111: ExtINT
	71	*/
	72	dest_mode : 1, /* 0: physical, 1: logical */
	73	delivery_status : 1,
	74	polarity : 1,
	75	irr : 1,
	76	trigger : 1, /* 0: edge, 1: level */
	77	mask : 1, /* 0: enabled, 1: disabled */
	78	__reserved_2 : 15;
	79
e1d91978 TG	80	__u32 __reserved_3 : 24,
e1d91978 TG	81	dest : 8;
e1d91978	82	} __attribute__ ((packed));
e1d91978	83
89027d35 SS	84	struct IR_IO_APIC_route_entry {
	85	__u64 vector : 8,
	86	zero : 3,
	87	index2 : 1,
	88	delivery_status : 1,
	89	polarity : 1,
	90	irr : 1,
	91	trigger : 1,
	92	mask : 1,
	93	reserved : 31,
	94	format : 1,
	95	index : 15;
e1d91978 TG	96	} __attribute__ ((packed));
e1d91978 TG	97
abb00522 TG	98	#define IOAPIC_AUTO -1
	99	#define IOAPIC_EDGE 0
	100	#define IOAPIC_LEVEL 1
	101
e1d91978 TG	102	#ifdef CONFIG_X86_IO_APIC
	103
	104	/*
	105	* # of IO-APICs and # of IRQ routing registers
	106	*/
	107	extern int nr_ioapics;
e1d91978	108
d5371430 SS	109	extern int mpc_ioapic_id(int ioapic);
d5371430 SS	110	extern unsigned int mpc_ioapic_addr(int ioapic);
c040aaeb	111	extern struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic);
a1a33fa3	112
d5371430	113	#define MP_MAX_IOAPIC_PIN 127
e1d91978 TG	114
	115	/* # of MP IRQ source entries */
	116	extern int mp_irq_entries;
	117
	118	/* MP IRQ source entries */
c2c21745	119	extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
e1d91978	120
e1d91978 TG	121	/* Older SiS APIC requires we rewrite the index register */
	122	extern int sis_apic_bug;
	123
	124	/* 1 if "noapic" boot option passed */
	125	extern int skip_ioapic_setup;
	126
a9322f64 SA	127	/* 1 if "noapic" boot option passed */
	128	extern int noioapicquirk;
	129
9197979b SA	130	/* -1 if "noapic" boot option passed */
	131	extern int noioapicreroute;
	132
35542c5e MR	133	/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
	134	extern int timer_through_8259;
	135
e1d91978 TG	136	/*
	137	* If we use the IO-APIC for IRQ routing, disable automatic
	138	* assignment of PCI IRQ's.
	139	*/
	140	#define io_apic_assign_pci_irqs \
	141	(mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
	142
e5198075	143	struct io_apic_irq_attr;
9b1b0e42	144	struct irq_cfg;
e5198075 YL	145	extern int io_apic_set_pci_routing(struct device *dev, int irq,
e5198075 YL	146	struct io_apic_irq_attr *irq_attr);
18dce6ba	147	void setup_IO_APIC_irq_extra(u32 gsi);
857fdc53	148	extern void ioapic_insert_resources(void);
e1d91978	149
a6a25dd3 JR	150	extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *,
	151	unsigned int, int,
	152	struct io_apic_irq_attr *);
9b1b0e42 JR	153	extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *,
	154	unsigned int, int,
	155	struct io_apic_irq_attr *);
	156	extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg);
a6a25dd3	157
7601384f JR	158	extern void native_compose_msi_msg(struct pci_dev *pdev,
	159	unsigned int irq, unsigned int dest,
	160	struct msi_msg *msg, u8 hpet_id);
da165322	161	extern void native_eoi_ioapic_pin(int apic, int pin, int vector);
20443598	162	int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
ff973d04	163
31dce14a SS	164	extern int save_ioapic_entries(void);
	165	extern void mask_ioapic_entries(void);
	166	extern int restore_ioapic_entries(void);
4dc2f96c	167
de934103	168	extern void setup_ioapic_ids_from_mpc(void);
a38c5380	169	extern void setup_ioapic_ids_from_mpc_nocheck(void);
2a4ab640 FT	170
2a4ab640 FT	171	struct mp_ioapic_gsi{
eddb0c55 EB	172	u32 gsi_base;
eddb0c55 EB	173	u32 gsi_end;
2a4ab640 FT	174	};
2a4ab640 FT	175	extern struct mp_ioapic_gsi mp_gsi_routing[];
a4384df3	176	extern u32 gsi_top;
eddb0c55 EB	177	int mp_find_ioapic(u32 gsi);
eddb0c55 EB	178	int mp_find_ioapic_pin(int ioapic, u32 gsi);
2a4ab640	179	void __init mp_register_ioapic(int id, u32 address, u32 gsi_base);
05ddafb1	180	extern void __init pre_init_apic_IRQ0(void);
2a4ab640	181
2d8009ba FT	182	extern void mp_save_irq(struct mpc_intsrc *m);
2d8009ba FT	183
7167d08e HK	184	extern void disable_ioapic_support(void);
7167d08e HK	185
4a8e2a31 KRW	186	extern void __init native_io_apic_init_mappings(void);
	187	extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
	188	extern void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int val);
	189	extern void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
1c4248ca	190	extern void native_disable_io_apic(void);
afcc8a40 JR	191	extern void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries);
afcc8a40 JR	192	extern void intel_ir_io_apic_print_entries(unsigned int apic, unsigned int nr_entries);
373dd7a2 JR	193	extern int native_ioapic_set_affinity(struct irq_data *,
	194	const struct cpumask *,
	195	bool);
4a8e2a31 KRW	196
	197	static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
	198	{
	199	return x86_io_apic_ops.read(apic, reg);
	200	}
	201
	202	static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
	203	{
	204	x86_io_apic_ops.write(apic, reg, value);
	205	}
	206	static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
	207	{
	208	x86_io_apic_ops.modify(apic, reg, value);
	209	}
da165322 JR	210
	211	extern void io_apic_eoi(unsigned int apic, unsigned int vector);
	212
e1d91978	213	#else /* !CONFIG_X86_IO_APIC */
78f28b7c	214
e1d91978	215	#define io_apic_assign_pci_irqs 0
de934103	216	#define setup_ioapic_ids_from_mpc x86_init_noop
35542c5e	217	static const int timer_through_8259 = 0;
857fdc53	218	static inline void ioapic_insert_resources(void) { }
a4384df3	219	#define gsi_top (NR_IRQS_LEGACY)
eddb0c55	220	static inline int mp_find_ioapic(u32 gsi) { return 0; }
78f28b7c	221
4966e1af JP	222	struct io_apic_irq_attr;
	223	static inline int io_apic_set_pci_routing(struct device *dev, int irq,
	224	struct io_apic_irq_attr *irq_attr) { return 0; }
7d0f1926	225
31dce14a	226	static inline int save_ioapic_entries(void)
7d0f1926 HK	227	{
	228	return -ENOMEM;
	229	}
	230
31dce14a SS	231	static inline void mask_ioapic_entries(void) { }
31dce14a SS	232	static inline int restore_ioapic_entries(void)
7d0f1926 HK	233	{
	234	return -ENOMEM;
	235	}
	236
b6a1432d	237	static inline void mp_save_irq(struct mpc_intsrc *m) { };
7167d08e	238	static inline void disable_ioapic_support(void) { }
4a8e2a31 KRW	239	#define native_io_apic_init_mappings NULL
	240	#define native_io_apic_read NULL
	241	#define native_io_apic_write NULL
	242	#define native_io_apic_modify NULL
1c4248ca	243	#define native_disable_io_apic NULL
afcc8a40	244	#define native_io_apic_print_entries NULL
373dd7a2	245	#define native_ioapic_set_affinity NULL
a6a25dd3	246	#define native_setup_ioapic_entry NULL
7601384f	247	#define native_compose_msi_msg NULL
da165322	248	#define native_eoi_ioapic_pin NULL
96a388de	249	#endif
e1d91978	250
1965aae3	251	#endif /* _ASM_X86_IO_APIC_H */