]>
Commit | Line | Data |
---|---|---|
1965aae3 PA |
1 | #ifndef _ASM_X86_IPI_H |
2 | #define _ASM_X86_IPI_H | |
1da177e4 | 3 | |
d53e2f28 IM |
4 | #ifdef CONFIG_X86_LOCAL_APIC |
5 | ||
1da177e4 LT |
6 | /* |
7 | * Copyright 2004 James Cleverdon, IBM. | |
8 | * Subject to the GNU Public License, v.2 | |
9 | * | |
10 | * Generic APIC InterProcessor Interrupt code. | |
11 | * | |
12 | * Moved to include file by James Cleverdon from | |
13 | * arch/x86-64/kernel/smp.c | |
14 | * | |
15 | * Copyrights from kernel/smp.c: | |
16 | * | |
17 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
18 | * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com> | |
19 | * (c) 2002,2003 Andi Kleen, SuSE Labs. | |
20 | * Subject to the GNU Public License, v.2 | |
21 | */ | |
22 | ||
1da177e4 | 23 | #include <asm/hw_irq.h> |
00f1ea69 | 24 | #include <asm/apic.h> |
e3f8ba81 | 25 | #include <asm/smp.h> |
1da177e4 LT |
26 | |
27 | /* | |
28 | * the following functions deal with sending IPIs between CPUs. | |
29 | * | |
30 | * We use 'broadcast', CPU->CPU IPIs and self-IPIs too. | |
31 | */ | |
32 | ||
061b3d90 JP |
33 | static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector, |
34 | unsigned int dest) | |
1da177e4 | 35 | { |
1a426cb7 JB |
36 | unsigned int icr = shortcut | dest; |
37 | ||
38 | switch (vector) { | |
39 | default: | |
40 | icr |= APIC_DM_FIXED | vector; | |
41 | break; | |
42 | case NMI_VECTOR: | |
1a426cb7 JB |
43 | icr |= APIC_DM_NMI; |
44 | break; | |
45 | } | |
1da177e4 LT |
46 | return icr; |
47 | } | |
48 | ||
061b3d90 | 49 | static inline int __prepare_ICR2(unsigned int mask) |
1da177e4 LT |
50 | { |
51 | return SET_APIC_DEST_FIELD(mask); | |
52 | } | |
53 | ||
1b374e4d SS |
54 | static inline void __xapic_wait_icr_idle(void) |
55 | { | |
56 | while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY) | |
57 | cpu_relax(); | |
58 | } | |
59 | ||
dac5f412 | 60 | static inline void |
d53e2f28 | 61 | __default_send_IPI_shortcut(unsigned int shortcut, int vector, unsigned int dest) |
1da177e4 LT |
62 | { |
63 | /* | |
64 | * Subtle. In the case of the 'never do double writes' workaround | |
65 | * we have to lock out interrupts to be safe. As we don't care | |
66 | * of the value read we use an atomic rmw access to avoid costly | |
67 | * cli/sti. Otherwise we use an even cheaper single atomic write | |
68 | * to the APIC. | |
69 | */ | |
70 | unsigned int cfg; | |
71 | ||
72 | /* | |
73 | * Wait for idle. | |
74 | */ | |
1b374e4d | 75 | __xapic_wait_icr_idle(); |
1da177e4 LT |
76 | |
77 | /* | |
78 | * No need to touch the target chip field | |
79 | */ | |
80 | cfg = __prepare_ICR(shortcut, vector, dest); | |
81 | ||
82 | /* | |
83 | * Send the IPI. The write to APIC_ICR fires this off. | |
84 | */ | |
1b374e4d | 85 | native_apic_mem_write(APIC_ICR, cfg); |
1da177e4 LT |
86 | } |
87 | ||