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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
6ce60b07 TG |
2 | /* |
3 | * Machine dependent access functions for RTC registers. | |
4 | */ | |
1965aae3 PA |
5 | #ifndef _ASM_X86_MC146818RTC_H |
6 | #define _ASM_X86_MC146818RTC_H | |
6ce60b07 TG |
7 | |
8 | #include <asm/io.h> | |
6ce60b07 | 9 | #include <asm/processor.h> |
6ce60b07 TG |
10 | |
11 | #ifndef RTC_PORT | |
12 | #define RTC_PORT(x) (0x70 + (x)) | |
13 | #define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ | |
14 | #endif | |
15 | ||
b08ee5f7 | 16 | #if defined(CONFIG_X86_32) |
6ce60b07 TG |
17 | /* |
18 | * This lock provides nmi access to the CMOS/RTC registers. It has some | |
19 | * special properties. It is owned by a CPU and stores the index register | |
20 | * currently being accessed (if owned). The idea here is that it works | |
21 | * like a normal lock (normally). However, in an NMI, the NMI code will | |
22 | * first check to see if its CPU owns the lock, meaning that the NMI | |
23 | * interrupted during the read/write of the device. If it does, it goes ahead | |
24 | * and performs the access and then restores the index register. If it does | |
25 | * not, it locks normally. | |
26 | * | |
27 | * Note that since we are working with NMIs, we need this lock even in | |
28 | * a non-SMP machine just to mark that the lock is owned. | |
29 | * | |
30 | * This only works with compare-and-swap. There is no other way to | |
31 | * atomically claim the lock and set the owner. | |
32 | */ | |
33 | #include <linux/smp.h> | |
34 | extern volatile unsigned long cmos_lock; | |
35 | ||
36 | /* | |
37 | * All of these below must be called with interrupts off, preempt | |
38 | * disabled, etc. | |
39 | */ | |
40 | ||
41 | static inline void lock_cmos(unsigned char reg) | |
42 | { | |
43 | unsigned long new; | |
933a4415 | 44 | new = ((smp_processor_id() + 1) << 8) | reg; |
6ce60b07 TG |
45 | for (;;) { |
46 | if (cmos_lock) { | |
47 | cpu_relax(); | |
48 | continue; | |
49 | } | |
50 | if (__cmpxchg(&cmos_lock, 0, new, sizeof(cmos_lock)) == 0) | |
51 | return; | |
52 | } | |
53 | } | |
54 | ||
55 | static inline void unlock_cmos(void) | |
56 | { | |
57 | cmos_lock = 0; | |
58 | } | |
933a4415 | 59 | |
6ce60b07 TG |
60 | static inline int do_i_have_lock_cmos(void) |
61 | { | |
933a4415 | 62 | return (cmos_lock >> 8) == (smp_processor_id() + 1); |
6ce60b07 | 63 | } |
933a4415 | 64 | |
6ce60b07 TG |
65 | static inline unsigned char current_lock_cmos_reg(void) |
66 | { | |
67 | return cmos_lock & 0xff; | |
68 | } | |
933a4415 JP |
69 | |
70 | #define lock_cmos_prefix(reg) \ | |
6ce60b07 TG |
71 | do { \ |
72 | unsigned long cmos_flags; \ | |
73 | local_irq_save(cmos_flags); \ | |
74 | lock_cmos(reg) | |
933a4415 JP |
75 | |
76 | #define lock_cmos_suffix(reg) \ | |
77 | unlock_cmos(); \ | |
78 | local_irq_restore(cmos_flags); \ | |
6ce60b07 | 79 | } while (0) |
96a388de | 80 | #else |
6ce60b07 TG |
81 | #define lock_cmos_prefix(reg) do {} while (0) |
82 | #define lock_cmos_suffix(reg) do {} while (0) | |
1affc46c JJ |
83 | #define lock_cmos(reg) do { } while (0) |
84 | #define unlock_cmos() do { } while (0) | |
6ce60b07 TG |
85 | #define do_i_have_lock_cmos() 0 |
86 | #define current_lock_cmos_reg() 0 | |
96a388de | 87 | #endif |
6ce60b07 TG |
88 | |
89 | /* | |
90 | * The yet supported machines all access the RTC index register via | |
91 | * an ISA port access but the way to access the date register differs ... | |
92 | */ | |
93 | #define CMOS_READ(addr) rtc_cmos_read(addr) | |
94 | #define CMOS_WRITE(val, addr) rtc_cmos_write(val, addr) | |
95 | unsigned char rtc_cmos_read(unsigned char addr); | |
96 | void rtc_cmos_write(unsigned char val, unsigned char addr); | |
97 | ||
e27c4929 AB |
98 | extern int mach_set_rtc_mmss(const struct timespec64 *now); |
99 | extern void mach_get_cmos_time(struct timespec64 *now); | |
fe599f9f | 100 | |
6ce60b07 TG |
101 | #define RTC_IRQ 8 |
102 | ||
1965aae3 | 103 | #endif /* _ASM_X86_MC146818RTC_H */ |