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1965aae3 PA |
1 | #ifndef _ASM_X86_MSR_H |
2 | #define _ASM_X86_MSR_H | |
be7baf80 | 3 | |
af170c50 | 4 | #include <uapi/asm/msr.h> |
be7baf80 | 5 | |
8f12dea6 | 6 | #ifndef __ASSEMBLY__ |
c210d249 GOC |
7 | |
8 | #include <asm/asm.h> | |
9 | #include <asm/errno.h> | |
6bc1096d BP |
10 | #include <asm/cpumask.h> |
11 | ||
12 | struct msr { | |
13 | union { | |
14 | struct { | |
15 | u32 l; | |
16 | u32 h; | |
17 | }; | |
18 | u64 q; | |
19 | }; | |
20 | }; | |
c210d249 | 21 | |
6ede31e0 BP |
22 | struct msr_info { |
23 | u32 msr_no; | |
24 | struct msr reg; | |
25 | struct msr *msrs; | |
26 | int err; | |
27 | }; | |
28 | ||
29 | struct msr_regs_info { | |
30 | u32 *regs; | |
31 | int err; | |
32 | }; | |
33 | ||
1e160cc3 | 34 | static inline unsigned long long native_read_tscp(unsigned int *aux) |
8f12dea6 GOC |
35 | { |
36 | unsigned long low, high; | |
abb0ade0 JP |
37 | asm volatile(".byte 0x0f,0x01,0xf9" |
38 | : "=a" (low), "=d" (high), "=c" (*aux)); | |
41aefdcc | 39 | return low | ((u64)high << 32); |
8f12dea6 GOC |
40 | } |
41 | ||
c210d249 | 42 | /* |
d4f1b103 JS |
43 | * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" |
44 | * constraint has different meanings. For i386, "A" means exactly | |
45 | * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, | |
46 | * it means rax *or* rdx. | |
c210d249 GOC |
47 | */ |
48 | #ifdef CONFIG_X86_64 | |
49 | #define DECLARE_ARGS(val, low, high) unsigned low, high | |
abb0ade0 | 50 | #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) |
c210d249 GOC |
51 | #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) |
52 | #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) | |
53 | #else | |
54 | #define DECLARE_ARGS(val, low, high) unsigned long long val | |
55 | #define EAX_EDX_VAL(val, low, high) (val) | |
56 | #define EAX_EDX_ARGS(val, low, high) "A" (val) | |
57 | #define EAX_EDX_RET(val, low, high) "=A" (val) | |
8f12dea6 GOC |
58 | #endif |
59 | ||
be7baf80 TG |
60 | static inline unsigned long long native_read_msr(unsigned int msr) |
61 | { | |
c210d249 | 62 | DECLARE_ARGS(val, low, high); |
be7baf80 | 63 | |
c210d249 GOC |
64 | asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); |
65 | return EAX_EDX_VAL(val, low, high); | |
be7baf80 TG |
66 | } |
67 | ||
68 | static inline unsigned long long native_read_msr_safe(unsigned int msr, | |
69 | int *err) | |
70 | { | |
c210d249 | 71 | DECLARE_ARGS(val, low, high); |
be7baf80 | 72 | |
08970fc4 | 73 | asm volatile("2: rdmsr ; xor %[err],%[err]\n" |
be7baf80 TG |
74 | "1:\n\t" |
75 | ".section .fixup,\"ax\"\n\t" | |
08970fc4 | 76 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
be7baf80 | 77 | ".previous\n\t" |
abb0ade0 | 78 | _ASM_EXTABLE(2b, 3b) |
08970fc4 | 79 | : [err] "=r" (*err), EAX_EDX_RET(val, low, high) |
0cc0213e | 80 | : "c" (msr), [fault] "i" (-EIO)); |
c210d249 | 81 | return EAX_EDX_VAL(val, low, high); |
be7baf80 TG |
82 | } |
83 | ||
c9dcda5c GOC |
84 | static inline void native_write_msr(unsigned int msr, |
85 | unsigned low, unsigned high) | |
be7baf80 | 86 | { |
af2b1c60 | 87 | asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
be7baf80 TG |
88 | } |
89 | ||
0ca59dd9 FW |
90 | /* Can be uninlined because referenced by paravirt */ |
91 | notrace static inline int native_write_msr_safe(unsigned int msr, | |
c9dcda5c | 92 | unsigned low, unsigned high) |
be7baf80 TG |
93 | { |
94 | int err; | |
08970fc4 | 95 | asm volatile("2: wrmsr ; xor %[err],%[err]\n" |
be7baf80 TG |
96 | "1:\n\t" |
97 | ".section .fixup,\"ax\"\n\t" | |
08970fc4 | 98 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
be7baf80 | 99 | ".previous\n\t" |
abb0ade0 | 100 | _ASM_EXTABLE(2b, 3b) |
08970fc4 | 101 | : [err] "=a" (err) |
c9dcda5c | 102 | : "c" (msr), "0" (low), "d" (high), |
0cc0213e | 103 | [fault] "i" (-EIO) |
af2b1c60 | 104 | : "memory"); |
be7baf80 TG |
105 | return err; |
106 | } | |
107 | ||
cdc7957d | 108 | extern unsigned long long native_read_tsc(void); |
be7baf80 | 109 | |
1f975f78 AP |
110 | extern int rdmsr_safe_regs(u32 regs[8]); |
111 | extern int wrmsr_safe_regs(u32 regs[8]); | |
132ec92f | 112 | |
92767af0 IM |
113 | static __always_inline unsigned long long __native_read_tsc(void) |
114 | { | |
115 | DECLARE_ARGS(val, low, high); | |
116 | ||
92767af0 | 117 | asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); |
92767af0 IM |
118 | |
119 | return EAX_EDX_VAL(val, low, high); | |
120 | } | |
121 | ||
b8d1fae7 | 122 | static inline unsigned long long native_read_pmc(int counter) |
be7baf80 | 123 | { |
c210d249 GOC |
124 | DECLARE_ARGS(val, low, high); |
125 | ||
126 | asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); | |
127 | return EAX_EDX_VAL(val, low, high); | |
be7baf80 TG |
128 | } |
129 | ||
130 | #ifdef CONFIG_PARAVIRT | |
131 | #include <asm/paravirt.h> | |
96a388de | 132 | #else |
be7baf80 TG |
133 | #include <linux/errno.h> |
134 | /* | |
135 | * Access to machine-specific registers (available on 586 and better only) | |
136 | * Note: the rd* operations modify the parameters directly (without using | |
137 | * pointer indirection), this allows gcc to optimize better | |
138 | */ | |
139 | ||
1423bed2 | 140 | #define rdmsr(msr, low, high) \ |
abb0ade0 JP |
141 | do { \ |
142 | u64 __val = native_read_msr((msr)); \ | |
1423bed2 BP |
143 | (void)((low) = (u32)__val); \ |
144 | (void)((high) = (u32)(__val >> 32)); \ | |
abb0ade0 | 145 | } while (0) |
be7baf80 | 146 | |
c9dcda5c | 147 | static inline void wrmsr(unsigned msr, unsigned low, unsigned high) |
be7baf80 | 148 | { |
c9dcda5c | 149 | native_write_msr(msr, low, high); |
be7baf80 TG |
150 | } |
151 | ||
abb0ade0 JP |
152 | #define rdmsrl(msr, val) \ |
153 | ((val) = native_read_msr((msr))) | |
be7baf80 | 154 | |
c210d249 | 155 | #define wrmsrl(msr, val) \ |
abb0ade0 | 156 | native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) |
be7baf80 TG |
157 | |
158 | /* wrmsr with exception handling */ | |
c9dcda5c | 159 | static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) |
be7baf80 | 160 | { |
c9dcda5c | 161 | return native_write_msr_safe(msr, low, high); |
be7baf80 TG |
162 | } |
163 | ||
060feb65 | 164 | /* rdmsr with exception handling */ |
1423bed2 | 165 | #define rdmsr_safe(msr, low, high) \ |
abb0ade0 JP |
166 | ({ \ |
167 | int __err; \ | |
168 | u64 __val = native_read_msr_safe((msr), &__err); \ | |
1423bed2 BP |
169 | (*low) = (u32)__val; \ |
170 | (*high) = (u32)(__val >> 32); \ | |
abb0ade0 JP |
171 | __err; \ |
172 | }) | |
be7baf80 | 173 | |
1de87bd4 AK |
174 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
175 | { | |
176 | int err; | |
177 | ||
178 | *p = native_read_msr_safe(msr, &err); | |
179 | return err; | |
180 | } | |
177fed1e | 181 | |
be7baf80 | 182 | #define rdtscl(low) \ |
205516c1 | 183 | ((low) = (u32)__native_read_tsc()) |
be7baf80 TG |
184 | |
185 | #define rdtscll(val) \ | |
205516c1 | 186 | ((val) = __native_read_tsc()) |
be7baf80 | 187 | |
abb0ade0 JP |
188 | #define rdpmc(counter, low, high) \ |
189 | do { \ | |
190 | u64 _l = native_read_pmc((counter)); \ | |
191 | (low) = (u32)_l; \ | |
192 | (high) = (u32)(_l >> 32); \ | |
193 | } while (0) | |
be7baf80 | 194 | |
1ff4d58a AK |
195 | #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) |
196 | ||
abb0ade0 JP |
197 | #define rdtscp(low, high, aux) \ |
198 | do { \ | |
199 | unsigned long long _val = native_read_tscp(&(aux)); \ | |
200 | (low) = (u32)_val; \ | |
201 | (high) = (u32)(_val >> 32); \ | |
202 | } while (0) | |
be7baf80 | 203 | |
c210d249 | 204 | #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux)) |
be7baf80 | 205 | |
c210d249 | 206 | #endif /* !CONFIG_PARAVIRT */ |
be7baf80 | 207 | |
715c85b1 | 208 | #define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val), \ |
abb0ade0 | 209 | (u32)((val) >> 32)) |
be7baf80 | 210 | |
1423bed2 | 211 | #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high)) |
be7baf80 | 212 | |
5df97400 | 213 | #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) |
be7baf80 | 214 | |
50542251 BP |
215 | struct msr *msrs_alloc(void); |
216 | void msrs_free(struct msr *msrs); | |
22085a66 BP |
217 | int msr_set_bit(u32 msr, u8 bit); |
218 | int msr_clear_bit(u32 msr, u8 bit); | |
50542251 | 219 | |
be7baf80 | 220 | #ifdef CONFIG_SMP |
c6f31932 PA |
221 | int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
222 | int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); | |
1a6b991a JP |
223 | int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
224 | int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); | |
b8a47541 BP |
225 | void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
226 | void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); | |
be7baf80 TG |
227 | int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
228 | int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); | |
1a6b991a JP |
229 | int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
230 | int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); | |
8b956bf1 PA |
231 | int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
232 | int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); | |
be7baf80 | 233 | #else /* CONFIG_SMP */ |
c6f31932 | 234 | static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) |
be7baf80 TG |
235 | { |
236 | rdmsr(msr_no, *l, *h); | |
c6f31932 | 237 | return 0; |
be7baf80 | 238 | } |
c6f31932 | 239 | static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
be7baf80 TG |
240 | { |
241 | wrmsr(msr_no, l, h); | |
c6f31932 | 242 | return 0; |
be7baf80 | 243 | } |
1a6b991a JP |
244 | static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
245 | { | |
246 | rdmsrl(msr_no, *q); | |
247 | return 0; | |
248 | } | |
249 | static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) | |
250 | { | |
251 | wrmsrl(msr_no, q); | |
252 | return 0; | |
253 | } | |
0d0fbbdd | 254 | static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
b034c19f BP |
255 | struct msr *msrs) |
256 | { | |
257 | rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); | |
258 | } | |
0d0fbbdd | 259 | static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
b034c19f BP |
260 | struct msr *msrs) |
261 | { | |
262 | wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); | |
263 | } | |
abb0ade0 JP |
264 | static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, |
265 | u32 *l, u32 *h) | |
be7baf80 TG |
266 | { |
267 | return rdmsr_safe(msr_no, l, h); | |
268 | } | |
269 | static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) | |
270 | { | |
271 | return wrmsr_safe(msr_no, l, h); | |
272 | } | |
1a6b991a JP |
273 | static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
274 | { | |
275 | return rdmsrl_safe(msr_no, q); | |
276 | } | |
277 | static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) | |
278 | { | |
279 | return wrmsrl_safe(msr_no, q); | |
280 | } | |
8b956bf1 PA |
281 | static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
282 | { | |
283 | return rdmsr_safe_regs(regs); | |
284 | } | |
285 | static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) | |
286 | { | |
287 | return wrmsr_safe_regs(regs); | |
288 | } | |
be7baf80 | 289 | #endif /* CONFIG_SMP */ |
ff55df53 | 290 | #endif /* __ASSEMBLY__ */ |
1965aae3 | 291 | #endif /* _ASM_X86_MSR_H */ |